SU1314386A1 - Content-addressable storage - Google Patents

Abstract

The invention relates to computing, in particular, to storage devices, and is intended for electronic digital computing systems. The purpose of the invention is to increase the speed of the device. The device contains drives 2, - 2 |, register 3 polls, groups of elements INEQUAL VALUE 4, - 4 ,, blocks 5, - 5d of permanent memory, accumulating adders 6d, counters 7, - 7, sorting matrix 8, register 9 of the search result . An increase in the device's speed when performing a search operation for words having a minimum code distance with respect to the interrogation attribute (search for the closest one according to Hemanchaus) is achieved by dividing the words of the argument array into equal parts and processing them in parallel. 2 Il. i (L with pirjmjnr jnr I I g g-- - J I I I Lfau L --- J —J. oe NU CO 00 C5 figure 1

Description

The invention relates to computing, in particular, to a storage device (RAM) - and is intended for electronic digital computing systems.

The purpose of the invention is to increase the speed of the device.

Figure 1 shows the functional diagram of the associative memory device; FIG. 2, page 1 of the control unit circuit.

The associative memory device contains a control block 1, a main 2 and an additional 2 drives, where k is an integer, register 3 polls, main 4, and additional 4, 4 c of the group of elements UNACTICAL, blocks 5d of permanent memory, where m is the number storing cells in each accumulator 2, accumulating adders 6, counters 7d, sorting matrix 8, register 9 of the search result. Matrix 8 contains m (L + P) -discharge cells 10 where ,, (N / K-); N is the register resolution of 3 polls; L and P, respectively, the lower and upper bits of the cells of the matrix 8.

The control unit 1 has outputs 11-15 and contains (FIG. 2) the operation code register 16, a clock pulse generator 17, a decryptor 18, a microprogram matrix 19 and a micro-command register 20. The sorting matrix 8 can be built on triggers and logic elements. Each of the counters 7 serves to count the incoming pulses to its input.

The device works as follows.

Argument array words are stored in the storage cells of drives 2, and the polling indication is in polling register 3, the N-bit words i of the argument array and the polling indication are divided into: k equal parts.

The storage cells of the accumulators 2 and the register 3 of the interrogation may have a different design (static or dynamic memory, shift registers, memory on a CMD, tracks of rotating magnetic memories, etc.). However, they must provide a sequential one-by-one reference, namely, when the next control pulse arrives at the control inputs of accumulator 2, the output of each memory cell is read.

Rare bit content of this cell. Similarly, when a control pulse arrives at the control input of the poll 3 register from the outputs

This bit register reads the next bits of each of the k parts of a poll tag.

When the search command that is nearest to Hamming arrives at the inputs of block 1 control, block 1 generates the following sequence of signals. At output 12 of block 1, a single signal is formed, which sets all bits of the register to zero.

 9 search results. After that, from outputs 11, 13, 14, 15, three- and three-level signals are sent to the control inputs of the interrogation register 3, accumulators 2, fixed memory blocks 5, adders 6, respectively. As a result, sequential sampling of the terminals 2 occurs. and register 3 polling of all bit slices of k parts of the words of the array argument and the poll sign, respectively. Bit slices of k parts of all words come from accumulator 2 to the first inputs of the corresponding elements NEVER 4; to the second inputs of which come from the outputs. Register 3 polling potentials of the corresponding bits of each of the k parts of the poll sign.

The signals of the mismatch of the bits of the i'th parts (, k) of numbers with the corresponding bits of the polling sign at the outputs of the i'th elements UNEQUAL VALUE 4 of the corresponding groups arrive: on the i-th address

the inputs of the corresponding blocks of the constant memory corresponding to each word of the argument array, on the outputs of which a code of the number of mismatches of the k bits of the words with the corresponding bits of the polling feature is generated.

The codes for the number of mismatches arriving at the inputs of adders 6 are summed and accumulated in adders 6, the transfer from which is fed to the input of the corresponding counters 7, thereby increasing their contents by one.

The duration of the clock pulse is determined by the maximum signal delay in the block 5 of the permanent memory, cyiviMaTOpe 6 and the counter 7. Then the signals arriving at the control inputs

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D1 of the fixed memory unit 5, the adder 6 and the counter 7, respectively, from outputs 13 and 14 of the control unit 1, ensure that the operation time of the blocks of the permanent memory, the adder 6 and the counter of 7 units, i.e. while the adder 6 and the counter 7 process the signal S-ro (S

N

1, 1) clock cycle; at the output of block 5 of the permanent memory, the code for the number of mismatches (S + l) -ro clock cycle is duplicated. After the adder 6 and the counter 7 process the N / K-ro signal of the clock, the sorting matrix 8 determines the word of the argument array nearest the Hamming to the poll sign, i.e. the unit at the output of the sorting matrix 8 corresponds to a word that has the minimum number of matches with a poll sign.

Claims (1)

Invention Formula An associative memory device that contains the poll register, main and additional drives, the main group of elements UNIMPLANITY, counters, sorting matrix, search result register and control unit, the first, second and third outputs of which are connected respectively to the control inputs of the accumulator, result register, search and poll register, the main output of which is connected to the first inputs of the elements 64 groups, the second inputs of which are connected to the outputs of the main storage unit, the outputs of the bits of the counters are connected to the inputs of the higher bits of the corresponding cells of the sorting matrix, the outputs of which are connected to the inputs of the search result register, of which the purpose of improving the speed of the device in it accumulative adders, fixed memory blocks and additional groups of elements are UNEQUAL, with the outputs of the fixed memory blocks connected to the information inputs of the corresponding accumulating adders, the accumulating overflow outputs of the accumulators are connected to the counters of the corresponding counters, and the outputs accumulating adders are connected to the low-order inputs of the corresponding cells of the sorting matrix; addressing the inputs of the corresponding blocks of permanent memory, the fourth and fifth outputs of the Single control are connected with the control inputs of the blocks permanent memory and accumulator. FIG. 2  if 15