SU1310897A1 - Super-fast-access storage - Google Patents

Abstract

The invention relates to computing, in particular, to storage devices for computers with high performance. The purpose of the invention is to increase the speed of the device. The ultra-fast memory (POP) contains blocks 1, -IK of address analysis, drives 2, -2 write signs, drives 3t-3 of data and block 12 controls. The RAM allows to reduce the time that the computer spends on accessing the random access memory (RAM) or external memory when processing program cycles or re-accessing the subroutines. A RAM is located between the RAM or the external memory of the computer and its central processing unit (CPU). Under the control of the CPU, which generates read and write signals, and also provides an address in the memory, the RAM performs these operations. At the same time, the RAM also performs the same operations, which, in addition, monitors the relationship between the current address supplied to the RAM from the CPU and the addresses of its high-speed drives 3 data, which were filled in during previous CPU accesses to the RAM. As soon as it determines that the CPU re-accesses a certain address area (which happens when processing program cycles or calling subroutines), it blocks the RAM reading cycle and issues data stored in one of the drives 3 at a high speed. 2 h. n. f-ly, 5 ill. i (L S 6 with 00 with FIG

Description

The invention relates to computing and, in particular, to storage devices for computers with high performance.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a block diagram of a super-fast storage device; in fig. 2 is a block diagram of the address analysis block; in fig. 3 is a block diagram of a recording feature accumulator; in fig. 4 is a block diagram of the control unit; in fig. 5 - a high-speed memory device as part of a computer.

The interoperative memory device (Fig. 1) contains blocks 1, address analysis, primary 2, and additional 2i-2k drives for recording attributes, primary 3 and additional 3r-3k data stores (where k is an integer). The device has inputs 4-8 and outputs 9 and 10. The device also contains switch And and control unit 12.

Each block of address analysis (Fig. 2) contains a register 13 of the starting address, a subtractor 14, and an NAND element 15.

Each drive 2 recording features (Fig. 3) contains a decryptor 16, triggers 17, switch 18, element OR-NOT 19 and element AND-NOT 20.

The control unit 12 (FIG. 4) contains an OR element 21, a delay element 22, an AND element 23, a delay element 24, a decoder 25, an AND-NE element 26, a counter 27, an AND element 28, an AND element 29, a delay element 30 , triggers 31 and 32.

The proposed super-operative storage device (POP) 33 (FIG. 5), during operation, interacts with the operative storage device (RAM) 34 and the central processor 35, which are included as well as the device 33 in the computer.

The device operates in two modes: write and read.

Recording mode

In this mode, the t-bit address of the record from the processor 35 is supplied to the RAM 34 and to the address input of the POPs 33. Then, the write data is sent to the RAM 34 and POPs 33. Next, a negative write pulse is applied, according to which the RAM 34 starts the write cycle. At the same time, this pulse, arriving at the input of the trigger 32, sets at its direct output a logical "O, which, arriving at the control input of the switch 11, connects the input 8 of the device to the information inputs of drives 3. In addition, this recording signal The mentor 29 and the delay element 30 cause a negative recording pulse at the recording inputs of the accumulators 3.

50

five

0

0

Q 5

The address of the entry entered at the address inputs of blocks 1 causes a sign to appear in one of the drives 3, if it is separated from the register of the initial address 13 by an amount not exceeding the length of the POP, that is, the hit condition can be written as follows: - TAi-2, (1)

where PHA is the contents of register 13 of the initial address of j-ro block 1; TA - current address; 2 - length of j-ro accumulator 3 (- number of address bits of j-ro accumulator 3).

Suppose that PHA and TA are of length t. If we now apply PHA and TA to the inputs of the subtractor 14, which has an output analysis circuit to zero (not shown in Fig. 2), then inequality (1) will be satisfied only if if its w-F senior outputs are equal to zero (output) in the state of logical "1 and there is no transfer from the higher bit (the output of Cn is in the state of logical" 1), i.e., the result of the subtraction is non-negative. In the case of a hit, the output of the result of the analysis of block 1 is in the state of logical zero. Consider two cases: there is no entry address in the address area of any of the drives 3; There is a hit in the address area of the drive 3j.

If there is no hit in the address area of drives 3, then the outputs of the results of the analysis of all blocks 1 are in the logical "1. Consequently, in spite of the arrival at the write inputs of the drives 3 of the write pulse, the write cycle does not occur.

If there is an entry address in the address area of accumulator 3, then in this case the output of the result of the analysis of block 1 will be set to logical "O, which is fed to the input of accumulator 2 features.

Somewhat earlier, the address from the Ij block arrives at the address inputs of the accumulator 2j. Next, the write flag is read through the switch 18 to the output and allows writing to the addressed drive 3, as described above. Since the output of the trigger 32 is low logic level, the data located at the input 8, goes through the switch 11 to the information inputs of the drives 3 and is recorded in the information storage 3 /, since the output of the trigger 31 is constantly in the low logic level and allows the passage of a pulse from the output of the delay element 30 through the OR element 21 to the recording inputs of the accumulators 3.

On this, the write cycle ends.

Reading mode

In this mode, the RAM 34 and the input 4 of the POPs 33 receive the t-bit read address from the processor 35. Then

a negative read pulse from the processor 35, according to which the RAM 34 begins a reading cycle. At the same time, this impulse arrives at the input of the trigger 32, sets at its forward output a logical “1”, which, arriving at the control input of the switch 11, connects the device input 7 to the information inputs of the accumulators 3. This same impulse, entering through the element 29 and the element 30, causes the appearance at the write inputs of the drives 3 a negative write pulse, and entering through the delay element 24, causes the appearance at the counting input of the counter 7 and the enable input of the decoder 5 a negative pulse. Depending on the value of the current read address, the contents of the registers 13 of the starting address and the contents of drives 2, three different read operations are possible.

Go to subroutine. In this case, the current address, arriving at the inputs of blocks 1, causes the appearance at their outputs of the result of the analysis of logical “1. This indicates that inequality (1) is not fulfilled for any of the blocks 1, and therefore, the current reading address does not fall into the address area of np {one of the drives 3. Proceeding from the device operation algorithm, you must install in one of the drives 3 the new starting address, clear the corresponding drive 2 and then (at subsequent readings) fill it again.

Filling pops.

In this case, the accumulator 3 is sequentially filled with information read from RAM 33. The current address falls into the address region of accumulator 3j, therefore the PHA does not change and the low-level indication allows writing the sign (logical zero) to accumulator 2. The signal "Reset reading cycle in RAM 34 does not arrive, therefore, it continues the reading cycle, trigger 31 is not set to a high logic level, which permits the write pulse through the OR 21 element to the recordings of the drive 3 (after the read data from RAM 34 in hardware on the information inputs of drives 3). This read cycle ends.

Reading from pops.

In this case, reading from RAM 34 is replaced by reading from accumulator 3. At the same time, the current address falls into the address area 3j, therefore the PHA does not change and the sign of entering from the output of block 1 / enters the input of accumulator 2j and permits reading of the write feature, as well as to the input drive 3 |, preparing it for reading.

Claims (3)

1. An ultra-fast memory containing a main data storage 5, a main recording feature accumulator and a control unit, the first and second outputs of which are connected respectively to the recording input of the main data storage and the synchronization input of the main Q recording characteristic accumulator, the output of which is connected to the recording presence input control unit, characterized in that, in order to increase the speed of the device, address analysis blocks, additional data collectors, 15 additional recording feature accumulators and a switch, the information inputs of which are the information inputs of the device, and the output connected to the information inputs of the data collectors, The Q information inputs of the analysis units are combined and are the address inputs of the device, the information outputs of the address analysis blocks are connected to the address inputs of the corresponding record attributes and data accumulators,  the outputs of which are combined and are informational outputs of the device, pe3yvabTaTa analysis outputs of the address analysis blocks are connected respectively to the drive access permission inputs Q records and the first inputs for accessing the data collectors, the third output of the control unit is connected to the control input of the switch, the output group of the control unit is connected to the write inputs of the address analysis blocks and the setting inputs of the recording feature accumulators whose outputs are combined and connected to the second permission inputs addresses of data accumulators, the outputs of the result of the analysis of address analysis blocks are connected to a group of inputs for the presence of a record of the control unit data cells and synchronization inputs of additional drives for recordings are connected to the first and second outputs respectively 5 of the control unit, the fourth output of the control unit is the output of the device read cycle reset, the read and write enable entries of the control unit are the read and write entries of the device, respectively. 0 2. The device according to claim 1, wherein each address analysis block contains a starting address register, a subtractor and an NAND element, the first input of the subtractor and the information input of the starting address register are combined and are the information input of the block, the synchronous input register the start address is the block entry input, the sub bits of the subtractor are informational five the output of the block, the outputs of the higher bits of the subtractor are combined and connected to one of the inputs of the NAND element, the other input of which is connected to the transfer output of the subtractor, and the output of the NAND element is the output of the analysis result of the block. 3. The device according to PP. 1 and 2, characterized in that each recording feature store contains a descrambler, triggers, a switch, an AND-NOT element and an OR-NOT element, the information inputs of the decoder and one of the information inputs of the switch are combined respectively and are address inputs of the storage drive, other information switch inputs connected to the outputs of the flip-flops, the inputs of the asynchronous installation in "1 flip-flops connected to the outputs of the decoder, the inputs of the asynchronous installation in the" About flip-flops are combined and are the installation input of the AND-NOT element and the output of the accumulator the switch is connected and is the input of the drive enable resolution, the second input of the element OR is NOT the synchronization input of the drive, the output of the element OR is NOT connected to the second input of the element IS – NOT, the output of which is connected to the control input Ode to the decoder. Address / 77 one BUT P.1 , -g 1 -I / 77 / 1 Record PH / 1 NK / ffpec FS / a.2 / Idre with sixteen f f / // f 17 77 77 / 18 / 7jyu3Haf. And cfJue.3 /  a / raffcf i / C / 77poS { 20 nineteen 7 Paapeu / ff ije /