SU1621033A1 - Device for with check for multiplying numbers - Google Patents

Abstract

The invention relates to computing and can be used in the construction of arithmetic nodes. The purpose of the invention is to increase the reliability of the device. The device contains a group of registers, the matrix of elements AND, the matrix of adders, the adder, the output register, the comparison node, triggers, elements I. from the input of the device. The result of the calculation is written to the output register. Then there is a cyclic shift of information in the registries of the group, as a result of which the factors are swapped. The new result of the calculation is compared by the comparison node with the contents of the output register. If the two results are not equal, the trigger is set to a single state, which indicates an error in the operation of the device. 2 Il. /) with

Description

The invention relates to computing and can be used in the construction of arithmetic nodes.

The aim of the invention is to increase the reliability of the device.

Figure 1 shows the functional diagram of the device for six-bit factors; figure 2 - the timing diagram of his work.

The device (Fig. 1) contains a group of registers 1, a matrix of 2 elements AND, a matrix of 3 adders, an adder 4, an output register 5, a comparison node 6, triggers 7-9, elements 10 and 11j of the inputs 12, 13 of a multiplicand device multiplier, respectively , clock 14

and installation 15 inputs of the device, information output 16 of the device, the control output 17 of the device.

The device works as follows.

The inputs 12 and 13 of the device receive multiplier and multiplier, respectively. On the clock input 14 of the device, the sync pulses are supplied. The impulse arriving at the installation input 15 of the device at the beginning of operation sets the first 7 and second 8 triggers to zero.

At time T1 on the falling edge of the clock pulse occurs when O

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OE

with

The multiplier and multiplier bits in registers of group 1.

The receive mode is provided with a zero value of the signal P at the inputs of setting the operation mode of the registers of group 1, coming from the direct output of the first trigger 7. From the outputs of the registers of group 1, the multiplicand and multiplier bits are received respectively at the first and second inputs of the AND matrix 2 elements, which define conjunctions of multiplicand and multiplier. Conjunctions from the outputs of elements II of each j-th row (j + 1) -ro of the column of matrix 2 are fed to the first information input of the adder of the j-th row of the j-ro column of matrix 3 (1: j ig (n-1), where n is the multiplicity of the multiplier and multiplier).

Conjunctions from the outputs of the elements And (j + 1) -fi row of the first column of matrix 2 is fed to the second inputs of the adders of the j-th row of the first column of matrix 3.

The second inputs of the adders of the k-th row of each column of matrix 3, starting from the second, receive signals from the output of the sum of the adder (k + 1) -th row of the previous column of matrix 3 (1 6).

The second inputs of the adders (p-1) of the row of each column of the matrix 3, starting with the second, receive the conjunctions from the outputs of the elements And the nth row of the previous column of the matrix 2.

The third inputs of the adders of the first column of the matrix 3 are connected to the zero potential bus of the device. The third inputs of the adders of all columns of matrix 3 are connected to the transfer outputs of the corresponding adders of the previous column of matrix 3.

Adder 4 summarizes the signals from the outputs of the sum and carry of the adders of the (n-1) th column of matrix 3 and the outputs of the element And the n-th row of the n-th column of matrix 2, and in the k-th section of adder A is added the transfer output the adder of the kth row and the output of the sum of the adder (k + 1) -u row (n - - 1) -th column of the matrix 3.

The high bits (from the seventh to the twelfth) are removed from the output of the adder 4, and the low bits of the product (from the first to the sixth) are removed from the output of the element And the first row of the first column of the mat

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Fig. 2 and the sum of the adders of the first row of the matrix 3.

All 12 bits of the output go to the information input of the output register 5 and are written into it by the signal from the output of the element AND 10 at the moment 12 on the falling edge of the clock pulse.

U On this clock front

a cyclic shift of the contents of the registers of group 1 occurs. The shift mode is determined by a single signal at the direct output of the trigger 7.

15 Thus, the multiplier and the multiplier are interchanged. The calculation is repeated, but the result of the work is not recorded in register 5, but is transferred to the first information

The 20 input of the comparison node 6, where it compares with the previous result recorded in register 5. In the case of non-comparison, trigger 9 is set to one and a single signal is generated at the control output 25 and 16 of the device, indicating that the device is faulty.

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Claims (1)

Invention Formula A device for multiplying the numbers with the control, containing the matrix of elements And dimensions fpr (n is the size of the factors), the matrix of adders of dimension (n-1) x (n-1) and adder, with the output of each element And j-th row (j + 1) -ro of the matrix column is connected to the first information input of the adder of the j-th row of the j-ro column of the matrix (1 -Sj p-1), the second information input of the adder (p-1) -th row of the j-ro column is connected to the output of the element And the n-th row of the j-ro column of the matrix, the output of the sum of the adder of the p-th row of the k-ro column of the matrix is connected to the second information input with the adder's (p-1) -th row (kH) -ro column of the matrix (2 $ p (p-1); 1 $ k n-2), the transfer output of each adder of the j-th row of the k-ro column of the matrix is connected to the third the information input of the adder of the jth row (k + 1) -ro of the matrix column, the second informa tion input of the adder j-rt of the row of the first column of the matrix is connected to the output of the element And (jH) -ft row of the first column of the matrix, the third information input of the adder of the first matrix rows connected to bus n5 the left potential of the device, the transfer output of the adder of the j-th row (n - - 1) of the matrix column is connected to the j-th input of the first term of the adder, the k-th discharge of the second adder's input is connected to the output of the sum of the adder (k + 1) -ft row (n-1) -th column of the matrix, the output of element II of the n-th column of the n-th column of the matrix is connected to the last bit of the input of the second term of the adder, characterized in that, in order to increase the reliability of the device, it contains a group of registers, an output register, a comparison node, two AND elements and a tr and a trigger, with the first and second bits of the information inputs of the group registers connected to the corresponding bits of the input multiplicand and input multipliers of the device, respectively, the output of the first bit of the 1st register of the group (1 jЈ in) is connected to the first inputs of all elements AND 1 matrix column, the output of the second bit of the 1st register of the group is connected to the second inputs of all elements And the i-th row of the matrix, the clock inputs of the group registers, the counting input of the first trigger and the first inputs of the first and second elements AND are connected to the clock input y device, the output of the second bit of the 1st register of the group is connected to the serial input ten 101136 Home of the i-ro register of the group, the installation inputs of the first and second triggers are connected to the installation input of the device, the direct output of the first trigger is connected to the second input of the first element I, the clock input of the second trigger and the inputs of the setting of the operation of the registers of the group, the weight output the first trigger is connected to the second input of the second element AND, the output of the first element AND is connected to the clock input of the output register, the output of the AND element of the first row of the first column of the matrix, the outputs of the sum of adders of the first row of the matrix and the sum outputs and transfer outputs of the adder are connected to the corresponding information inputs of the output-. The 20th register and the corresponding bits of the first information input of the comparison node, the output of which is unbalanced is connected to the information input of the third trigger, 25 the output of which is the control output of the device, the output of the second element And the direct output of the second trigger are connected to the clock and installation inputs of the third trigger, respectively, the output of the output register is connected to the second information input of the comparison node and is the information output of the device, the information input of the second trigger connected to the bus of the unit 3 $ th potential of the device. thirty Re entry i Przykodo pg g fae. 2