SU1644136A1 - Product sum calculator - Google Patents

Abstract

The invention is related to computing and is intended111 for use in systems for collecting and processing acoustic and speech signals. The purpose of the invention is to reduce the amount of equipment. To do this, a block 6, a memory, and an adder 3 are inserted into the device containing block 1 of the shift registers, block 2 of memory, adder 4 and register-accumulator 5. The proposed technical solution becomes effective when the hardware cost of implementing the additional adder 3 and memory block 6 is less than half the cost of implementing the main storage device for a table of 2 words, where N is the number of coefficients. The effect is achieved at N 6, and starting from N 8 the reduction in hardware costs is determined by the dependence 2fN No, where H0 6. 2 Il.

Description

ten

4

3

C # C

77

1

 ; /

The invention relates to computing and is intended for use in systems for collecting and processing acoustic and speech signals.

The purpose of the invention is to reduce the amount of equipment of the device (by reducing the storage capacity of the tables of partial works).

Figure 1 shows the structural diagram of the device; FIG. 2 is a time chart of his work.

The device contains a block of 1 shift registers, a block of 2 memory (partial products), adders 3, 4, register-drive 5, block 6 of memory, control buses (inputs) 7-10 write, shift, write to register-drive, reset, input bus U multiplied, output bus 12 result.

The device performs an operation K

2ralxi gDe x | variables; but

coefficients; ,

The operation of the device for N 10 and the x-size of 16 is as follows.

The operation is carried out in a tabular and algorithmic manner.

Partial products are written into the first memory block (512x16p). In each cell with the address tf {, ..., 0 (p, where, 0.1, the number 4 tf, a, + ... + is written).

The second block of memory (2x16p) contains the numbers 0 and a 10.

In the first clock cycle, a pulse is applied to inputs 7 and 10. The numbers x1, xg ... x 1Q are written to the registers of block 1 and the contents of the register-drive are reset. In the next series of sixteen clocks, pulses are fed to inputs 8.9 and carried out

calculation

THOSE

D; x;

After the first clock of sixteen clock series at the output of the block

2 sets the number in the cell with the address Ј x 1 ... , x, where Xj - the younger (16th) bits of the numbers x ... x. At the output of block 6, the number 0 or a nd is suspended, depending on the value of x. the output of the adder 3 is formed by the number th

G,

")

ajx .. upon the arrival of the second

the pulse to the input 3 is shifted by one bit to the right of the information in the registers of block 1. At the output of the sum of the torus, the number Г а-х is formed. ,

 & one

h - 1

(J)

where x is the 15th digit of x. On

The output of drive register 5 is the sum of f, +. 0 In the last (17th) clock cycle, it is computed and written to the register register.

bullet 5 number

one

ah ..

Ula Invention Form

A device for calculating work sums containing a block of shift registers, a first memory block, a first adder, a drive register, the inputs of the shift register block being connected to the device inputs, and all but one of the outputs are connected to the corresponding bits of the address input of the first memory block , the output of the first adder is connected to the input of the register-accumulator, the output of the register-accumulator is connected to the output of the device and is shifted by one bit to the right with the first input of the first adder, characterized in that, in order to reduce the equipment volume, the second adder and the second memory block are entered into it, the address input of which is connected to the last output of the shift register block, and the output - to the first input of the second adder, the second input of which is connected to the output of the first memory block, and the output to the second the entrance of the first

adder.

fix. | 7.10

fl

fix. 8.9

STI

H

Feed 2

Claims (1)

Claim A device for calculating the sums of works containing a block of shift registers, a first memory block, a first adder, a storage register, the inputs of the block of shift registers being connected to the inputs of the device, and all outputs except one ^ connected to the corresponding bits of the address input of the first memory block, output the first adder is connected to the input of the register-drive, the output of the register-drive is connected to the output of the device and with a shift of one bit to the right - with the first input of the first adder, characterized in that, in order to reduce equipment, the second adder and the second memory block are inserted into it, the address input of which is connected to the last output of the block of shift registers, and the output is connected to the first input of the second adder, the second input of which is connected to the output of the first memory block, and the output is from the second input of the first adder.