SU698017A1

SU698017A1 - Digital integrator

Info

Publication number: SU698017A1
Application number: SU782589148A
Authority: SU
Inventors: Геннадий Яковлевич Кузьмин; Евгений Павлович Балашов; Михаил Степанович Куприянов
Original assignee: Ленинградский Ордена Ленина Электротехнический Институт Им. В.И.Ульянова (Ленина); Предприятие П/Я А-3890
Priority date: 1978-03-13
Filing date: 1978-03-13
Publication date: 1979-11-15

Description

(54) ЦИФРОВОЙ ИНТЕГРАТОР(54) DIGITAL INTEGRATOR

1one

Изобретение относитс к цифровой вычислительной технике и может найти применение в устройствах программного управлени .The invention relates to digital computing and can be used in software control devices.

Известно устройство, содержащее блок подынтегральной функции, выходной блок, блок итераций, програмный блок, состо щий нз регистра сдвига, сумматора, элемента задержки 1.A device is known that contains a block of the integrand function, an output block, an iteration block, a program block consisting of a shift register, an adder, and a delay element 1.

Недостаток устройства - больпше затраты на оборудование.The disadvantage of the device is more equipment costs.

Наиболее близок предлагаемому по технической сущности цифровой интегратор, содежащий блок подьштегральной функции, блок итераций, сдвиговый регистр, сумматор, элемент задержки, элементы И 21.Closest to the proposed by the technical nature of the digital integrator, containing the unit podshtegralnoy functions, the iteration unit, shift register, adder, delay element, the elements And 21.

Недостатком интегратора вл етс низкое быстродействие.The disadvantage of the integrator is low speed.

Цель изобретени - повьпиение быстродейгтви .The purpose of the invention is the behavior of speed.

Указанна цель достигаетс тем, что в цифровой интегратор, содержащий блок пам ти , первый разр дный выход которого соединен с первым пр мым входом трехвходового элемента И, второй пр мой вход коiTOporo соединен с первым выходом сумматора и вторым разр дным выходом блока пам ти, инверсный вход трехвходового элемента И подключен к первому входу сумматора , второй, выход которого через первый элемент задержки соединен с пр мым входом двухвходового элемента И, инверсный вход которого соединен с первым выходом генератора и вторым входом сумматора, выход двухвходового элемента И подключен к третьему входу сумматора, введены счетчик , второй элемент задержки и элемент НЕ, причем вход элемента НЕ соединен .с первым выходом сумматора, а выход через второй элемент задержки - с установочным входом счетчика, управл ющий вход которого соединен со вторым выходом генератора, выход счетчика подключен к адресному входу блока пам ти, первый и второй управл ющие входы которого соединены соответственно с третьим и четвертым выходами генератора.This goal is achieved by the fact that a digital integrator containing a memory block, the first bit output of which is connected to the first direct input of the three-input element I, the second right input of the koiTOporo is connected to the first output of the adder and the second bit output of the memory block, inverse the input of the three-input element And is connected to the first input of the adder, the second, the output of which through the first delay element is connected to the direct input of the two-input element And, the inverse input of which is connected to the first output of the generator and the second input of the sum the output, the output of the two-input element AND is connected to the third input of the adder, the counter is entered, the second delay element and the element are NOT, the input of the element is NOT connected to the first output of the adder, and the output through the second delay element is connected to the installation input of the counter with the second output of the generator, the output of the counter is connected to the address input of the memory unit, the first and second control inputs of which are connected respectively to the third and fourth outputs of the generator.

Claims

The drawing shows a block diagram of the proposed integrator. The digital integrator contains a memory block 1, a three-input element And 2, an adder 3, an output of mirerparopa 4, a delay element 5, a two-input element And 6, a generator 7, the element 8, a second delay element 9, a counter 10. Block 1 is a two-bit A single memory block, in one section of which a value of the integrand function is stored, and in the other a sum of unit increments is performed. The integrator works as follows. Before starting work in the first information section (IC1), which is formed by the aggregate of the first bits of all cells of block 1, the value of the integrand function is written, the old bit of which is located in the first cell of block 1, and the second information section (IC 2) and counter 10 are embraced. The function of the digital integrator is to provide at the output 4 series of signals, the number of which is determined by the value of the integrand recorded in the IC1. In the first cycle, from the first output of the generator 7 to the second input of the adder 3 it enters 1, a signal is sent from the third output of the generator 7 to the first control input of the unit 1, providing the Read mode at the address set on the account 10. As the counter has zeroed before starting then, the first input of the adder 3 and the first direct input of the element And 2 receive the zero value of the first bit of IC2 and the value of the staging bit of IC1, respectively. At the output of the adder 3, an amount of 1 is formed. Thus, O is fed to the inverse input of element 2, and 1 is fed to the second input, which ensures the output of the high bit of the integrand function to output 4. In the second cycle of the fourth output the generator 7 sends a signal to the second control input of the unit 1, which provides the Record mode, in which the obtained value of the sum is recorded in the first digit; IS2. In the third cycle, O, read from block 1 through the element HE 8 and the delay element 9, is fed to the installation input of the counter 10, which leads to the nulling of its contents. Further, the operation cycle of the device is repeated. If 1 is read from the memory block in the first clock cycle, the value of the subsampling function is not output to output 4, in the second clock the transfer value through delay element 5 and the AND 6 element is fed to the third input of the adder 3, since the first output of the generator 7 in the third cycle to the inverse of the input of the element And 6 comes O. The value of the integrand function is fully on the output bus 4 in the case when the contents of the IC2 overflow. In comparison with the known, the speed of the proposed integrator is increased by 3-4 times. DETAILED DESCRIPTION OF THE INVENTION A digital integrator containing a memory block, the first bit output of which is connected to the first direct input of the three-input element I, the second direct input of which is connected to the first output of the adder and the second bit output of the memory block, is connected to the inverse of the three-input element to the first input of the adder, the second output of which through the first delay element is connected to the direct input of the two-input element I, the inverse input of which is connected to the first output of the generator and the second input of the adder, output d V-input element I connected to the third input of the adder, characterized in that, in order to increase speed, a counter, a second delay element and a NO element are entered into it, and the input of the element is NOT connected to the first output of the adder, and the output through the second delay element - with the installation the counter input, the control input of which is connected to the second output reHepaToj a, the counter output is connected to the address input of the memory unit, the first and second control inputs of which are connected respectively to the third and fourth outputs of the generator . Sources of information taken into account during the examination 1. A. Shileyko. Digital models. ML, Energy, with. 27.

2. USSR author's certificate for application No. 2327397 / 18-24, cl. G 06 T 1/02, 1976.