SU1429174A1 - Digital information delay device with self-check - Google Patents

Abstract

The invention relates to the field of computing and can be used in the delay lines of digital information. The purpose of the invention is to increase the reliability of the device by correcting multiple errors of the delayed information words that are not less than m time ticks apart (t is the information word depth). The device contains registers 1-3 and 7-10 of shift, units 4,5,11,13 convolutions by module, block 6 of memory, blocks 12 and 14 are comparable. neither, register 15 shift, elements AND 16-19 and the elements UNEQUALITY 20-23. 1 pc., 1 tab.

Description

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The invention relates to storage devices and can be used in delay lines of digital information.

The purpose of the invention is to increase the reliability of the device.

The drawing shows a block diagram of a device for delaying digital information (for, where m is the number of information inputs of the device)

The device contains the first group of shift registers 1–3 (three-, two- and one-bit respectively), the first .4 and third 5 convolution units modulo, memory block 6, the second group of shift registers 7–10 (respectively one, two - and three bits), the second module of convolution 11 by modulo, the first comparison block 12, the fourth module 13 of convolution by modulus, the second comparison block 14, three-digit shift register 15, elements AND 16-19, and UNIMKNESS 20-23. The device has a control input 24, a synchronization input 25, information inputs 26, input 27 Correction blocking, information outputs 28, input 29 Error presence and input 30 Error location.

The device works as follows,

At the initial moment, all device registers are zeroed out and the delay code arrives at the input x: device input 24 (zero circuits are not shown). This sets the recalculation factor for the address circuits of block 6, i.e. the delay value K. Next, from the device inputs 26, t-bit informational words begin to arrive, followed by a square-wave type sync pulse at input 25. At each leading edge of the sync pulse, the address in block 6 increases by one, and during the first half of the period the information from cells of the memory recorded K cycles back, and during the second half of the period of clock pulses, information is written to the same cell, which will be read after K cycles

Before entering the inputs of block 6, the information words of the input sequence are delayed bitwise in such a way that only one bit of the given word is recorded in each clock cycle.

For this, the first bits of the input sequence are delayed by register 1 by three cycles, the second bits are delayed by register 2 by two cycles, and so on, the fourth - the last bit is fed to the input of block 6 without delay. The first check bits are computed as a sum modulo convolution unit 4. The second check bits are also inserted as a sum modulo unit 5, only for the bit of the input sequence shifted one cycle. The control bits are recorded in block 6 together with the corresponding information bits, from where they will be read out in K ticks.

The location of information in memory

0 of control delay block 6 is illustrated by a table for the four input words: a, b, c and d.

The table shows that the fourth bit of the word a (a4) and the corresponding check bits Ka and K1 are recorded in block 6, the fourth digit of the word b (b4) and the third bit of the word a (AZ ) with the corresponding test rows of Kb and K2. Moreover, the bits Ka, Kb, Kc, and Kd represent a convolution modulo the output words a, b, c, and d, respectively, and bits K1, K2, and so on. - convolution on the same module of information that comes directly to the information inputs of block 6 in the first, second, etc. ticks.

When reading, a similar calculation of the first and second check bits takes place after alignment of the shift entered and recorded in the write, respectively. The mismatch of the check bits read from block 6 and calculated on the basis of the read bits,

5 indicates a distortion of information during the delay.

We conclude that in the course of the delay, information was distorted in the discharge of L2. Then when reading occurs

0 mismatch test bits Kb

and K4, which indicates that the distortion occurred in the word b in the fourth cycle, since in this cycle. Only one bit of word was read.

5 b (b2), then it can easily be fixed, inverted.

Registers 7-9 align the shift entered in the recording.

five

0

Register 10 aligns the read first check bits with the corresponding information words. Blocks 11 and 13 compute the convolution modulo the read out of block 6 and the aligned information, determine the second and first check bits, respectively. The discrepancies between the first and second check bits appear at the outputs of the comparison blocks 14 and 12 in the form of signals of a logical unit. The signals on the coincidence of the second control bits from the output of block 12 are fed to the input of register 15, where they are delayed by three cycles. In this case, as soon as the output of block 14 shows a signal that the first check bits do not match (the logical unit at the output of block 14), the corresponding element AND 16-19 transfers its output to the state of a logical unit; the translation connected to its output is UNABILITY to inversion mode. The bad bit received from registers 7-9 or the first information output of block 6 will be inverted. Giving input to the device 27 signal blocking, you can disable the correction, forcibly set at the output of block 12, a signal of logical zero. After this logical zero fills all the bits of register 15, the outputs of the AND elements 16-19 are held

in the state of logical zero, prohibit the inversion of information. In this case, the information input of the device receives uncorrected information, accompanied by signals

error on the input 29 of the device.

Claims (1)

Invention Formula A device for delaying digital information with self-control, containing a memory block, first and second module convolution modulo, first and second comparison blocks, with the inputs of the first module convolution block being information inputs of the device, the output of the first module convolution is connected to the input of the first check bit of the memory block, the synchronization input and the control input of the memory block are respectively the synchronization input and the control input of the device; the first information input of the first comparison unit is connected n to the output of the second control 0 5 0 5 o with 0 5 0 e the memory block bit, the second information input of the comparison block is connected to the output of the second convolution block modulo, the inputs of which are connected to the information bits of the memory block, the input of the last information bit of the memory block is connected to the corresponding information input of the device, that, in order to increase the reliability of the device, the first and second groups of shift registers, the third and fourth modulation convolution blocks, the shift register, the elements of And and the elements of unequalities, and info The input inputs of the shift registers of the first group are connected to the information inputs of the device, except the last, the outputs of the shift registers of the first group are connected to the information slots of the memory block, except the last; the inputs of the third convolution unit modulo are connected to the outputs of the shift registers of the first group, the outputs of the information bits of the memory block, except for the first information bit, and the output of the first control the memory bit of the memory block is connected to the information inputs of the group shift registers, the output of the first information bit of the memory block, and the outputs of the second group shift registers except the last register shift, connected to the first inputs of the UNEQUALITY elements, the second inputs of which are connected to the outputs of the AND elements, the outputs of the UNEQUALITY elements are information outputs of the device; modulo, the output of the second comparison unit is connected by the first inputs of the AND elements, the second input of one of the AND elements and the information input of the shift register are connected to the output of the first block By comparison, the second inputs of the other AND gates connected to outputs of the bit shift register, synchronization shift register inputs are connected to the synchronization input device, outputs the first and second comparison is output blocks are respectively Availability dosing errors and vy5 June 2 Stroke The location of the device-Comparison error is the input of the Block, which controls the input of the first block of the device correction. Dd ETEinnilLin Ltd K7 c1 Oh oh Kb Tact number a1 b2 sz Kd K4 ABOUT a2 B3 c4 O O AZ 3 Ks Kb KZ K2 About About About a4 Ka K1