SU1341643A1

SU1341643A1 - Device for checkining information being transmitted

Info

Publication number: SU1341643A1
Application number: SU843813585A
Authority: SU
Inventors: Рудольф Николаевич Мусатов; Сергей Георгиевич Николаев; Павел Николаевич Смирнов
Original assignee: Предприятие П/Я А-3325
Priority date: 1984-11-16
Filing date: 1984-11-16
Publication date: 1987-09-30

Abstract

Изобретение относитс к вычислительной технике и может быть использовано в устройствах обмена информацией между вычислительным устройством и внешними блоками, а также в устройствах обмена между блоками вычислительного устройства . Цель изобретени повьшение надежности передачи информации путем коррекции ошибок в канале св зи. Устройство содержит регистры 1 и 2, два блока 3 и 4 формировани контрольных разр дов, блок 5 сравнени , элементы задержки 6 и 7, триггер 8, две группы 9 и 10 сумматоров по модулю два, вход 11 синхронизации, выход 12 синхронизации , выход 13 ошибки, выходы 14 информационные . Устройство позвол ет корректировать ошибки, возникающие вследствие обрыва или замыкани на ноль отдельных проводов линии св зи. Повышение надежности передачи информации достигаетс за счет введени двух групп сумматоров по модулю два, двух элементов задержки и триггера. 1 ил. i (ЛThe invention relates to computing and can be used in devices for exchanging information between a computing device and external units, as well as in devices for exchanging between units of a computing device. The purpose of the invention is to increase the reliability of information transmission by correcting errors in a communication channel. The device contains registers 1 and 2, two blocks 3 and 4 for the formation of test bits, a block 5 of comparison, delay elements 6 and 7, trigger 8, two groups 9 and 10 modulo-two adders, synchronization input 11, synchronization output 12, output 13 errors, exits 14 informational. The device allows to correct errors resulting from the breakage or closure of the individual wires of the communication line to zero. An increase in the reliability of information transmission is achieved by introducing two groups of modulo-two adders, two delay elements and a trigger. 1 il. i (L

Description

Изобретение относитс к вычислительной технике и может быть использовано в устройствах обмена информацией между вычислительным устройством и внешними блоками, а также в устройствах обмена между блоками вычислительного устройства.The invention relates to computing and can be used in devices for exchanging information between a computing device and external units, as well as in devices for exchanging between units of a computing device.

Цель изобретени - повьппение надежности передачи информации путем коррекции одиночных ошибок в канале св зи.The purpose of the invention is to increase the reliability of information transmission by correcting single errors in a communication channel.

Устройство дл контрол принимаемой информации содержит регистры 1 и 2, два блока 3 и 4, формировани контрольных разр дов, блок 5 сравнени , элементы 6 и 7 задержки, триггер 8j -две группы сумматоров 9 и 10 по модулю два, вход 11 синхронизацииThe device for monitoring received information contains registers 1 and 2, two blocks 3 and 4, generation of check bits, comparison block 5, delay elements 6 and 7, trigger 8j - two groups of adders 9 and 10 modulo two, synchronization input 11

выход 12 синхронизации, выход 13 ошиб-2о ное тому, которое сформировано на выки , выходы 14 информационные.synchronization output 12, output 13 is erroneous to the one formed on the skills, outputs 14 are informational.

Устройство работает следующим образом .The device works as follows.

Регистр 1 формирует на своих выходах многоразр дное двоичное слово. Сигнал, свидетельствующий о том,что .сформированное слово подлежит передаче , подаетс на вход 11 устройства и представл ет собой импульс, длительность которого соответствует интервалу гарантированного посто нства передаваемого кода. Допустим, что в начальном состо нии триггер 8 находитс в нулевом состо нии. При этом информаци в сумматорах 9 и 10 не инвертируетс . Переданное слово подаетс на входы блока 3 формировани контрольных разр дов, с выхода формируютс контрольные разр ды. Прин тое слово поступает на входы блока 4 формировани контрольных разр дов , с выхода которого также формируютс контрольные разр ды.Register 1 forms a multi-bit binary word at its outputs. The signal, indicating that the formed word is to be transmitted, is fed to the device input 11 and is a pulse whose duration corresponds to the interval of the guaranteed constant of the transmitted code. Assume that in the initial state the trigger 8 is in the zero state. However, the information in adders 9 and 10 is not inverted. The transmitted word is fed to the inputs of the block 3 forming the check bits, with the output forming the check bits. The received word enters the inputs of the block 4 for forming check bits, from the output of which the check bits are also formed.

Если контрольные разр ды переданного и прин того кодов равны между собой, на выходе блока 5 сравнени будет низкий потенциал, что свидетельствует о правильности цередачи информации . В этом случае через врем , определ емое элементом 6 задержки, сигнал, поступающий на тактовый вход триггера 8, не измен ет его состо ни и через врем задержки на элементе 7 задержки сигнал приема поступает на управл ющий вход записи регистра 2, разреша прием информации.If the check bits of the transmitted and received codes are equal to each other, the potential of the comparison unit 5 will be low, which indicates the correctness of the information transfer. In this case, after the time determined by the delay element 6, the signal arriving at the clock input of the trigger 8 does not change its state, and after the delay time at the delay element 7 the reception signal arrives at the control input of the register 2, allowing reception of information.

Прием информации в регистр 2 сопровождаетс по влением сигнала на выходе 12 устройства, а низкий потен25Reception of information to register 2 is accompanied by the appearance of a signal at the output 12 of the device, and a low potential

ходе регистра 1. 1 the course of the register 1. 1

В этом случае, если ошибку удалось исправить, на выходе блока 5 сравнени образуетс низкий потенциал, поступающий на выход 13 и свидетельствующий о том, что сигнал, формируемый на выходе 12, сопровождает правильно переданную информацию.In this case, if the error was corrected, a low potential is formed at the output of the comparison unit 5, which arrives at output 13 and indicates that the signal generated at output 12 accompanies the correctly transmitted information.

Если после переключени триггераIf after switching the trigger

30 8 высокий потенциал с выхода блока 5 сравнений не измен етс на противоположный , значит ошибку устранить не удалось, сигнал с выхода 12, поступающий одновременно с высоким по35 тенциа;лом с выхода 13, свидетельствует о том, что в регистре 2 записано слово с ошибками.30 8 high potential from the output of block 5 comparisons does not change to the opposite, it means that the error could not be eliminated, the signal from output 12, simultaneously arriving with a high potential; scrap from output 13, indicates that the word 2 in the register 2 contains errors .

Claims

Invention Formula

40

A device for controlling information in transmission, containing the first and second registers, the first and second blocks of formation of control bits 45 rows, the comparison block, with the outputs of the first register connected to the inputs of the first block of forming test bits, a group of outputs of which are connected to the first group

The 50 inputs of the comparison unit, the second group of inputs of which is connected to the group of outputs in the second block for generating check bits, the output of the comparison block is the error output of the device, characterized in that, in order to increase the reliability of information transfer, two groups are entered modulo two, two delay elements

five

The output port 13 indicates that the information has been received correctly.

If the check bits from the outputs of block 3 and block 4 are not equal to each other, a high potential appears at the output of comparator block 5 allowing, after the delay time determined by delay element 6, switching of the trigger 8 to the opposite state. In this case, a high potential is formed at the second inputs of adders 9 and 10 modulo two. In this case, a word is transmitted that is invertible relative to the word formed by register 1, and a double inverted word is fed to the inputs of register 2, i.e. word, rav5

the course of the register 1. 1

In this case, if the error was corrected, a low potential is formed at the output of the comparison unit 5, which arrives at output 13 and indicates that the signal generated at output 12 accompanies the correctly transmitted information.

If after switching the trigger

0 8 high potential from the output of block 5 comparisons does not change to the opposite, it means that the error could not be eliminated, the signal from output 12, arriving simultaneously with a high potential; scrap from output 13 indicates that the word 2 in the register 2 contains an error word .

Invention Formula

0

A device for controlling information in transmission, containing the first and second registers, the first and second blocks of formation of check bits, a comparison block, the outputs of the first register connected to the inputs of the first block of forming check bits, the output group of which is connected to the first, group

0 inputs of the comparison unit, the second group of inputs of which is connected to the group of outputs in the second block forming the check bits, the output of the comparison block is the error output of the device, characterized in that, in order to increase the reliability of information transfer, two groups are entered adders modulo two, two delayed elements - 1341643

and a trigger, the outputs of the first inputs of the second register generation unit are connected to the first inputs of control bits and information corresponding modulators of the second register, the outputs of the first two groups, whose outputs are informational through communication lines are connected to the first the device's outputs, the input by the synchronous inputs of the corresponding summation of which is connected to the input of moduli two second groups, the second-first delay element, the output of which inputs and the second inputs of sum-toro о is connected to the synchronizer input modulo two of the first trigger IQ group and with the input of the second one are connected and connected to the output, the delay ment, whose output is a trigger, inputs I and K are combined with the input of the second register record and connected to the output of the blocker and is the comparison synchronization output, the outputs of the adders on my device, the two two second groups are connected to