SU1307461A1 - Interface for linking two computers - Google Patents

Abstract

The invention relates to computing and can be used in computing complexes built on universal and specialized computing machines. The purpose of the invention is to improve the performance of the device. Achieving the goal is ensured by that. (L 00 o | (

Description

that the device contains a shift register 1, two groups of elements AND 2 and 3, a pulse counter 4, register 5, a decoder 6, a control trigger 15, elements AND 7-P, ШШ 12-14. The device allows you to transfer two words of information in one session. The word of information from the universal machine enters register 5 and then through

one

The invention Refers to computing and can be used in computing systems built on a universal and special-purpose computerized computers (COMPUTER).

The purpose of the invention is to increase the productivity of the device.

The drawing shows a block diagram of the device.

The device contains a shift register 1, elements AND 2 of the first group, elements AND 3 of the second group, a pulse counter 4, information register 5, a decoder 6, first 7, second 8, third 9, fourth 10 and fifth And elements AND, first 12, the second 13 and third 14 elements OR, the control trigger 15, the first 16 and second 17 write inputs of the device, the first 18 and second 19 read inputs of the device, the output 20 of the interrupt signal of the first computer, the output 21 of the interrupt signal of the second computer, the output 22 of the readiness of the first computer, the output 23 of the readiness of the second computer, the outputs 24 and 242 of the signal about the end of the information message ki, the output 25 of the readiness signal of the first computer, the output 26 of the readiness signal of the second computer, the output 27 of the signal, the start of the clock generator, the output

28 of the information transmission resolution signal, the first 29 and second 30 computers information input 31 and output 32 of the serial code and input 33 of the device clock, information input 34 and output 35 of the parallel code of the device.

The device works as follows.

If the need arises for a computer

29 get information from the computer 30, then

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The shift register I is serialized to a specialized computer. At the same time, the information word from the specialized machine is transmitted through register group 2 to register 5. The sequence of information input to register bits 5 is determined by the control signals of the decoder 6. 1 Il.

five

0

five

0

35

40

it generates a write signal, which is fed to the input 16. According to the interrupt signal, the computer 30 generates a read signal at flow 19 and the next information word at input 35 and a readiness signal at input 23.

The information from register 5 is fed to the inputs of the corresponding elements of IZ. The high level signal from the element output AND 7 (the result of the signal coincidence is the readiness of the computer 30 and the recording mode of the computer 29) through the element OR 12 goes to the inputs of the element 3. The high signal from the output of the element OR 12 goes through the element OR 14 to the output 27 of the signal triggering the generator of synchronizing pulses, the computer 29 forms a series of clock pulses. The synchronizing pulses are fed to the input of the counter 4 and the input of the element 11. The counter 4 counts to (n + 3), where n is the number of bits of the transmitted information word, after which it returns to the initial state. In state 1, the signal from the corresponding output of the decoder 6 is fed to the inputs of the And 3 elements, and information from register 5 is transmitted to register 1. Under state 2, the high level signal from the corresponding output of the decoder 6 is fed to the zero input of the register 5, to the single trigger input 15 and output 28 of the information transmission permission signal. The trigger 15 goes into one state and the signal from its output goes to the input of the And 11 element, where it allows the passage of the next sync pulses to the clock input of the register 1. With the arrival of each clock pulse from the output of the register I, the next information bit is transmitted to the computer 29. When the counter (n + 3) is in state, the decoder 6 generates a signal about the end of the information packet, which is fed to the trigger input 15 and to the outputs 24 and 24g. zero state. This completes the transfer of one word of information from the second machine to the first. The transmission of subsequent words is organized in a similar way.

If the need arises for a computer

30 to receive information from the computer 29, the second machine generates a recording signal, which is fed to input 17, to output 20. The interrupt signal of the computer 29 generates a ready signal at input 22, which is fed to the second input of the fourth element And 10 and the output 25 of the ready signal first Computer device, the next word of information.

I

High output signal

element I 10 (the result of coincidence of signals: the readiness of the first machine is the recording mode of the second machine) through the element ШИИ 13 enters the inputs of elements И 2 and prepares them for operation, the input signal of the register record 5, where it allows receiving information from the outputs of elements И 2 and the input element OR 14. From the output of the element OR 14, the high level signal is fed to the output 27 of the trigger signal of the trigger of the synchronizing pulses of the computer 29 forms a series of clock pulses, which are fed to the input of the counter 4 and the first input of the AND 1I element. When counter 2 is in state, the high level signal from the corresponding output of the decoder 6 is supplied to the reset register 5, to the single output 28 of the information transfer resolution signal.

With the receipt of the information transmission permission signal, the computer 29 for each clock pulse (i.e., starting from the 3rd pulse of the series) is input

31 alternate bit word transfer information. The value of the next word bit determines the level of the SI1 at the first inputs of the elements.

And 2 (About - yizky level, 1 - high). Counter 4 counts the synchronous generator of synchronizing pulses, and decoder 6 generates control signals corresponding to the state of counter 4. When the cosses are. The computer 29 generates a series of clock pulses, which are fed to the input of the counter 4. In the state of the counter 2, a high level signal with a ratio of 3 produces a high signal

five

0

five

0

five

0

five

0

the level that enters the input of the first element And 2, the value of the first bit from the catch t of the output of the first element And 2 of the first group is entered in the first digit of the register 5.

When the signal level at the output of the element is low And the 2 state of the discharge 5 does not change, at a high level of the signal it becomes single. With the arrival of the fourth clock pulse, the second bit of the information word is output, counter 4 goes to state 4, and decoder 6 generates a high level signal that goes to the third input of second element 2. The second bit value of the word from the output of second element 2 is entered in the second bit d register 5 and etc. With the arrival (n + 2) of the clock pulse, all bits of the word will be entered into register 5. When the counter state is n + 3, the decoder generates a signal about the end of the information parcel, which goes to the outputs 24 / and 242 of the device and to the trigger input 15. With receiving The signal about the end of the information package of the computer 30 ensures that the parallel code word receives information from register 5 on the device output 25. This completes the transfer of one word of information from the first machine to the second. The transmission of subsequent words is organized in a similar way.

If the computer 30 does not require information from the computer 29, but is able to receive and process it, then it generates a readiness signal that goes to the device output 26 and to the input of the element 9. And if necessary, the information is transmitted from the computer 29 to the computer 30, the computer 29 forms the information word and the reading signal, which is fed to the input of the AND 9 element. The high level signal from the output of the AND 9 element through the OR 13 element enters the inputs of the AND 2 elements, preparing them for operation, to the input of the OR element 14, and to the input signal of the register 5, allowing the reception of information from And elements 2. The high level signal from the output of the element Р1ЛИ 14 is fed to the output 27 of the trigger signal

clock pulse generator

owls The computer 29 generates a series of clock pulses that arrive at the input of the counter 4. When the counter 2 is in state, the high level signal from the corresponding output of the decoder 6 is fed to the reset input of the register 5 and to the output 28. With the receipt of the information transmission signal, the computer 29 bit word transfer information. The order for further operation of the device is described above.

If the computer 29 does not require information from the computer 30, but is able to receive and process it, then it generates a ready signal that goes to output 25. If it is necessary to transfer information from the computer 30 to the computer 29, the computer 30 generates an information word and a reading signal The second allows the reception of information into the register 5. The high level signal from the output of the element AND 8 through the element OR 12 enters the input of the element OR 14 and the inputs of the elements FROM, where it allows the transmission of information from the register 5 to the register 1 The high level signal from the output of the element OR 14 enters exit 27 Igna run oscillator clock pulses. The computer 29 generates a series of clock pulses, which are fed to the inputs of the counter 4 and the element And I1. When counter 1 is in state, the high-level signal from the corresponding output of the decoder 6 is fed to the inputs of the IZ elements, after which information from the output of register 5 through the elements of 3 is transmitted to register I. When counter 2 is in state, the high level signal from the corresponding output of the decoder 6 goes to input zero register 5, to the input of the trigger 15 and output 2.8. The trigger 15 goes into one state and the high level signal from its output goes to the input of the element 11, allowing the passage of successive sync pulses to the input of register 1. The order of further operation of the device was considered earlier.

If both the second 30 and first 29 computers simultaneously generate recording signals, then two-way communication is performed. The recording signal of the computer 30 is fed to the output 20 and the input element And 10. The recording signal of the computer 29 is fed to the output 21 and the input of the element 7. With the receipt of the interruption signal, the computer 30 generates a reading signal, which is fed to the input 19 of the device and the signal input reading register 5, the next word

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information, which is fed to the input 34 and the read signal to the register 5, and the ready signal, which is fed to the inputs of the elements And 7 and 9 and. on the output 26 of the readiness signal of the second computer. The interrupt signal of the computer 29 generates a readiness signal, which is fed to the inputs of the elements 8 and 10 and the output 25 of the readiness signal of the first computer, and the next information word. The high level signal from the output of the element And 7 through the element OR 12 enters the inputs of the elements AND 3 and the element OR 14. The high level signal is J5 n from the output of the element AND 10 through the element OR 13 enters the input of the element OR 14, to the inputs of the elements AND 2 and to the input signal of the register 5, allowing the reception of information from the outputs

elements And 2 of the first group. The high signal from the output of the element OR 14 is fed to the output 27. The computer 29 forms a series of clock pulses, which are fed to the input of the counter 4

and the input element And 11. When the state of the counter 1 is high, the signal from the corresponding output of the decoder 6 is fed to the inputs of the elements And 3, passes information from the output

register 5 to register 1. In the state of the counter 2, the signal is high, level - from the corresponding output of the decoder 6 is fed to the input of zeroing the register 5 to output 28 and

trigger input 15. Trigger 15 goes into one state. Signal. high level from the output of the trigger 15 is fed to the input element And 11, which allows the passage of the next

synchronizing pulses to the input of the register 1. With the receipt of the information transmission permission signal, the computer 29 for each successive sync pulses (i.e., starting from the 2nd pulse of the series) sends the next bit of the information word transmitted to the device input 31. With the arrival of each successive sync pulse (i.e., starting with the 3rd pulse of the series), the control input of the register I is transmitted once again to the information word on output 32 of the device. In the state of counter 3, the signal is high with a certain output of the decoder 6

It appears on the input element And 2,. information from input 31. The value of the first bit of information transmitted from the output of the first element And 2 is written to the first

register bit 5. On the fourth clock pulse, the second bit of the transmitted information word is output at the 31st input. In the state of counter 4, the high level signal from the output of the decoder 6 is fed to the input of the second element 2 and the second bit of information from the output of the second element 2 is recorded in the second register of the register 5. Thus, for each clock pulse, starting from the 3rd one The word bit of information transmitted from computer 30 to computer 29 is transferred from register 1 to device output 32, and one bit of information sent from the first computer to the second is drained from device input 31 to register 5. With receipt ( n + 2) sync pulse all word bits info The transmissions are transmitted to the output 32 of the device and to the register 5. When the counter () is in state, the decoder 6 generates a signal about the end of the information parcel, which goes to the outputs 24 and 24 and to the trigger input 15. The trigger 15 goes to the zero state. With the receipt of the signal about the end of the information board of the computer 30, the parallel code of the word receives information from the register 5 on the output 35 of the device. This completes the transfer of a word pair of information. The transmission of subsequent pairs of words is organized in a similar way.

If both the first 29 and second 30 computers are ready for exchange and simultaneously generate reading signals, then the two-way exchange of information is organized as follows. The read signal of the computer 29 receives the input 18 of the device and the input of the third element I 9, to the other input of which a ready signal of the second computer arrives. The read signal of the computer 30 enters the read input of the register 5 and provides the reception of a word of information intended for transferring from the computer 30 to the computer 29 from the input 34 of the device to the register 5. The read signal of the computer 30 also goes to the input of the And 8 element, to another the input of which receives the readiness signal of the first computer. The high signal from the output of the element And 9 is fed to the input of the element OR 13, from the output of which it is fed to the input of the record of register 5, to the inputs of the elements AND 2 and the element OR 14. The signal is high

the level from the output of the element And 8 enters the input of the element OR 12 from the output of which goes to the inputs of the elements AND 3 and the element OR 14. The high level signal from the output of the element OR 14 enters the output 27. The computer 29 forms. It runs a series of clock pulses that arrive at the input of counter 4 and element 11. The order of further operation of the device when transmitting a word pair of information between two computers is similar to that described.

Claims (1)

Invention Formula 15 A device for interfacing two computers that contains a pulse counter, a shift register whose output is the output of the device for connecting the information input of the first computer, two groups of AND elements, an information register, a read enable input and the first information input and the output of which are, respectively, the inputs and the output of the device for connecting the output of the reading signal and the information output and input of the second computer, the outputs elements of the first group are connected to the second information input of the information register, and the first inputs are the input of the device for connecting the information output of the first the computer, the first inputs and outputs of the elements of the second group are connected respectively to the second output of the information register and the information input of the shift register, the counter input is the input of the device for connecting the clock output of the first computer, characterized in that A descrambler, five AND elements, three OR elements, a control trigger are entered into it, with the outputs of the first and second OR elements being connected respectively to the first and second inputs of the third element OR and the second input el8meN | Both the first and second groups, the third inputs of the elements of the second group are connected to the first output of the decoder, the output group of which is connected to the third inputs of the elements of the first group, the second output of the decoder is connected to the reset input of the register and the installation input 91 control trigger, the reset input of which is connected to the third output of the decoder, connected to the output of the pulse counter, the enable input of the information register recording is connected to the output of the second element OR, the outputs of the first and second elements AND, are connected respectively to the first and second inputs of the first element OR, outputs the third and fourth elements AND are connected respectively to the first and second inputs of the second element OR, the first inputs of the first and fourth elements AND are in the inputs of the device for Connecting outputs recording signals of the first and second computers, the first and second inputs of the third AND gates are respectively input device for coupling the output signals of the read first and second computers, the second inputs of the second. 0746110 the fourth and first, third elements And are respectively the inputs of the device for connecting the outputs of the ready signal of the first and 5 of the second computer, the clock input of the shift register is connected to the output of the fifth element I, the first input of which is connected to the output of the control trigger, and the second input fO is connected to the input of the device for connecting the clock output of the first computer, the second output of the decoder and the output of the third element OR are, respectively, 5 outputs of the device for connecting the information transfer permission inputs and starting the clock generator of the first computing machine, the third output of the decoder is 20 The output of the device is to connect the inputs to the end of the information board of the first and second computing machines.