SU997254A2 - Error correcting device - Google Patents

Description

(54) DEVICE TO FIX ERRORS

This invention relates to communication and computing technology and. It can be used in systems of transmitting information and information subject to interference. i -.

According to the main AV-1. St. No. 729849, a device for error correction is known, which contains a repetition counter, the output of which is connected to the input of the switch, and the input to the inputs of the first and second adders and control key, the other inputs of which are connected to. the outputs of the first and second KiySKK opoSf shift register and switch, and the output to the input of the shift register, the decoder adder, whose inputs are connected to the outputs of the shift register, and the outputs to the inputs of the majority element, the output of which is connected to the output of the switch, the additional shift register, the input of the second key and the output of the majority element, the error maker and the comparison element, the first input of the KQ is connected to the input 11, the second input. - to the output of the majority element, and the output through the error counter - to one of the inputs i of the commumrator

The decoding of a code combination in a device occurs in the following way: if the multiplicity of errors in the received messages is more. the maximum multiplicity of errors, is; equal to the correction code), then for decoding the code combination, three premises are necessary, if- {X maxo / then for decoding and correcting

10 errors must be at least two parcels of information 1 D.

A disadvantage of the known device is its low speed.

15

The purpose of the invention is to improve the speed of the device.

The goal is achieved in that the error correction device containing the repetition counter, switch, key, shift register, counter, and comparison element is entered with AND elements, cheap counter, register, AND group of elements, and OR If element, and the counter outputs are connected to the inputs 25 of the element And, the output of which is connected to the control input of the decoder, the information inputs of which are connected to the outputs of the counter. repetitions, and the outputs;

30 the output of which is connected to the first input of the corresponding element AND of the group, the second inputs of the terminal are connected to the corresponding outputs of the additional shift register, the outputs of the elements of the AND group and the second key are connected to the inputs of the OR element, the output of the second is the output of the error correction device. The drawing shows a block diagram of a device for error correction. The device contains a repetition counter 1, the input of which is connected to the input of the device, the first key .2, the shift register 3, adders 4 and 5, the switch 6, the counter 7, the comparison element 8, the decoder adders 9, the decoder 10, the element 11 And register 12, second key 13, additional shift register 14, majority element 15, group of elements 16 AND, element 17 OR. The outputs of the counter 1 reps connect nen. The inputs of the switchboard bis information inputs of the decoder 10 The inputs of the first key 2 are connected to the inputs of the device, the outputs of summers 4 and 5, and the outputs of switch 6. The code of the first key is connected to the input of the shift register 3, the outputs of which are connected to the inputs of the adder 9 of the decoder and the adders 4 and 5, the inputs of which are connected to the input of the device Other, the input of the switch 6 is connected to the output of the counter 7, which is connected to the input of the element 11 AND, the other output of the switch 6 is connected to the input of the second key 13. The input of the counter 7 is connected to the element 8 cf An input, one input of which is connected to the input of devices and another, with an output of the majority element 15, whose inputs are connected to the outputs of the adder-decoder 9. The output of the majority element 15 is connected to the input of the additional register 14shift. The control input of the decoder 10 is connected to the output of the element 11 And, the outputs of the decoder connected to the inputs of the register 12, the outputs of which are connected to the first inputs of the corresponding elements AND group 16. The output of the second key 13 is connected to the input of the element 17 OR, and the input of the second key 13 is connected to the output of the additional shift register 14, lower 1, the bit outputs of which are connected to the second inputs of elements AND of group 16, the outputs of elements AND of group 16 are connected to the inputs of element 17 OR, the outputs of which are outputs of the device for correcting mistakes. The device works as follows. When receiving (the First Send, the signal from the switch 6 puts the first key 2 into a position in which the received symbols are passed to the shift register 3. At the end of receiving the first send (code combination), the signal from the repetition counter I goes to the switch. 6, the output signal from which it puts the first key 2 in a position where signals from the first adder 4, operating according to rule 1-C 1; 1 + 0 ,, are passed to the shift register 3. Counter 7 is set to the zero state. The second parcel is simultaneously corrected. error correction in the first parcel with the help of decoders 9 and the major element 15. Each symbol of the second parcel is compared in comparison element 8 with the corresponding corrected first parcel symbol, which is written into the additional shift register 14. If the symbols match, the first and second parcels of the element Comparison step 8 generates a single signal, by which counter 7 increases its state by one, it is advisable to consider two characteristic cases: the first or second messages are the error rate. The first or second packages are the multiplicity of errors. Oi P / wG cc. About the presence of errors, the multiplicity is greater than 1 d | indicates the state of the counter 7. After the reception of the second parcel, the signals from the repetition counter 1 and the counter 7 arrive at the switch 6, the signal from which puts the first key 2 in a position where the signals from the output of the second adder, 5, go to the input of the shift register 3 working according to the rule: 1 + 1 17 0 + 0-0; 0 + 1 0; 2 + 1 1; where the characters / coming from the 3 shift register are written first. Simultaneously with the reception of the third premise, errors are corrected with the help of adders 9 of the decoder and the majority element 15, and the entry of the corrected code combination is added to the additional register 14. At the end of the reception of the third premise, the signal from the count of 1 repetitions goes to the switch 6, which opens the second key 13 and corrected a code sequence is issued by a serial code via element 17 OR to the output of the device for error correction. In addition, it is possible to fix the corrected code combination with a parallel code. In another case, the second and corrected first parcels differ no more than cash, symbols, or coincide. When in counter 7 will be written. Number equal to p-d p-maximum

Claims (1)

Claim Device for correcting errors by ed. St. № 729,849 _t of t l ich ayuscheesya in that, in order to increase performance, it introduced an AND, decoder, register, a group of AND gates, an OR gate, wherein the counter outputs are connected to inputs of the AND gate, whose output is connected to a control input of decoder , the information inputs of which are connected to the outputs of the repetition counter, and the outputs - to the inputs of the register, each output of which is connected to the first input of the corresponding element AND groups, the second inputs of which>'are connected to the corresponding outputs of the additional shift register, the output And the group of elements and the second switch are connected to inputs of OR element whose output is an output device.