GB1214704A - Method of ensuring correct transmission of binary coded data - Google Patents

Abstract

1,214,704. Digital transmission systems. TELEFUNKEN PATENTVERWERTUNGS G.m.b.H. 11 April, 1968 [13 April, 1967], No. 17661/68. Heading H4P. In transmission of binary coded data, e.g. from a computer Q (Fig. 1), information passes to a first store Sp1 where it is coded with redundant information and transferred in parallel, block by block, to a second store Sp2 from which it is passed in series, timed by clock signals, through modulator Mod to channel K, and to an auxiliary store Hsp. At the receiver (Fig. 2) the information is demodulated at Dem, and the input is connected to an interference detector St monitoring the level of the modulated information. Interference causes the normal level to be exceeded, and St determines whether it is at such level or greater or less than the same. The demodulator output is connected to a decoder Dec for code checking, and the combined outputs of St and Dec control an acknowledgment transmitter QS to transmit a correct acknowledgment signal for each block if neither device indicates error, and an error acknowledgment signal if error is detected by either. The output of Dem passes the incoming information to a first receive store Sp3 from which it is transferred block by block to a second receive store Sp4, whose contents are switched by Sch to data sink S. On transmission of a correct acknowledgment the block of information associated therewith in store Sp3 is transferred to store Sp4, out of which it is nondestructively read to the data sink S. On occurrence of an error, an error acknowledgment signal is sent from QS over channel R to receiver QE (Fig. 1) which opens Sch to inhibit transfer of the block of information in Sp3 to Sp4, and the transfer of the erroneous block to the data sink S, so that the last correct block remains stored in Sp4 while transmitter QS is blocked and coincidence device K 0 is released. At the transmitter the readout of further data from Q into store Sp, is also inhibited by QE, and switch S1 closes to connect stores Hsp and Sp2 into a series closed ring, of which Hsp then contains at least that number of blocks of information as corresponds to the maximum possible loop transmission time plus a further block; store Hsp being appropriately dimensioned as a shift register. The ring information shifts cyclically and energizes the modulator Mod on passing store Sp2, and correct transmission acknowledgments are received for reception of successive blocks of information. An error acknowledgment initiates repetition of the cycle; while absence of an error acknowledgment unlocks data source Q and opens switch S1. The repeated blocks of information arrive successively in store Sp3, whose contents are compared by coincidence circuit Mo with the preceding correctly received block in store S4. Coincidence denotes the last correct block, and Ko releases QS so that the next block arriving (which was erroneous on first transmission) and succeeding blocks are processed normally. Synchronizing character blocks may be transmitted before each repetition; so that the receiver checks the received blocks for coincidence with the last received correct block following the synchronizing block, and at coincidence passes information to the data sink.