SU1193667A1 - Device for multiplying n-digit numbers - Google Patents

Abstract

A device for multiplying p-bit numbers containing multiplicative and multiplier registers, a matrix of elements AND, a group of gates, accumulating adder, a group of elements AND and a combinational adder, and the outputs of the digits of the register of multiplicable are connected to the first inputs of the elements of the And corresponding columns of the matrix, My outputs of the bits of the register of the multiplier are connected to the first inputs of the corresponding elements AND groups, the outputs of which are connected to the second inputs of the elements AND the corresponding rows of the matrix, the output of the first element the first row is connected to the input of the first discharge of the accumulator, the output of AND the n-th row of the matrix is connected to the input

Description

The invention relates to computing and can be used in the development of high-speed multiply devices of the asynchronous type.

The purpose of the invention is to increase the speed of the device.

The drawing shows a structural diagram of the proposed device for multiplying b-bit numbers (for the case of T | 4).

The device contains a register of 1 multiplicand, a register of 2 multipliers, accumulating adder 3 (made in the form of adder with memory transfer), a combination adder 4, a group of elements OR 5, a matrix of elements AND 6, a group of elements AND 7 a group of elements 8 delay, an element OR 9 , input 10 start operation, output 11 end of operation.

The device works as follows.

Suppose you want to multiply the n-bit multiplier X by the n-bit multiplier Y - 1010. In the initial state in the register 1 of the multiplicator is stored the binary code of the unsigned number X, in the register 2 of the multiplier - the binary code of the unsigned Y, adder 3 cleared. . .

The operation of the device starts from the moment the multiplication operation start signal is input to input 10 (this signal is fed to input 10 only once at the beginning of the operation, and the appearance of a signal at output 11 signals the end of the operation to multiply the numbers). After that, the output of the adder 4 forms the result С С4СзС2С 0101 + 0000 + 0001 ITO (the first term is equal to the inverse value of the multiplier Y; the second term comes from the outputs of the delay elements 8, the third term is the value of the input transfer of the adder 4). Since only C i 2. At the output of the element 7, a control signal is generated, which transmits the appropriately shifted multiplicand from the outputs of the elements 6 of the second row of the matrix through the elements OR 5 to the adder 3. This control signal is fed to the input of the element 8 2 delay and does not change its value throughout the entire summation of the first partial product in adder 3. After a time equal to the summation time of the first partial product in adder 3, at the output of delay element 82 are signal that entered the corresponding input of the adder 4, it forms a second summand 0100. At the output of the adder 4 is formed. the result is C, 0101 + 0100 + +0000 1001, with the result that the AND is formed at the output of the element. the control signal (since only 1), which transmits the appropriately shifted multiplicative from the outputs of the AND 6 elements of the fourth row of the matrix through the elements OR 5 to the inputs of the adder 3. This control signal arrives at the input of the 8-l delay element and does not change its value for the entire summing time of the second partial product in adder 3. After this, the output time of the delay element 84 is a signal that through the element OR 9 enters the transfer control input with mmatora 3 to permit the summation memory transfers it to form the bottom odnor result in the code, and is also supplied to the output 11, signals the end of the operation vsholneni therein multiplying two numbers.

The average multiplication time of two, n-bit binary numbers in the device is approximately equal to

t with

t +

tPn

-sl

- cm

-r- CP

about u

where tcM is the time of summation of p-bit numbers in adder 3 with memory of hyphenation; time required

summation of t-bit. numbers in adder 4 with the spread of hyphenation.

The first component in the above expression determines the average

0 number of summations performed

in the device on adder 3, assuming that the occurrence of zeros and ones in the bit dunh multipliers is equally likely. The second component characterizes the delay, which the adder 4 introduces to the total time of the operation (the signal that starts at the beginning of 5, no operation goes to input 10

311936674

and which, in the future, the multiplication process actually has to transfer, as appropriate, once through the entire sum of shifted multipliers into adder 3, into torus 4),

Claims (1)

DEVICE FOR MULTIPLICATION P-BIT NUMBERS containing the registers of the multiplier and the multiplier, the matrix of AND elements, the group of OR elements, the accumulating adder, the group of AND elements and the combination adder, with the outputs of the bits of the register of the multiplicable connected to the first inputs of the elements AND of the corresponding matrix columns, the direct outputs of the bits of the multiplier register are connected with the first inputs of the corresponding elements AND groups, the outputs of which are connected to the second inputs of the elements AND the corresponding rows of the matrix, the output of the first element And the first row of the matrix is connected by the input of the first discharge of the accumulating adder, the output of the nth element AND of the nth row of the matrix is connected to the input (2rt-l) of the th discharge of the accumulating adder, the outputs of the elements of the qth diagonal of the matrix (q, = 2 ..... 2p-2) are connected to the inputs ( <^ - 1) of the OR element of the group, the output of the rth element of the OR group (p = 1, ..., 2p-3) is connected to the input of the (p + 1) th discharge of the accumulating adder, the second input of each element And the group is connected to the output of the corresponding discharge of the combinational adder, the transfer input of which is connected to the input of the beginning of the operation of the device, the inverse outputs of the bits of the register of the multiplier are connected to the first inputs of the corresponding bits of the combinational adder, which, in order to increase the speed, it contains group of delay elements and elem nt OR, and an accumulator formed as a latched adder shifts, while the output 6 of the AND-th group (6 = 1, ..., η-1.) via the respective. the group delay element is connected. with the second input of the (6 + 1) th discharge of the combinational adder, the transfer output of which is connected to the first input of the OR element, the output of the h-ro element of the And group through the corresponding delay element of the group is connected to the second input of the OR element, the output of which is connected to the input of the control control carry accumulating adder and output end * ts ^ device operation.