SU690478A1 - Arrangement for sequential multiplying of n-digit binary codes - Google Patents

Description

The invention relates to the field of computing technology and is intended to multiply two synchronously n (k; numbers that are blunt in the sequential complementary code, in which the sign is contained in the nth digit and the lower bits first arrive.

A device is known for multiplying two numbers, simultaneously arriving in a sequential direct code, in which the sign is contained in the n-th bit and the low-order bits first arrive (I.

The known device, which performs multiplication in two cycles, contains the multiplier and multiplier shift registers, the allocator, the static register, the shift register, as well as the AND elements and consecutive one-bit adders.

The closest technical solution to the invention; is an apparatus for multiplying two synchronously incoming consecutive direct codes of numbers in which the sign is contained in the "th bit" and first comes the lower bits (2) containing the multiplicable shift register, the multiplier shift register whose output is connected to the inputs (p-I) of the elements AND

the first group, () -discharge-distributor, ka) kdyy1- and the discharge of which is connected through (i - f I) -and element AND of the first group with the input (i 4-1) -size (n - 1) - bit register, the first bit of which through the first element And the first group is connected to the control bus, which is connected to the input of the (n - 2) -disk allocator,

, (n - 2) -discharge shift register, output of th digit (n. - 1) -disk register and output of (1-1) th digit (n -2) -discharge shift register are connected to the inputs of the i-ro element AND, (n-I) of the elements of the second group, and the output of the first bit (n - 1) of the bit register and the input of (r - 2) -shift shift register are connected to the inputs of the first element AND of the second group . The outputs (2n - 1) of the second and second elements of the second group (K 1.2 ...,) are connected to the inputs K-g of a one-bit adder of the first group. The outputs (2cj- 1) -th and one-digit adders of the first group (1, 2, ..., - I) are connected to the inputs

th one-bit adder of the second group. The outputs of the last one-bit summer of the first group and the last bit of the last element AND the second group are connected to the inputs of the last one-bit adder of the second group. The outputs of one-bit adders of the (-1) -th group (f 1, 2, ..., logjn) are connected to the inputs of a sequential one-bit totalizer, paj, and group. . -; The low speed of such devices is due to the fact that when multiplying the numbers received in a sequential additional code, they are required to be converted into a direct code, i.e., P clocks are required additionally. The aim of the invention is to improve the speed.; T This is achieved by introducing other technologies into the proposed device. the elements OR, AND, NOT, the delay and and additional one-bit adders. The output of the shift register of the multiplicand is connected to one of the outputs of the first additional element, AND, the other input of which is connected through the first delay element to the output (n-2) of the discharge distributor, and the output is the code output of the first element OR , another entrance; which is connected to the output of the second element OR, the input of which is connected to the output of the first element OR, the output - with one of the inputs of the third element OR, the other input of which is connected to the output of the register of the multiplicand, and the output - to the input (n - 2) dNog shift register. The output of the register is connected to the interconnected from the input 6 in 1 of the second element And, the other input of which is connected to the output; the first delay element, and the output is to one of the inputs of the fourth OR element, the other input of which is connected to the output; the terminal is the OR element, the input is connected to the output of the fourth element, OR-8IN1 - to one of the inputs of the third element, The other VHBD of which is connected to the output of the First Delay Element, and the output to one of the inputs of the first control unit. a one-size DIoGr adder, with the OTHER input of which is connected to a 1AHYdOm; . the helicopter of an additional element, And, from the entrance of which is connected with the other; p tgr element OR, a; Another input 7 in the input element is NOT, the input which through the second delay element is connected To: B1- :, during the run (n-2) -d discharge6 of the sixth register, The output of the first additional one-digit adder is connected to oneDNA of the inputs of the second Additional one-digit adder, the other input of which is connected to the output of the third consecutive one-bit adder, and the output of the switch to the output bus of the device. One of the inputs of the Third additional odnoprazp dnagq adder is connected to v1: 4 one odd digit of the adder J.- and group, the other input to the output of the fifth element And, one input of which is connected to the output of the last digit (n - 2) -discharge distributor ,

Claims (2)

.690478 and another input - to the output of the one-digit adder J. - group. A functional diagram of the apparatus for multiplying successive p-discharge codes for case n 8 is shown in the drawing. The device contains a shift register multiplier 1, elements And 2-8 of the first group; (p-2) -discharge distributor 9, - 1) discharge static register 10, control bus P, (n - 2) -discharge shift register 12, elements 13 and 18 of the second group, successive one-bit adders of the first group 19 - 22, successively one-digit adders of the second group 23, 24, a sequential one-digit adder of the third group 25, a multiplicative shift register 26, additional elements AND 27, delay elements 28, elements IL AND 29 - 31; Additional one-digit adder 36, additional elements NOT 38, elements .., -. ,,. . delays 39, the supplementary one | 5sr d ers 40–4, the input bus 42.: CR.yyr, .. element. Rounding 43. The device works as follows, IN the original CONDITION additional multipliers and Myo $ are placed respectively in the multiplier shift registers and multiplicand. 26. From registers 1 and 26 these codes are given by the lower bits. Forward and are contained in the first bits of the codes. In the first cycle of the multiplier shift registers, the minor multiplier and multiplier bits are supplied. In the same cycle, a single signal is sent to the control bus 11, which opens element 2 at the first cycle, element 3 at the second cycle, etc., and element IV at the seventh cycle, since the control bus I starting from the second cycle, a zero signal is given. As a result, the fraction of the multiplier code is written into the static register 10. Let the multiplicative equals -0.101 SPC. and the factor is -0.1100101 (Then FROM the shift register, multiplier 26, the additional iodine 1.010010 is fed, and from the shift register of the multiplier 1 - the additional code 0.1100101.; At the first; output pulse And 2 will be a single signal, which will be written into the first trigger (pL) -discharge register 10. At the output of the element-OR 30 will be zero Sigi a lz-due to the presence of a zero signal at the output of the delay element 28. As a result, at the output of the element 19 there will be a single signal that through a chain of one-bit adders -20, 23, j25, 41 fl 40 prodOdyt on the output line 42 of the device, Since the outputs of the elements And 13; 18, 35, 37 and 43 will be zero signals. At the second cycle at the output of the element And 3 there will be a signal that records the 30 second trigger of the (n - 1) discharge register 10. In the first discharge register 12 is written 1. As a result, at the output of the element And 19, we obtain the product of the first bit multiplier by the second bit of the multiplicand (zero signal), and on the course of the element And 13, the product of the second bit m | 1 resident for the first bit of the multiplicand (zero signal ). Next, at the output of the adder 20, we have a single signal that passes through the chain of adders 23, 25, 41 and 40 to the output 42 of the device. Further, the device works in a similar way. In the seventh cycle from the last bit output (and - 2) -discharge distributor 9, the rounding element AND 43 is turned on. In this case, the output of the adder 36 has a zero signal, since the outputs of the elements 35 and 37 have zero signals due to the presence of a zero signal at the output of the delay element 28, and in the adders 40 and 42 the transfer is zero. As a result, if at the seventh cycle, at the output of the adder 25, we have a single signal, it is remembered in the adder 41 as a single transfer. Starting from the eighth cycle, the AND 43 rounding element gives out cortst O, and from the output 42 of the device we remove significant bits of multiplication. At the eighth cycle, the output of delay element 28 will be a single signal. As a result, due to the presence of a unit in the sign: the element that is multiplied by the element OR 31 is output-, gives const 1; On the fifteenth clock cycle, the device issues a multiplication sign, and the device operation ends on this. For the considered example, the device from the eighth to the fifteenth clock cycle shows the result of multiplication in the additional code 1.01 PTUO () If there is a unit multiplier in of the eighth clock cycle, the OR element 34 outputs 1. As a result, at this clock step from the AND 35 element, one is fed to the input of the adder 36. To the other input of which from register 12 through the delay element 39 and the elements NOT 38 and 37 is fed the Reverse multiplicand code. Thus, the device multiplies consecutive additional G1-ra: binary binary codes by 2n-1 cycles. The invention makes it possible to increase fast; Rotation of the device for multiplying consecutive and-bit binary codes by n clock cycles. Claims of the invention A device for multiplying consecutive p-bit double codes, supporting the multiplier shift register, the multiplier shift register j, the output of which is connected to the inputs (n I) of the AND elements of the first group, (n – 2) -disable distributor. 690478 each 5th bit of which is connected via (I + 1) -y element AND of the first group with the input of (X-1) -th digit (n - 1) -bit register, the first bit of which through the first element AND of the first group is connected to the control bus, which is connected to the input of the (n-2) -disable distributor, (n-2) -disable shift register, the output of the {-th bit (n - I) -disable register output (} - f) -ro bit (and -2) -par d of the shift register are connected to the inputs of the i -th element AND, (n - 1) elements of the second group, and the output of the first bit (h-1) -d discharge register and input (n -2) bit of the first shift register are connected to the inputs of the first element of the second group, and the outputs of the (2k-1) -th and th (-th elements, --- - .. and the second group (to 1, 2, ...,) are connected with inputs of a one-bit single-digit adder of the first group, outputs (2q-) of a single and single-digit adders of the first group (j I, 2, ...,) are connected to the inputs of the i-th single-bit adder of the second group, outputs of the last one-bit the adder of the first group and the last element And the second group are connected to the inputs of the last one-bit sum of the second Thor, the outputs of the one-bit one sum Hur (j- 1) th group (s) 1, 2, ..., logan) are connected to the inputs of the adder-stand odnorazr f-th group, characterized JGM, that in order to improve performance in. it, additional elements are introduced; you are OR, AND, NOT, delays and additional one-bit adders; the output of the multiplicand shift register is connected to one of the inputs of the first element AND, the other input of which is connected to the output through the first delay element one of the inputs, the first element OR, the other input of which is connected to the output of the second OR element, whose input is connected to the G output of the first branch OR, and the output to one of the inputs of the third OR element, the other the input of which is connected to the Re Out the multiplier shift source and the output to the input of (n 2) -discharge shift register, the output of the multiplier shift register is connected to one of the inputs of the second And element, the other input of which is connected to the output of the JBorb delay element, and the output to one of the fourth inputs element, whose other input is connected to the output of the OR element, whose input is connected to the output of the fourth OR element, and the output to one of the inputs of the third AND element, the other input of which is connected to the output of the first delay element, and the output from inputs first th additional odnorazr summatfa-stand, Dru goy input of which is connected to the output of the fourth AND gate, one of whose inputs. connected to the output of the fifth OR element, and another input to the output of the NOT element, whose input is connected to the output through the second delay element (n - bit shift register, the output of the first additional one-bit adder is connected to one of the inputs of the second additional one-bit adder , the other input of which is connected to the output of the third additional one-bit adder, and the output is connected to the output bus of the device, one of the inputs of the third additional one-bit adder is connected to one A different adder of the j-th group, another input - with the output of the fifth element I, one of the inputs of which is connected to the output of the last digit (-2) of the bit distributor, and the other input - to the output of the one-bit adder j of the group. Sources of information taken into account in the examination 1.Zak vek number 1994659/24, class G 06 F 7/39, 07.02.74, which made the decision to issue an author's certificate. 2. Pevtsov D.V. and others. Elementary computational operations in homogeneous media with independent tuning. Sat “Questions of cybernetics. Uniform microelectronic structures. M., “Soviet Radio. 1973, p. 88, fig. four.