SU1367156A1 - Parallel-series a-d converter - Google Patents

Abstract

The invention relates to information-measuring technology and can be used in radar, experimental physics, automation and telemechanics. Into a device containing first and second analog-to-digital converters 1 and 2, digital-to-analog converter 3 and subtraction unit 4, in order to eliminate gross measurement errors in the docking areas of the exact and coarse scales of the two-rack analog-to-digital converter while reducing the requirements to the accuracy of the first analog-digital converter, the first and second binary counters with S (L

Description

0-

7 ./

.n-and

00 05

|

ate

1367

5 and 8 pulses, the element OR 6, the element 2 OR-AND-HE 7 and the control block 9. An introduction to the parallel-to-serial analog-to-digital converter of the above-listed nodes with appropriate connections ensures the functioning of the device, with

By the torus, the signal from the subtractor does not exceed the limits of the worker. range of the second analog-to-digital converter, which allows you to completely eliminate gross measurement errors in the docking areas of coarse and accurate scales. 1 hp f-ly, 4 ill.

one

The invention relates to a control and measurement technique and can be used in radar, televisation, experimental physics, automation and telemechanics.

The purpose of the invention is to eliminate gross measurement errors in the docking areas of an accurate and coarse cabinet of a two-scale analog-digital converter while reducing the accuracy requirements of the first analog-digital converter.

Figure 1 shows the structural diagram of a two-scale analog-to-digital converter; Figures 2 and 3 are diagrams given below; operation of the device is not; Fig. 4 is a block diagram of the control unit.

The converter contains the first and second analog-to-digital converters 1 and 2, the digital-to-analog converter 3, the subtraction unit 4, the first binary counter 5, the logical element OR 6, the logical element 2OR-AND-NE 7, the second binary counter 8, the control unit 9. The control unit is made on the trigger 10, the clock generator 11, the eight-channel distributor 12 pulses, the element OR 13, the driver 14 short pulses.

The coding process of the input voltage starts at the Start 10 signal, which enters the input of the control unit 9. On this signal, the control unit generates a series of control signals 11-14. Signal 11 from its first output gates the first analog-to-digital converter 1, and at the output of the last binary code appears proportional to the input voltage, all bits of which, except the lows

are fed to the information inputs of the binary counter 5. At the end of the cycle of operation of the first analog-digital

the converter by the first signal 12 from the third output of the control block 9 causes the received code to be entered into the counter 5 and switching to a single state of the two-digit binary counter 8, which by a direct output of the first bit transfers the first binary counter 5 to the power mode, and the inverse output of the first bit yes unlocks the first half of logic element 7. If the output signal of element 6 is low, which corresponds to the zero code of the first analog-digital converter, the signal is high

The level from element 7 blocks the operation of counting in the counter 5. If the code of the analog-digital converter 1 is not zero, the second signal 12 from the third output of the control unit subtracts one from the code written into counter 5. By the same signal, one is added to counter 8 and it sets a code equal to two. As a result, at the control inputs

counter 5, the potentials corresponding to the addition mode are set. (zero at the first control input and one at the second).

After a certain time required for the completion of transients, the digital-to-analogue converter 3 and the subtraction unit 4 use the signal 13 from the second output of the control unit to start the second analog-to-digital converter .2, the output of which is a code representing the exact bits output device code. If the result of converting the analog-digital converter 2 contains the unit 1 in the higher (K + 1) -th bit, the triangle 7 switches the counter 5 to the addition mode and the third signal 12 from the third output of the control unit 9 performs the operation of adding the unit to a coarse code , previously recorded in counter 5. In the zero state of the most significant bit of the analog-digital converter 2 by a high level signal from the output of element 7, this operation on the first control input

counter 5 is blocked. Specified altogether, in practice, in contrast to the requirement, it actually performs the operation of summing the contents of the high bit of the second analog-to-digital converter with the coarse code obtained in the first stage of measurements.

Introduction of the listed nodes with corresponding connections to a two-scale analog-to-digital converter allows one to eliminate gross measurement errors at the coarse and precise scales docking sites and significantly reduce the accuracy requirements of the first single-scale analog-to-digital converters. With their help, such a systematic additive perturbation of the device is ensured, in which the resolutions in the digital-analogue level of the signal of the subtractor device do not go beyond the operating range of the second analog-digital converter, corresponding to two units of the smallest coarse scale, large deviations from the nominal parameters of the main units of the device.

Suppose that a digital-to-analog converter, a subtractor, and a second analog-to-digital converter are ideal and do not introduce errors. Let () th

the coder and the adder appear in the offset of the cjrMM threshold conversion function, which

35 can be easily corrected by well-known methods.

Let us consider the second extreme situation in which in a known device the violation of a normal

40 functioning of the second analog-to-digital converter and the appearance of gross errors. For her, the 21st level of quantizing the first analogue. digital converter has

the odd level of quantization of the first 45 is positively offset, and Ug is

between 2i-M and (21-1) level. At the same time, the output code of the first analog go-digital converter exceeds one. Then, in accordance with the operation algorithm of the device, the counter content of the counter block signal decreases by one and the difference signal at the input of the subtractor is equal to UB

the analog-digital converter is installed with a negative error uU2; (Fig. 4), and the measured voltage level Ug lies between its (21 + 1) th and (2i + 2) -M quantization levels 50. Then, in accordance with the considered algorithm of the device operation, as a result of dropping the Mpadshi bit in the output code, the interim 2i-M and (21-1) -th levels. At the same time, the output code of the first analog go-digital converter exceeds one. Then, in accordance with the operation algorithm of the device, the counter content of the counter block signal decreases by one and the difference signal at the input of the subtractor is equal to UB

55 analogue digital converter The absolute value of u, U at

l to the input of the deducting device receives a differential signal i U

and

in

- U; where U; - eg the level of sampling U, - and U

Zi i

Thus, the digital-analogue converter is transformed in this case as

Tits and.;., and .;

l, corresponding to the ideal position of the 2i-ro node of the scale of the first analog-digital converter. Obviously & and in this case can be zero only when

i.e. the absolute error in setting the quantization step of the first analog-to-digital converter in the limit can be comparable to its nominal value or to half the coarse quantization step of the entire device. It is also obvious that this condition can easily be satisfied with the absolute error of the first analog-to-digital converter in the prototype, where it should be less than the quantization step on an exact scale.

Similar to this, small deviations from the nominal position of the nodes of the D / A converter cabinets, as well as small systematic errors of both characters of the subtraction device and the second analog-digital converter do not disrupt the normal operation of the proposed device and do not cause gross errors as a result of measurements. The maser and the summing device manifests itself in a threshold offset of the cjrMMap conversion function, which

can be easily corrected by known methods.

Consider the second extreme situation in which in a known device a violation of the normal

functioning of the second analog-to-digital converter and appearance. gross errors. For her, the 21st level of quantizing the first analog. digital converter has a positive offset, and Ug is

between 2i-M and (21-1) level. Let the output code of the first analog-to-digital converter exceed one. Then, in accordance with the algorithm of the device operation, the counter content is reduced by one by the signal of the control unit and the difference signal at the input of the subtractor is UB

this does not exceed two coarse-scale quanta even when the level

sampling U, - and U

Zi i

Thus, in the previous one, comparable to the nominal quantization step of the first analog-to-digital converter, the errors in its installation do not cause disruptions in the operation of the second analog-to-digital converter and do not affect the measurement accuracy.

Claims (2)

1. Parallel-to-serial analog-to-1-digital converter containing the first (n + 1) -discharge and second K-bit analog-to-digital converters, the information input of the first of which is combined with the forward input of the subtraction unit and is the input bus, inverse the input of the subtraction unit is connected to the output of the digital-analogue converter, the inputs of which are the output buses of the higher bits, and the output of the subtraction unit is connected to the information input of the second analog-digital converter, the outputs of the first through (K-1) -th Predicted are low-order output buses, characterized in that, in order to increase the conversion accuracy by eliminating measurement errors in the docking areas of the exact and coarse scales, the first and second binary pulse counters, element, are introduced into it. NAND, the control unit whose input is a Start bus, and the first and second outputs are connected to control inputs of the first and second analog-to-digital converters, respectively, the output of the first bit of the first of which is connected to the first input of the element and OR, the other inputs of which are combined with the corresponding inputs of the first setup pulse and a binary counter connected to the corresponding outputs of the second to (n + 1) s bits of the first analog-to-digital converter, the output OR element connected to the first input element 2IL-AND-NOT, the second input of which is connected to the inverse output of the first discharge of the second binary pulse counter, the direct output of the first discharge of which is connected to the first control input of the first binary pulse counter, the outputs of which are connected by the corresponding inputs of a digital-analogue converter, and the second control input is connected to the direct output of the second discharge of the second binary pulse counter, the inverse output of the second discharge of which is connected to the third input of the element 2Ш1И-И И И НЕ, the fourth input of which o is connected to the output (K + O-th bit of the second analog-digital converter, and the output is connected to the third control input of the first binary pulse counter, the clock input of which is combined with the same name input of the second binary pulse counter and connected to the third output of the control unit, the fourth output of which is connected to the installation input of the second binary pulse counter. 2. The converter according to claim 1, which means that the control unit is made on a trigger, the input of which is set to 1 which is connected to the input of the control unit, and the output through the clock generator is connected to the input the eight-channel pulse distributor j whose output of the first channel is the first output of the control unit, the second output of which is the output of the sixth channel of the pulse distributor, the outputs of the BTOIJO, third and seventh channels of which are connected respectively to the first, second and third inputs of the OR element, outputwhich is the third output of the control unit, and the output of the eighth channel of the pulse distributor through the short pulse shaper is connected to the installation input to the O flip-flop and is the fourth output of the control unit, pn .- pp p l qp l qpLfff.Z Cjpue.3 ten (ri & l 12 /five