RU2132043C1 - Gear for autonomous measurement of physical quantities - Google Patents

Abstract

FIELD: measurement technology. SUBSTANCE: gear is designed for use in measurement systems functioning autonomously at all stages from perception to processing and usage of measurement information. Gear includes two units of instrument converters, two controlled commutators, comparator meant to control commutators. Divider is positioned across output of one of commutators. Gear also has N output comparators and (N-1) groups of elements each incorporating inverter, commutator and adder. These groups are coupled to output comparators whose outputs are information outputs of gear. Binary code registered in them corresponds to measurement result. Its further processing is carried out in digital form. Given gear makes feasible to increase speed of response by 2^N times as compared with known analogs if summary time of transition processes in mentioned above groups of elements does not exceed period of clock frequency of gate generators. EFFECT: increased speed of response of gear. 1 dwg

Description

 The invention relates to measuring equipment and can be used in measuring systems that operate autonomously from a person at all stages from perception to processing and use of measurement information.

 A device for autonomous measurements of physical quantities, implemented according to the method [1].

 The disadvantage of this device is the low speed.

 A device for offline measurements of physical quantities, implemented according to the method [2], containing two blocks of measuring transducers, two switches, a comparator, an inverter and a divider.

 The disadvantage of this device is the lack of performance.

 The aim of the invention is to improve the performance of the device.

 The drawing shows a diagram of a device for autonomous measurements of physical quantities.

 The device contains two blocks 1 and 2 of the measuring transducers, the outputs of which are connected respectively to the first and second inputs of the first 3 and second 4 managed switches, a comparator 5, the direct input of which is connected to the output of the first 1 block of measuring transducers, and the inverse to the output of the second 2 blocks measuring transducers. The output of the comparator 5 is one of the outputs of the device and is connected directly to the control input of the first 3 switch and through the inverter 6 to the control input of the second 4 switch, the output of which is connected to the input of the divider 7, which has N outputs. The device also contains N output comparators and (N-1) a group of elements including an inverter 9, a switch 10 and an adder 11. In each such group, the output of the inverter 9 is connected to the second input of the switch 10, the output of which is connected to the second input of the adder 11, the output of which connected to the first input of the adder 11 of the subsequent group and the inverse input of the corresponding output comparator 8, the output of which is connected to the control input of the switch 10 of the subsequent group. The output of the first 3 switch is connected to the direct inputs of the N output comparators 8. The first output of the divider 7 is connected to the first input of the adder 11 of the first group and the inverse input of the first output comparator 8, the output of which is connected to the control input of the switch 10 of the first group. The subsequent (N-1) outputs of the divider 7 are connected to the inputs of the inverters 9 and the first inputs of the switches 10 of the corresponding groups. The outputs N of the output comparators 8 are information outputs of the device.

 The device operates as follows.

When the units 1 and 2 of the measuring transducers are operating, the outputs U ₁ and U ₂ , respectively, carry information on the measured quantities that characterize any property of the objects, respectively. The values of U ₁ and U ₂ from the outputs of blocks 1 and 2 are respectively supplied to the direct and inverse inputs of the comparator 5, which performs the operation of comparing them. Moreover, its output signal carries information about which of the two values U ₁ or U _{2 of the} measured values is greater (or less) with respect to each other. The signal from the output of the comparator 5 controls the operation of the first 3 and second 4 switches. At the same time, it goes directly to the control input of the first 3 switches, and to the control input of the second 4 switches through inverter 6. If U ₁ <U ₂ , then the value of U ₁ is supplied to the output of the first 3 switches from its first input, and the output of the second 4 of the switch from its second input, the value U ₂ is supplied. If U _1> U _2, 3 on the output of the first switch to its second input is fed U ₂ value and to the output of the second switch 4 with its first input - the value U _1. Thus, the output of the first 3 switch is always the smaller of the two values U ₁ or U ₂ , while the output of the second 4 switch is always the larger of them.

For definiteness, let U ₁ <U ₂ . Then at the output of the first 3 switch will be the value of U ₁ , and at the output of the second 4 switch - the value of U ₂ . The latter goes to the input of the divider 7, which carries out N division U ₂ on the basis of the number system, in which the measurement result raised to the appropriate degree will be presented. When at the outputs of the binary radix divider 7 will present N values U _2/2 ^1, U _2/2 ^2, U _2/2 ³ ..., U _2/2 ^N. The number of outputs of the divider 7 corresponds to the number of bits representing the measurement result. The accuracy of the measurement result is determined by the least significant bit whose weight is equal to U _2/2 ^N. Thus, the larger N, the higher the measurement accuracy and the better the resolution of the device.

The signal from the output of the first 3 switch goes to the direct inputs of the output comparators 8. In this case, for definiteness, this will be the signal U ₁ .

(1)
Сигнал U₂/2² со второго выхода делителя 7 поступает непосредственно на первый вход коммутатора 10 первой группы элементов 9, 10, 11, а на второй его вход - через инвертор 9. На управляющий вход этого коммутатора поступает сигнал A₁ с выхода первого выходного компаратора 8. Если сигнал A₁=1, то на выходе коммутатора 10 первой группы будет присутствовать сигнал U₂/2². Если сигнал A₁= 0, то на выходе этого коммутатора будет присутствовать инверсный сигнал (-U₂/2²). Сигнал с выхода коммутатора 10 первой группы поступает на второй вход сумматора 11 этой же группы, первый вход которого объединен с инверсным входом первого выходного компаратора 8, и, следовательно, на него поступает сигнал U₂/2¹. В итоге на выходе этого сумматора будем иметь сигнал

(2)
Сигнал X₁ поступает на инверсный вход второго выходного компаратора 8, на прямой вход которого поступает сигнал U₁ с выхода первого 3 коммутатора. Если U₁<X₁, то на выходе (обозначим его A₂) этого компаратора будет уровень логического нуля. Если U₁>X₁, то на его выходе будет уровень логической единицы, то есть

(3)
Сигнал U₂/2³ с третьего выхода делителя 7 поступает аналогично предыдущему случаю непосредственно на первый вход коммутатора 10 второй группы элементов 9, 10, 11, а на второй его вход - через инвертор 9. На управляющий вход этого коммутатора поступает сигнал A₂ с выхода второго выходного компаратора 8. Если сигнал A₂=1, то на выходе коммутатора 10 второй группы будет присутствовать сигнал U₂/2³. Если A₂=0, то на выходе этого коммутатора будет присутствовать инверсный сигнал (-U₂/2³). Сигнал с выхода коммутатора 10 второй группы поступает на второй вход сумматора 11 этой же группы, первый вход которого объединен с инверсным входом второго выходного компаратора 8 и, следовательно, на него поступает сигнал X₁, определяемый выражением (2). В итоге на выходе этого сумматора будем иметь сигнал

(4)
Сигнал X₂ поступает на инверсный вход третьего выходного компаратора 8, на прямой вход которого поступает сигнал U₁ с выхода первого 3 коммутатора. Если U₁<X₂, то на выходе (обозначим его A₃) этого компаратора будет уровень логического нуля. Если U₁>X₂, то на его выходе будет уровень логической единицы, то есть

(5)
Аналогично работают последующие группы элементов 9, 10, 11. При этом на выходе сумматора 11 последней (N-1) группы элементов 9, 10, 11 будем иметь сигнал X_N-1 следующего вида

(6)
Сигнал X_N-1 поступает на инверсный вход последнего N-ого выходного компаратора 8, на прямой вход которого поступает сигнал U₁ с выхода первого 3 коммутатора. Если U₁<X_N-1, то на выходе (обозначим его A_N) этого компаратора будет уровень логического нуля. Если U₁>X_N-1, то на его выходе будет уровень логической единицы, то есть

(7)
Таким образом, двоичный код, зафиксированный на выходах компараторов 5 и 8, будет соответствовать результату измерения. Здесь выходной сигнал компаратора 5 несет информацию о том, какое из двух значений U₁ или U₂ измеряемых величин больше (или меньше) по отношению друг к другу, а сигналы A₁, A₂,... A_N выходных компараторов 8 соответствуют информационным разрядам. При этом A₁ является старшим разрядом, a A_N - младшим разрядом.The signal U _2/2 ¹ 7 the first divider output is supplied to the inverting input of the first output of the comparator 8. When U ₁ <U _2/2 ^1, the output (denoted by A ₁₎ of the comparator is logic-zero level. If U _1> U _2/2 ^1, then its output Buda logic one level, that is,

(1)
The signal U _2/2 ² with the second output of the divider 7 is supplied directly to a first input of the switch 10 of the first group of elements 9, 10, 11, and on its second input - the inverter 9. At this switch control input receives the signal A ₁ output from the first output comparator 8. If the signal A ₁ = 1, the output switch 10 of the first group will be present signal U _2/2 ^2. If the signal A ₁ = 0, the output of the switch will be present negated signal (-U _2/2 ^2). The signal output from the switch 10 of the first group is supplied to a second input of the adder 11 of the same group, of which a first input is combined with the inverted input of the first output of the comparator 8, and therefore, it receives the signal U _2/2 ^1. As a result, at the output of this adder we will have a signal

(2)
The signal X _{1 is} fed to the inverse input of the second output comparator 8, the direct input of which receives the signal U ₁ from the output of the first 3 switch. If U ₁ <X ₁ , then the output (denoted by A ₂ ) of this comparator will be the level of logical zero. If U ₁ > X ₁ , then its output will be the level of a logical unit, i.e.

(3)
The signal U _2/2 ³ 7 output of the third divider receives the previous case directly to the first input of the switch 10 of the second group of elements 9, 10, 11, and on its second input - the inverter 9. At this switch control input receives the signal from A ₂ output from the second output of the comparator 8. If the signal A ₂ = 1, the output switch 10 of the second group will be present U _2/2 ³ signal. If A ₂ = 0, the output of the switch will be present negated signal (-U _2/2 ^3). The signal from the output of the switch 10 of the second group is fed to the second input of the adder 11 of the same group, the first input of which is combined with the inverse input of the second output comparator 8 and, therefore, the signal X ₁ defined by expression (2) is supplied to it. As a result, at the output of this adder we will have a signal

(4)
The signal X _{2 is} fed to the inverse input of the third output comparator 8, the direct input of which receives the signal U ₁ from the output of the first 3 switch. If U ₁ <X ₂ , then the output (denoted by A ₃ ) of this comparator will be the level of logical zero. If U ₁ > X ₂ , then its output will be the level of a logical unit, i.e.

(5)
The subsequent groups of elements 9, 10, 11 work similarly. At the same time, at the output of the adder 11 of the last (N-1) group of elements 9, 10, 11, we will have a signal X _{N-1 of the} following form

(6)
The signal X _{N-1 is} fed to the inverse input of the last N-th output comparator 8, the direct input of which receives the signal U ₁ from the output of the first 3 switch. If U ₁ <X _N-1 , then the output (denoted by A _N ) of this comparator will be the level of logical zero. If U ₁ > X _N-1 , then its output will be the level of a logical unit, i.e.

(7)
Thus, the binary code fixed at the outputs of the comparators 5 and 8 will correspond to the measurement result. Here, the output signal of the comparator 5 carries information about which of the two values U ₁ or U _{2 of the} measured values is greater (or less) with respect to each other, and the signals A ₁ , A ₂ , ... A _{N of the} output comparators 8 correspond to information discharges. Moreover, A ₁ is the most significant digit, and A A _N is the least significant digit.

Further processing of the measurement result can be performed digitally. Mathematically, the measurement result, connecting the values of U ₁ and U ₂ , is written as follows:
if U ₁ <U ₂ , then
U ₁ = U ₂ [A ₁ (1/2 ¹ ) + A ₂ (1/2 ² ) + ... + A _N (1/2 ^N )], (8)
if U ₁ > U ₂ then
U ₂ = U ₁ [A ₁ (l / 2 ¹ ) + A ₂ (l / 2 ² ) + ... + A _N (1/2 ^N )], (9)
where A ₁ , A ₂ , ..., A _N - data (bits of information) recorded in comparators 8.

Information on the representation of the measurement result in the form of (8) or (9) is recorded in the comparator 5. As shown above, the signal from the output of the comparator 5 carries information about which of the two values U ₁ or U _{2 is} greater (or less) with respect to to each other.

This device allows to increase the speed compared to the analogue [1] by 2 ^N times, and compared to the prototype [2] by N times, if the total transient time in the groups of elements 9, 10, 11 does not exceed the clock period of the gating generators.

Sources of information
1. A.S. USSR N 1824521, MKI G 01 D 21/00. Bull. N 24, 1993.

 2. RF patent N 2063613, MKI G 01 D 21/00. Bull. N 19, 1996.

Claims (1)

 A device for autonomous measurements of physical quantities, containing two blocks of measuring transducers, two controlled switches, a comparator, an inverter, a divider, the output of the first block of measuring transducers connected to the first inputs of the first and second switches and a direct input of the comparator, the output of the second block of measuring transducers connected to the second the inputs of the first and second switches and the inverse input of the comparator, the output of which is one of the outputs of the device and is connected directly to the control the input of the first switch, and through the inverter, with the control input of the second switch, the output of which is connected to the input of the divider, characterized in that N output comparators and (N-1) groups of elements are introduced into it, each of which contains an inverter, a switch, and an adder moreover, in each group, the inverter output is connected to the second input of the switch, the output of which is connected to the second input of the adder, the output of which is connected to the first input of the adder of the subsequent group and the inverse input of the corresponding output comparator, output which is connected to the control input of the switch of the subsequent group, the output of the first switch is connected to the direct inputs of N output comparators, the first output of the divider is connected to the first input of the adder of the first group and the inverse input of the first output comparator, the output of which is connected to the control input of the switch of the first group, (N -1) the subsequent outputs of the divider are connected to the inputs of the inverters and the first inputs of the switches of the corresponding groups, the outputs of the N output comparators are information outputs of the devices a.