SU838612A1 - Device for determining dynamical characteristics of transducers - Google Patents

Description

one

The invention relates to electrical measuring equipment and is intended to measure dynamic parameters (aperture time - minimum conversion time, minimum delay time, maximum conversion frequency) and determine various dynamic characteristics based on them, as well as for metrological certification and verification of high-speed analog-digital (ADC) and digital-to-analog (D / A) converters with variable and constant conversion cycle duration regardless of how the control is organized. detection starting converters.

Devices are known for measuring dynamic parameters (rise time, transient response time) of an ADC using standard-shaped test signals containing a DAC (to form an input sample ADC signal), a digital delay line, a clock unit, a clock signal generator, a key element, and a processing unit one,

The disadvantages of these devices are the difficulty in accurately (hundredths of a percent) of determining the response of the ADC to

test signal, especially significant in the conditions of instability of the latter.

It is also known a device for determining the dynamic characteristics of converters, comprising a digital-analog converter connected via an analog-digital converter to the first input of the processing unit, a clock generator associated with a controlled frequency divider and an output terminal of the device, in this device the maximum frequency of the ADC conversion is determined in the process of changing the frequency of the clock signal generator 2 ..

The disadvantage of the device is narrow functionality.

The purpose of the invention is the expansion

0 device functionality.

The goal is achieved by the fact that a device for determining the dynamic characteristics of converters, containing a digital analog converter, connected through an analog-digital converter to the first input of the processing unit, is a generator of clock signals associated with

0 controlled frequency divider, and the output terminal of the device, equipped with two counters: a sawtooth generator, a comparator, a stepwise varying tread generator, a delay element, a five OR element, two AND elements, a single vibrator, six triggers, and a key, the first the input of which is connected with the output of the controlled frequency divider, the output with the first input of the first trigger, and the second input with one output of the processing unit, the other output of which through the first element OR connected in series, the first count The generator of stepwise varying voltage is connected to the first input of the comparator, the output of which is connected to the input of the first counter and the input of the analog-digital converter, the output of the first trigger is connected to the third input of the key, the input of the delay element and the first inputs of the second, third and fourth elements OR, the output of the first counter through the second counter is connected to the second 4 input of the processing unit and to the first input of the second trigger, the first output of which is connected to the first inputs of the third and fourth triggers, The second output of the second trigger is connected to the first | W of the first and sixth triggers, the second input of the first trigger is connected with the second and third input and the third trigger, the second inputs of the fourth, fifth and sixth triggers, the second input of the second trigger, the first input of the first OR element, the first input of the second counter and the output of the one-shot, the input of which is connected to the output of the fifth element OR, the first input of which is connected to the third output of the processing unit, the second input of the fifth element OR is connected to the output of the flip-flop and the output terminal of the device; The holder is connected via a sawtooth generator to the second input {input of the comparator, the output of the third trigger is connected to the third input of the fifth trigger, the first input of one AND element and the second input of the second OR element, the output of the fifth trigger is connected to the second entrance of the third element. This OR is also connected to the first input of another AND element connected with the output of the fourth OR element, the input of which is connected to the fourth trigger output and the third input of the sixth trigger, and the other AND outputs are connected to the corresponding inputs of a digital-to-analog converter,

The drawing shows a diagram of the proposed device.

The device contains processing unit 1, analog-to-digital converter 2 with measurement input 3, start input 4, code output 5 and output of the conversion end signal b, generator 7 of clock signals, digital-to-analog converter 8, controlled divider 9 of the signal frequency, key 10, element 11 delays, triggers 12-17, elements 18-22, OR elements 23-24, synchronization inputs 25 and inputs 26. reset trigger generator 27 sawtooth voltage comparator 28, alternating speed generator 29, one-shot 30, first 31 and second 32 counters, output terminal 33 devices.

The device automatically measures the aperture time of the A / D converter, determines the dependence of this time on the level of the input convertible voltage of the A / D converter, and thus makes it possible to determine other derivatives derived from the aforementioned dynamic characteristics of the A / D converter. For this, a set of steps (levels) of the sample input convertible voltage of the ADC is formed in the device. The duration of the step of each level is reduced from the maximum to the minimum, roughly and then smoothly until the appearance of the dynamic error of the ADC. This determines the aperture time of the A / D converter for each input signal level and the corresponding dynamic error of the A / D converter, in particular, is minimal.

The device works as follows (consider the control mode characteristics of the ADC).

In the initial state, the key 10 is closed, the output signals of the flip-flops 1315 are zero and thus the elements 23 and 24 are blocked and, therefore, the transmission of signals to the inputs of the reference DAC is excluded, starting from the input of the second bit. Both counters 31 and 32 are in the zero state. The DAC 8, according to the signals of the trigger 12, controlled by the signals of the generator 7, generates successive groups of square voltage signals of different levels, as the triggers 13-15 switch, the duration of which is regulated by changing the conversion factor of the controlled divider 9 according to the commands of the processing unit 1. Thus, the period of the clock signal following its extension by the divider 9 and the trigger 12 determines the duration of the set level of the output voltage of the DAC 8. In the initial state, the divider recalculation factor is set so that the period of the clock signal at the output of the divider 9 is, for example , is known to be greater than the conversion time at which the dynamic error of the A / D converter 2 is zero. The output signals of the trigger 12 with the start of operation of the device arrive at the input of the DAC 8 only one of the elements 18-20, directly connected to the input of the first bit. The sequence of these signals at the output of the D / A converter 8 produces the exemplary voltage of the square forka of the first smallest level equal to the quantum. The inputs of all other bits of the D / A converter 8 are blocked by zero signals of the flip-flops 13–15 applied to the inputs of all the corresponding elements 23 and 24 along the input circuits of these bits through the corresponding elements 18–20. The signal of block 1 opens the key 10, the first clock signal generated at the output of the controlled divider 9 switches the trigger 1 with a constant time trigger in the element 11 by the trigger signal 12 for the generator 27 of sawtooth voltage. With the appearance of the second signal, trigger 12 returns to its initial state, locking key 10 with its output signal. Generator 27, generator 29 and comparator 28 form a block of adjustable time delay of trigger output signal 12. Delay control is performed by varying the output voltage the wives of the general. torus 29. The delayed signal from the output of the comparator 28 is transmitted to the circuit for starting the A / D converters 2 and serially connected counters 31 and 32. The duration of the output signal of the trigger 12 determines the duration of the existence of the set DAC level 8, and the difference between this duration and the delay time of the ADC start 2 relative to the switching time of trigger 12 determines the duration of the signal level at the measuring input 3 of the ADC 2 during which coding of this level is allowed. When the output signal of the comparator 28 is zero delayed, the ADC 2 starts with a constant time delay relative to the start of switching of the trigger 12 and turning on the output voltage stage of the DAC 8, thereby providing the start of the analog-to-digital conversion after the transients of the DAC 8 complete. If the transducer of the D / A module 8 is large, then this allows us to exclude measurement errors due to the initial instability of the level of the sample voltage when it is set. The delay time is regulated within the limits of the duration of the trigger signal 12. In the initial state, this time is set to the maximum, which is ensured by setting the maximum output voltage level of the digital oscillator 29. The measurements start with the maximum duration of the set DAC level 8, t . at the maximum divider ratio of 9. If at the set voltage level of the DAC 8 and the specified duration of existence of this level, the dynamic conversion error is zero, then unit 1 generates a signal to change the conversion factor of the controlled divider 9, and thereby decreases the duration of the coded level DAC 8. The duration of the level changes roughly discretely by the value of the period of clock pulses. At the same time, with each change in the conversion factor of the controlled divider 9 by the signal of block 1 transmitted via element 21, the counter 31 is reset to the zero state. If the dynamic coding error of this level, as its duration decreases, turns out to be different from zero, block 1 stops generating a signal to change the conversion factor of the controlled divider 9. After this, the cycle of measuring the dynamic error starts for a series of durations of the set signal level at the measuring input of the A / D converter 2, limited by shifting start-up points of the A / D converter 2 and the end points (of an identically zero value) of the DAC signal 8. Measurements are conducted in the accumulated no. Reducing the delay of the DAC trigger 8 is performed by the signals of the counter 31. With each output signal of the counter 31, the level of the output voltage of the generator 29 decreases by one step, therefore; which reduces the delayed signal at the output of the comparator 28 relative to the beginning of the DAC 8. setting. Meanwhile, the NbiM increases the duration of the signal on the measuring input of the DAC 2 after its start, during which the signal is encoded. The recalculation coefficient of counter 31 determines the number of coding cycles in the cumulative mode. The counter 32 determines the number of different durations for which, at the set level of the D / A converter, it is necessary to measure the dynamic weights. Thus, counters 31 and 32 determine the relationship between the dynamic error and the corresponding duration of the measured signal at a constant level. In accordance with the signal of the sensor 31, the processing unit calculates the average value of the dynamic error of encoding this level at its corresponding duration mz and;.; Sde ADC 2, the time period existed, the voltage during which the voltage was with It and to p about Ip emga about with g b. due to the finite transient time of the A / D converter 2 and equal to ej.fi. It is defined as the difference between the time period of the clock signals (taking into account the division factor of the controlled divider 9 and the grigger 12) and the cyNn-th constant time delay delays of the signal at comparator 28, which triggers ADC 2. After calculating the average value of the regener for this current delay in starting the VDP 2, block 1 generates the next key control signal 10. After all the PDF estimates have been received Given a signal level of DAN 8, the counter 32 forks a switching signal of the level of the CPU 8, a coh; an ori is simultaneously transmitted to block 1,

The output signals of the counter 32 switches the trigger 17 which, in turn, sequentially switches the triggers 13-15 from the zero position to the single position.

: D-flip-flops 13-15 form the distributor of output signals of counter 32. In the initial state, the D inputs of these triggers (except for the first one in the input circuit of the D / A bit of the DAC 8) go to zero s, lt of currents, and all the Triggers are applied by a single signal of the single-brother 30 - With the appearance of the first output signal of the counter 32 and switching of the trigger. 17 switches - with the first of the DTpvirrepOB - 13 in the circuit

However, the next B-trigger 14K switches to it, although a single signal appears at its P-input, Tai-r as the synchronization input of this trigger is applied zero zero-shaft from the second output of the trigger i /. Thus, all other D-triggers with the appearance of the first high signal of counter 32 remain in their original position.,

From switching the first of 0-TKK: shooters 13 to the input of the first bit, the CE-D / A transmitter 8, via the corresponding e-2 ..1ent. 18–20, is constantly applied, (the single signal of this ipHr / eps and output of the DAC 8 setting a constant first-level voltage equal to a quantum, by switching the first D flip-flop 13, its single signal simultaneously arrives at element 23 in the second-bit circuit of the DAC 8 and, in addition, the input circuit of this bit is prepared : it is used to transmit signals of the counting trigger 12. According to the signals of the trigger 12 at the output of the D / A converter, 8 forms (Uyruk) are Square signals varying also

on the ve ; .ji :: y quantum, but now from the mouth; :: fixed constant level, E cyujMapt-ibin level of the output signal .p; (it achieves a maximum of two quanta.

Further, the operation of the device continues similarly.

Assume that the ADC 2 is controlled over the entire set of quantization levels. In the TS-1 case, the DAC 8 should output all the quantization levels of the A / D converters with an interval of one quantum. It is advisable to build such a DAC in the manner described above by the principle of converting a parallel unit code to a voltage, but in the form of several decades of various digits. In this case, the value of the resistors of each decade of the DAC 8 of the higher bit differs from the one of the decade of the resistors by the neighboring decade for a decimal order. Therefore, after completing the formation and coding cycle of the ninth level of the sample signal of this dec. DAC 8, after the corresponding signal of the counter 32 is decelerated, the trigger 16 switches, its first signal starts the first digit of the decades of the neighboring, more senior bit, the one-shot 30 simultaneously turns on; Kotor-ai drops the data of the lek; do in the initial state. Then, the process, with the form 4–1 of the output output stages, reset to the initial state by the decade of the CPD 8, is repeated, nsz already from the village, 11Only d) .j: iеm1: ЗХ poBHe-J most significant bits: not;: -: / le ka.py ,, and then the rest of the pains of the sun deca.c,

Controller / Tc1 .: govnH paSoGa-at impulses continuously, its frequency having chosen the rate from the maximum time for conversion to a certificate; -v: x iTsP 2, t, e, is rather high. But every pseudo ::; I launch the A / D converter 2 and define the level, for example, the marriage of the form C /: G, 8, prog

only POS le TS1G, O I-Ksp-.g comes down in block

1. Transferred the result of the npepbmaioFiiero cycle of the PE conversion, where ok is compared with the true value of the -tocss level, or the average error is calculated, So ity Iy use: start-stop asynchronous re2 :: g1m operation allows; g-ee unit 1 speed not .; the frequency of the clock; - and l; Remg; no conversion of the ADC 2

Claims (1)

; : .. ;;.: .... ij; j; jr; eacheny levels po1.r. . Occasionally, the auj-n-i pgrc. p. 2 p static mode storage codes of the block of av-p memory blocks with ifCvna.-n-f corresponding to the levels, nojj; use.t; ix when working in dknamichesk ;;. l re;:; ime, le after.raugh eis- :; dynamic nost; - all over :: m; -.-; e ADC 2 b.klok 3 elzment 22; per; - | cuts off one-vibration and all devices resetting the initial state. The present invention makes it possible to measure the delay time of many other elements of pulsed and digital equipment and, in general, receivers of electrical signals by shifting the triggering moment of the ADC relative to the moment of switching on the test element until the ADC detects the output signal of the test element. Thus, the device has wide functionality. It can be used to measure dynamic parameters and determine various dynamic characteristics on their basis, as well as for metrological certification and calibration of A11, P (including comparators), DAC and a number of other elements of pulsed and digital equipment, various receivers of electrical signals and The invention claims A device for determining the dynamic characteristics of transducers containing a digital-to-analog converter connected via an analog-to-digital converter to the first input of a block processing, a clock signal generator associated with a controlled frequency divider, and an output terminal of the device, characterized in that, in order to expand the functionality, the device is equipped with two counters, a sawtooth generator, a comparator, a generator stepwise. variable voltage, delay element, five OR elements, two AND elements, one-shot, six triggers and a key, the first input of which is connected to the output of a controlled frequency divider, the output to the first input of the first trigger, the second input to one the output of the processing unit, the other output of which is connected through the first OR element connected in series, the first counter and the generator of stepwise varying voltage is connected to the first input of the comparator, the output of which is connected to the first counter of the first counter and the analog-to input the first converter, the output of the first trigger is connected with the third key input, the input of the delay element and the first inputs of the second, third and fourth OR elements, and the output of the first counter through the second counter is connected to the second input of the processing unit and to the first input of the second trigger, the first output of which connected to the first inputs of the third and fourth flip-flops, the second output of the second flip-flop is connected to the first inputs of the fifth and sixth flip-flops, the second input of the first flip-flop is connected to the second and third inputs of the third m igger, the second inputs of the fourth, fifth and sixth triggers, the second input of the second trigger, the first input of the first OR element, the first input of the second counter and the output of a single vibrator whose input is connected to the output of the fifth OR element, the first input of which is connected to the third output of the processing unit , the second input of the fifth element OR is connected with the output of the sixth trigger and with the output terminal of the device, while the output of the delay element through the saw-tooth voltage generator is connected to the second input of the comparator, the output of the third tr the second is connected with the third input of the fifth trigger, with the first input of one AND element and the second input of the second OR element, the output of the fifth trigger is connected with the third input of the fourth trigger, with the second input of the third OR element and with the first input of another AND element connected input with the output of the fourth element OR, the input of which is connected to the output of the fourth trigger and the third input of the sixth trigger, while the outputs of the second element OR, as well as one and the other elements AND are connected to the corresponding inputs of the digital-analogue azovatel. Sources of information taken into account during the examination 1. Khlistunov V.N. . Basics of digital electrical engineering, M.-L., Energie, 1966, p. 32-40. 2, Bearded V.I. and others. Issues of building automated equipment for studying the dynamic characteristics of high-speed elements of IIS. Proceedings of the Institute of Physical-Technical Radio Engineering Measurements, 1975, No. 25 (55), p. 39-42, fig. 3