JP2757600B2 - Time A / D conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time A / D conversion circuit for converting a minute time into a numerical value such as a phase difference between two pulse signals having an arbitrary phase relationship. And this time A
The / D conversion circuit is, for example, an application of a measurement device that performs accurate measurement of a physical quantity such as pressure from an accurate measurement of a phase difference between two pulses, and a laser radar that measures a distance from a reflected wave of a laser beam to an object. It is suitable for use in equipment.

[0002]

BACKGROUND ART For example, two pulses P _A, when it is desired to detect a phase difference between the P _B, by encoding a plurality of bits of digital signals the phase difference between the pulses, two pulses P _A and P _B Can be detected in both positive and negative directions (phase difference). According to this method, by increasing the number of bits of the digital signal, it is possible to expand the detection range of the phase shift without lowering the detection accuracy.

However, the circuit scale is increased due to the increase in the number of bits.
It will expand significantly. Also, detection without changing the circuit scale
If you try to increase the range, the detection accuracy will decrease.
U. Therefore, the present inventors have proposed to increase the circuit scale and the detection accuracy.
That can expand the detection range without lowering
To form a ring of multiple delay elements (gate delays)
One pulse P connected and input at an arbitrary timing
_ALap and count the number of laps.
Another pulse P input with a desired phase difference _BInput field
Pulse P corresponding to imming_AThe orbital position of the
Two pulses P depending on the specific position and count number_A, P_B
Application for pulse phase difference encoding circuit to detect phase difference
It has been proposed in Japanese Unexamined Patent Publication No. Hei.

According to this method, since the final stage of the gate delay is fed back and the gate delay is used many times, the detection range can be expanded without increasing the circuit scale. .

Further, since the detection accuracy (time resolution) of this circuit is determined only by the delay time of one stage of the gate delay, even if the detection range is expanded, the accuracy does not decrease, and for example, the resolution of 1 ns or less. Can be realized.

[0006]

However, as a result of repeated studies by the present inventors, according to the present invention, a high resolution of 1 ns level can be realized with only a delay time of one stage of gate delay. However, it became clear that the gate delay time fluctuated due to fluctuations in temperature and power supply voltage. That is, the resolution slightly fluctuates due to fluctuations in temperature and power supply voltage.

The present invention has been made in view of this problem, and an object thereof is to stably digitize a minute time such as a pulse phase difference with high speed and high accuracy even if the detection accuracy (resolution) fluctuates. A time A / D conversion circuit is provided.

[0008]

SUMMARY OF THE INVENTION The general structure of the present invention for achieving the above object is to use a pulse phase difference encoding means (M1, M2) using a delay element proposed in Japanese Patent Application No. 2-15865. to correct for variations in the gate delay time due to variations in temperature and supply voltage, temperature and unaffected by fluctuations in the power supply voltage stable reference pulse P _C and the measurement signal to be pulse P
It is characterized in that a relative comparison (ratio comparison) of the time _B is performed. Here, the reference pulse P _C may use oscillation pulses from the crystal oscillator as an example.

The basic circuit configuration of the present invention shown in FIG.
Three signal pulses P input at the timing shown in FIG.
_A, P _B, will be described with reference to P _C. The first pulse phase difference encoding means M1 the input pulse P _A, the time difference T of the P _B
And it outputs a digital value D _AB corresponding to _AB, the second pulse phase difference encoding means M2 outputs a digital value D _AC corresponding to likewise input pulse P _A, the time difference T _AC of P _C. Here, in order to accurately measure the time difference T _AB between P _A and P _B ,
It is necessary to accurately correct the delay time of one stage of the gate delay of the pulse phase difference encoding means. Therefore, the calculation means M3 performs the following correction calculation. Here, the pulse P _C has been generated by stable oscillates with e.g. a crystal oscillator clock, the time difference T _AC of the pulse P _A and P _C may be regarded as always accurate.

The delay time _TG per gate delay in the second pulse phase difference encoding means M2 is

[0011]

## EQU1 ## T _G = T _AC / D _AC The time difference T _AB between the pulses P _A and P _B , which is the time to be measured, is calculated using the same delay time T _G because the first pulse phase difference encoding means M1 is the same as the above-described M1. Can be represented as

[0012]

## EQU2 ## T _AB = D _AB / T _G.

[0013]

T _AB = (D _AB / D _AC ) · T _AC , and the calculating means M 3 calculates M 1, M 2 based on Equation 3.
By comparing (dividing) the digital output from each, it is possible to detect T _AB with, for example, the accuracy of a crystal oscillator.

[0014] That is, in the timing chart shown in FIG. 2, so as to capture the input timing of the signal pulses P _B to be inputted with a phase difference with respect to pulse P _A as a relative ratio to the input timing of the reference pulse P _C, For example, when the time difference T _AC between the pulses P _A and P _{C is} fixed at 1000 ns as a reference time, the input timing of the pulse P _B is 500 ns after P _A (P _B1
Input) is detected as a 50% pulse P _C, also 35% for 350 ns (P _B2 input)
Will be detected as

Next, the fact that the delay time per one stage of the gate delay can be corrected when the delay time fluctuates due to a change in temperature or power supply voltage will be described using specific numerical values.

If there is no fluctuation, assuming that the delay time _TG per one stage of the gate delay is 1 ns, when T _AC = 1000 ns, the digital output D _{AC of} the second pulse phase difference encoding means M2 is obtained. Is equivalent to 1000 from Equation 1. In this case, if the digital output D _AB of the first pulse phase difference encoding means M1 due to the input of the pulse P _B is equivalent to 500, T _AB to be measured (pulses P _A , P (Time difference of _B ) is
Using,

[0017]

## EQU4 ## It is determined that T _AB = (500/1000) × 1000 ns = 500 ns. Here, assuming that the input timings of the pulses P _A , P _B , and P _C are invariable and the delay time _TG per one stage of the gate delay fluctuates and T _G ′ = 1.25 ns, the digital output D _AC two pulse phase difference encoding means M2 becomes equivalent to 800. On the other hand, the digital output D _AB of the first pulse phase difference encoding means M1 becomes equivalent to 400. Therefore, the pulse time difference T _AB to be measured is given by using _Equation 3.

[0018]

T _AB = (400/800) × 1000 ns = 500 ns, and it can be seen from Expressions 4 and 5 that even if the delay time of the delay element fluctuates, accurate detection can always be performed by correction.

As described above, according to the time A / D conversion circuit of the present invention, even if the detection accuracy (time resolution) fluctuates, the minute time such as the pulse phase difference is always digitized with high speed and high accuracy. be able to.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on an embodiment shown in the drawings. FIG. 3 shows a block circuit configuration which is one embodiment of the time A / D conversion circuit 100 when the present invention is realized in the optical round-trip time measurement of a laser radar. In FIG. 3, a time A / D conversion circuit 100 inputs an input pulse P _A rising from an input terminal 101 in response to a laser beam emission time, and rises from an input terminal 102 in response to a laser beam reception time. to enter the input pulse P _B. Further, a built-in crystal oscillator 103 is provided.

Hereinafter, referring to the time chart of FIG.
Next, the configuration of the present embodiment will be described. Crystal oscillator 103 is a signal
As shown in INCKC, stable oscillation at a constant frequency
Is going. Here, from the input terminal 101, the laser oscillation
Corresponding signal pulse P _AIs input, the control circuit 10
4 is the signal pulse P_ARST signal corresponding to counter 10
5 The counter 105_APulse rise
Reference pulse P that rises after a certain period of time_C
And the timing of the occurrence of the RST signal
Start counting the number of pulses of the INCKC signal according to the fall
It is set by counting only predetermined pulses.
It should be noted that not the oscillation pulse of the quartz oscillator 103 but, for example,
External stable clock signal EXCK like icon clock
The same applies when C is input from the external clock input terminal 107.
Reference pulse P_CCan occur.

Here, the pulse encoding circuits 108a and 108
b has, for example, the circuit configuration shown in FIG.
Luth P_APulse P input with a delay_B(I want
Is P _C) Is encoded into a digital value D_AB(Ah
Or D_AC).

Outline of pulse phase difference encoding circuit shown in FIG.
To explain the configuration, this circuit mainly consists of a large number of signal delay circuits.
Ring delay with path (hereinafter also referred to as gate delay)
Pulse generation circuit 1, counter 2, pulse selector
3, consisting of each block of encoder 4
Then, one of the input pulses P_AIs given,
From the middle of the delay pulse generating circuit 1, the pulse P_A
Delay time is determined by the number of gate delay stages
Full delay pulses are output and the pulse select
Input to the operator 3. On the other hand, in pulse selector 3,
Pulse P from terminal 8 _AAnother pulse P later_B(is there
Iha P_C) Is input and this pulse P_B(Or
P_C) Is input, the pulse P_AOf the stage that has reached
Only the input from the switching delay pulse circuit 1
-3 selects the signal corresponding to the selected input.
Input to the encoder 4. Then, the encoder input
A binary digital signal corresponding to the force is output from the encoder 4.
Output from force 9. Also, a ring delay pulse generation circuit
The final end 5 of the gate delay 1 returns to the OR circuit 1a.
So that the gate delay is ring-shaped
Connected, so the delay time for all gate delays
Accordingly, the repetition pulse P_AIs the ring delay pulse generation time
Return to the left end of the road 1, counter 2
Is the pulse P_AThe number of laps the gate delay
Output from output 10 as the above-mentioned bit of output 9 of
Then, these outputs 9 and 10 make the pulse P_A, P_B(Ah
Or P_C) Is the digital value D_AB(Or
D_AC). Note that in FIG. 5, NAND input
By setting 7 to 0, the ring delay pulse generation circuit 1
Is reset.

That is, in FIG. 3, when the pulse P _B indicating the timing of receiving the reflected laser beam is input from the input terminal 102 later than the oscillation (input timing of P _A ), the pulse phase difference encoding circuit 108a Converts the input time difference T _AB into a digital value according to the resolution of the gate delay as described above, and outputs it as a digital value D _AB . Here, the output timing of this batch of A / D change operations are those period until input of the next input pulse P _B is set.

Further, also in the other pulse phase difference encoding circuit 108b, and inputs the reference pulse P _C which rises at the timing described above, the gate delay of the input time difference T _AC from the P _A input to P _C input digital conversion by the resolution by, and outputs a digital value D _AC. Here, 108a and 108b have the same configuration,
They are formed on the same chip, and the delay time due to the gate delay fluctuates similarly in response to fluctuations in temperature and power supply voltage.

The circuit 108a, 108b sends the digital output D _AB, a D _AC to the arithmetic circuit 109. Arithmetic circuit 1
In 09, the time difference T _AB corresponding to to the reception from the oscillation of the laser, as a relative ratio to output D _AC sent from the circuit 108b, the exact value which is set based on the pulse signal always stably by a crystal oscillator 103 Based on the calculation processing shown in the above Equation 3, so as to correct by T _AC ,
Circuit 108a, the digital output value D _AB from 108b respectively, compared D _AC and (division), and outputs the D _O, which corresponds to a stable T _AB. D _O indicates the round trip time of the laser beam and corresponds to the measured distance.

Here, as described above, the circuits 108a, 1
Since the delay time due to the gate delay 08b fluctuates similarly, even if the delay time (that is, the time resolution) fluctuates, a stable output value D _O is always obtained by the calculation by the calculation circuit 109. That is, even if the time resolution fluctuates from 1 ns to 1.25 ns, for example, when measuring 500 ns, the measurement accuracy is 500 ns.
Only from s ± 0.5 ns to 500 ns ± 0.625 ns, stable measurement can always be realized.

As described above, in the present embodiment, the short time of laser reciprocation is digitized at high speed and high accuracy with the time resolution that can be obtained per one stage of the gate delay. The resolution can also be reduced. Further, the accuracy can be corrected by digital calculation based on the stability of the crystal oscillator, and adjustment for correction is not required. Furthermore, even if the detection accuracy decreases due to the increase in the gate delay time due to the high temperature, as long as it is within the allowable range,
Normal operation is possible even at a high temperature (200 ° C. or higher) at which a digital circuit operates, and the operating temperature range of a conventional analog circuit can be further exceeded.

The time A / D conversion circuit 100 used in the above-described embodiment can be applied to not only a laser radar but also other sensors as appropriate. FIG. 6 shows an example in which the present invention is applied to an acceleration sensor.

In FIG. 6, reference numeral 110 denotes an intelligent sensor in which a sensing unit and a circuit unit are formed on the same substrate so as to detect acceleration and output a change in the acceleration as a digital value. This intelligent sensor can be formed, for example, by a manufacturing method proposed in Japanese Patent Application Laid-Open No. 3-49267. Also, 12
Numeral 0 denotes a thin-walled beam that generates distortion when the weight 130 is displaced under acceleration. The beam 120 is formed with a piezoresistance effect element 140 whose resistance value changes according to the distortion.

On the circuit side, 150 is an oscillator,
The oscillating frequency of the piezoresistive element 140 changes according to the resistance change. The oscillator 150 further has a waveform shaping circuit, and the piezoresistive element 14
A pulse signal CKG having a frequency equal to the oscillation frequency determined by the resistance change of 0 is output. A known counter 160 calculates a pulse signal CKG output from the oscillator 150 and outputs count signals C0 to C3. The decoder 170 outputs a reset signal RST to the counter 160 when the count value of the counter 160 reaches a predetermined value (for example, 9). Also, the decoder 170
Outputs a pulse signal P _A shown in FIG. 6B when a preset count value, for example, an initial value is 0, and outputs a pulse signal P _B when the count value becomes 9. .

Here, the piezoresistive effect element 140
Is the one whose resistance changes when it receives displacement (strain)
And the oscillator 150 responds to the change in resistance value from small to large.
Since the oscillation frequency changes from high to low,
As shown in FIG. 6B, a pulse signal from the oscillator 150
Pulse signal P generated by counting CKG 10_BIs pa
Loose signal P_AThe rising position is the piezo resistance
The resistance change of the effect element 140, i.e., the load applied to the weight 130
It changes according to the magnitude of the speed change. Follow
The change in acceleration acting on the weight 130 is represented by a pulse signal.
P_A, P_BTime difference T _ABCan be detected as a change in
Wear. Note that this time difference T_ABIs the pulse signal P_BOccurs
Change of oscillation frequency included in each pulse signal until
Minutes are accumulated, so detection of acceleration changes
The sensitivity is improved, and the oscillation frequency
A change can be detected.

Then, the above-mentioned time A / D conversion circuit 100
Is for inputting pulse signals P _A and P _B , digitizing a time difference T _AB representing an acceleration change, and outputting it as a digital signal D _O.

Here, the time A / D conversion circuit 100 receives the stable clock signal CKC as well as the pulse signals P _A and P _B as described above, and thereby corrects the fluctuation of its own time resolution. Therefore, the sensor of this structure can always output the output value D _O with stable accuracy irrespective of temperature and power supply voltage fluctuation.

In the application example shown in FIG. 6, an acceleration sensor is described in which a change in resistance is given as a time difference between two pulse signals using a piezoresistive element. The present invention can also be applied to an acceleration sensor configured to be captured. Moreover,
By appropriately changing the sensing unit, the present invention can be applied to, for example, a magnetic sensor or the like.

Next, the time A / D according to another embodiment of the present invention will be described.
FIG. 7 shows a schematic block circuit configuration of the conversion circuit. In the above embodiment, two pulse phase difference encoding circuits 108a and 108b are used as shown in FIG. 3, but in the present embodiment, one pulse phase difference encoding circuit 108 Is realized. In this embodiment, the pulse signal P inputted to the pulse phase difference encoding circuit 108 is constituted so as to constitute one pulse phase difference encoding circuit.
_B and PC are _assigned by time division.

Hereinafter, the circuit operation will be described with reference to the time chart of FIG. Pulse signal P _A having a pulse waveform shown in FIG. 8 is input to the pulse phase difference encoding circuit 108. Further, in synchronism with the falling of the pulse signal P _A, the select signal SEL its state changes, another pulse signal P _B that is input to the pulse phase difference encoding circuit 108, either P _C whereas Is selected. That is,
In FIG. 8, when the signal SEL is at the H level, the pulse signal P _B input with an arbitrary phase difference to be detected with respect to the pulse signal P _A is selected, and when the signal SEL is at the L level, reference pulse signal P _C that is input with a constantly stable phase difference T _AC to pulsed signals P _A
Is selected. Then, the pulse phase difference encoding circuit 108
Performs the above-mentioned digital conversion corresponding to the time difference T _AB (or T _AC ) between the input pulse signal P _A and pulse signal P _B (or T _C ) with its time resolution, and obtains a digital value D _AB (or D _AC ) Output as The arithmetic circuit 109 performs a predetermined arithmetic operation shown in Expression 3 based on the digital values D _AB and D _AC input in a time-division manner.
An error included in the digital value D _AB due to a change in the time resolution of the pulse phase difference encoding circuit 108 is corrected by a digital value D _AC based on the time difference T _AC whose accuracy can be guaranteed, and the corrected time difference is used. the digital value corresponding to T _AB output as D _O.

In the configuration of this embodiment, the same effects as those of the above-described embodiment can be obtained, and the circuit area can be reduced. Therefore, the configuration is suitable for use in various sensor circuits.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic basic configuration of the present invention.

FIG. 2 is a time chart illustrating the operation of the present invention.

FIG. 3 is a block diagram of a laser radar to which an embodiment of the present invention is applied.

FIG. 4 is a time chart for explaining the operation of one embodiment.

FIG. 5 is a block diagram illustrating a circuit configuration example of a pulse phase difference encoding circuit.

FIG. 6A is a block diagram in which one embodiment is applied to an acceleration sensor, and FIG. 6B is a time chart illustrating a detection principle.

FIG. 7 is a schematic block diagram showing another embodiment of the present invention.

FIG. 8 is a time chart for explaining the operation of another embodiment.

[Explanation of symbols]

M1 first pulse phase difference encoding means M2 second pulse phase difference encoding means M3 calculating means 100 hours A / D converter circuit 101 P _A input terminal 102 P _B input terminal 103 crystal oscillator 106 D _O output 108 , 108a, 108b Pulse phase difference encoding circuit 109 Operation circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-220814 (JP, A) JP-A-53-15053 (JP, A) JP-A-55-40443 (JP, A) JP-A-60-1985 164257 (JP, A) JP-A-1-267491 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H03M 1/64 G04F 10/04 H03M 1/06 H03K 5/26 G01R 29/02

Claims (1)

(57) [Claims] 1. A second pulse signal which receives a first pulse signal, passes the first pulse signal through a plurality of delay elements, and delays the first pulse signal by an arbitrary time. And specifying the passing position of the first pulse signal through the plurality of delay elements at the input timing of the second pulse signal, so that the arbitrary time passes through the first pulse signal. First pulse phase difference encoding means for encoding based on the number of delay elements; and inputting the first pulse signal and converting the first pulse signal to the first pulse phase difference encoding means. The plurality of delay elements of the first pulse signal are passed through the plurality of delay elements configured as described above and at the input timing of the reference pulse signal input with a certain time difference with respect to the first pulse signal. And a second pulse phase difference encoding means for encoding the constant time difference based on the number of delay elements through which the first pulse signal has passed, and the first pulse phase difference code. Calculating means for outputting the arbitrary time encoded by the encoding means as a relative ratio to the constant time difference encoded by the second pulse phase difference encoding means. D conversion circuit.