SU754668A1 - Voltage-code converter - Google Patents

Description

The invention relates to a digital electrical measuring technique and can be used when copying an analog voltage to an η-bit digital code.

Known voltage Converter code, operating according to the method of sequential counting ^ 1 ^.

It comprises a comparison device, whose input is connected to the code-voltage converter, and a control unit (in the simplest case, a trigger) The compound via the AND gate to a generator of countable pulses and a counter, which outputs ¹ podklyuche- us to-code converter tension.

The main disadvantage of this converter is a relatively low speed with a large number of counter bits, since the compensating value in each cycle changes by an amount equal to the quantization step, and the number of cycles per conversion cycle (maximum) is 2 ^P '*, where n - number of digits. '

A voltage-code converter is also known, which contains a comparison device connected to a linear decoding converter and a control device, under-)

VOLTAGE-CODE

2

connected to the pulse generator and the counter, the discharges of which are connected to the input of a linear decoding converter and two elements AND in each discharge, one input of which is connected to the output of the first element AND of the previous discharge, the other inputs are connected to the trigger outputs of this counter discharge,

'and the output of the first element And is connected to the inputs of two elements And the next digit, the output of the second element And is connected to the counting input of the trigger of the next discharge account>tick; one of the inputs of two elements And the high-order discharge is connected to the output of the control device, the other inputs to the outputs of the high-level trigger trigger of the G2 counter}. ^one

1 The difference between the operation of this converter and the operation described above lies in the fact that the generator pulses do not arrive at the first (lower) discharge of the meter, but depending on the state of the high-order counter triggers (which corresponds to the input voltage), can be applied to various lower-order triggers

I counter, and as the dialing code

3

754668

four

the larger the code recorded in the counter, the more senior the counting impulse of the generator enters,

However, this increase in speed is not effective enough.

The aim of the invention is to increase the speed of the Converter.

This goal is achieved by the fact that the device containing the comparison unit, the first input of which is connected to the input signal bus, and the second - with the code-voltage converter output, the last inputs are connected to the first outputs of the meter triggers, the control unit whose first input is connected to the bus "start", and the second input - with the output of the comparison block; the first output of the control unit is connected to the generator input, the output of the latter is connected to the first inputs of the And element, the outputs of the latter are connected to the corresponding counting inputs of the trigger trigger ka, additionally introduced by the number of digits, except the senior one, comparators, summing amplifiers and I-NOT elements, with the first inputs of summing amplifiers connected to the code-voltage converter output, the second inputs to the outputs of the constant bias source, and the outputs to the first inputs of the corresponding comparators, the second inputs of which are connected to the input signal bus, the outputs of the comparators are connected to the first inputs of the corresponding AND-NOT elements and to the second inputs of the AND elements, the second inputs of the AND-NOT elements are connected to the second you the trigger moves of the counter of the previous discharge, and the outputs to one of the inputs of the And element of the corresponding and all subsequent digits, the third input of the And element of the first discharge is connected to the second output of the control unit.

The drawing shows a functional diagram of the Converter. It contains a comparison unit 1 connected to a code-voltage converter 2, and a control unit 3 connected to a counting pulse generator 4 and, through element 5, to the input of an η-bit counter 6 with trigger 7, the outputs of which are connected to a code-voltage converter, summing amplifiers 8, one input connected to a code-voltage converter, the second - to a constant bias source 9, and an output through comparators 10, the second input of which is connected to the source of the measured voltage 11, to the inputs of the elements AND-HE 12. of the previous discharge, the second input of the AND-NOT element is connected to the trigger output of the previous discharge counter, and the output to the input of the AND element of the corresponding and all subsequent discharges and the outputs of the AND elements are connected to the next trigger input of the counter discharges.

The conversion of the input measured voltage starts at the start pulse received over the bus 14. This pulse starts the control unit 3 and resets the triggers 7 of the counter 6. At the output of the code-voltage converter 2, a voltage corresponding to the zero code of the converter is set. This voltage goes to the inputs of the summing amplifiers. 8, to the second inputs of which a constant offset is applied in such a way that a voltage is set at the inputs of the amplifiers:

Sh ^{= + Δ} >

where i) ^{x is the} voltage from the ^{output of the PC} and the converter

code-voltage

! = 1,2,3 (η- 1) is the number of the counter discharge,

& - guard interval. The control unit 3 after the end of the transient process starts the generator of counting pulses 4. The voltage from the outputs of the amplifiers 8 is fed to the inputs of the comparators 10, and the measured voltage is fed to the second inputs of the bus 14. The comparators operate in such a way that the output will have a low "inhibiting" potential, and when and _to <and; - high "resolving" potential.

When the input voltage is 8 ^ 11 _ηκΗ + -t ^ +, the _high-order comparator closes the AND 13 element of the previous discharge and opens the AND 13 high-level element at its input, and the other comparators close the AND elements of the previous discharges and through its elements, AND-NOT will open at its inputs the element AND of the higher order, since. when u * - and _P cc ^ ^m + D, the condition –i and _k > for ί = 1,2,3 ·. -n-2 is all the more fulfilled and the first impulse of the generator - 4 passes to the most significant digit of the counter. If 1) ^, <and _pkn + pr + d, .but

> and _pkn + ^ ^t + d, then a _high-order comparator 10 will open the element AND 13 of the previous discharge, and through the element AND-NO 12, the potential of the previous discharge will flow to the element 13 of the higher discharge. All other comparators of 10 lower-order digits will close the elements of AND 13 of the previous digits and, through their elements AND-NO, will open the element of AND 13 (n-1) -th digit, since the condition and _x >

when ΐ = 1, 2.3. · -N-3, and the pulse of the generator of counting pulses 4 will go to the η-1st digit of the counter.

Thus, at each moment of time, the generator 4 pulses pass to the most senior of those: counter discharges, for which

five

754668

6

the condition and * - ^and pkn * ^ / * ^A 1 ^T · ^e · the difference between the input and compensating voltage of the code-voltage converter 2 is greater than the voltage corresponding to the weight of this discharge plus the guard interval a. This process will occur until the condition and _x <and _psn + Ιττ / ΐ "· * Δ ₍ and the comparator 10 low-order will open the element And 5, the generator 4 pulses will start to flow to the low-order counter, and the converter will start working as a normal sequential counting converter. At the moment of equality of the measured and compensating voltages, the main comparison unit 1 outputs a signal to the control unit, which stops the counting pulse generator 4.

The choice of the guard interval is determined by the required speed and requirements for the comparator. The smaller the interval a, the higher the speed, however, this increases the requirements for stability and identity of comparators and summing amplifiers.

The most optimal is the choice of a guard interval equal to half the weight of the corresponding discharge. In this case, the number of counting pulses in one conversion cycle over the entire voltage range becomes equal to the number of counter bits.

Claims (1)

Claim The voltage code converter containing the comparison unit, the first input of which is connected to the input signal bus, and the second input to the code-voltage converter output, the inputs of the latter are connected to the first outputs of the meter triggers, the control unit, the first input of which is connected to the “start” bus, and the second input is connected to the output of the reference unit. The first output of the control unit is connected to the input of the generator, the output of the last is connected to the first inputs of the elements And outputs the latter are connected to the corresponding counting inputs of the meter triggers, characterized in that, in order to increase the speed, the comparators, summing amplifiers, and NAND elements, the first the moves of the summing amplifiers are connected to the code-voltage converter output, the second inputs are connected to the DC bias source outputs, and the outputs are connected to the first inputs of the respective comparators, the second inputs of which are connected to the input signal bus, the outputs of the Comparators are connected to the first inputs of the corresponding AND AND elements to the second inputs of the elements AND the second inputs of the elements AND-NOT are connected to the second outputs of the triggers of the counter of the previous discharge, and the outputs to one of the inputs of the AND element of the corresponding and all subsequent times poisons third input element of first bit is connected to the second output of the control unit.