SU1531216A1 - Probability analog-digital converter - Google Patents

Abstract

The invention relates to digital measuring and computing technology and can be used in instruments for measuring DC and AC parameters. The purpose of the invention is to simplify the device and improve accuracy. The goal is realized through the use of probabilistic analog-to-digital converters containing a pseudo-random number generator, a comparator, pulse counters, as a digital-to-analog converter of a single-bit capacitive digital-to-analog converter on at least three switches made on field-effect transistors and two capacitors of the same capacitance . 1 il.

Description

one

(21) 4375737 / 24-24

(22) 12/07/87

(46) 12/23/89. Bul V 47

(71) Leningrad Scientific and Production Association Electronmash

(72) V.P.Volchok and V.D.Oududim

(53) 681.325 (088.8)

(56) Bilinsky I.Ya. et al. Stochastic digital processing of continuous signals. Riga: Zinatne, 1983, p. 15.

USSR author's certificate K 1229950, cl. H 03 M 1/04, 1984.

(54) PROBABLE ANALOG-DIGITAL CONVERTER

(57) The invention relates to digital

measuring and computing technology and can be used in instruments for measuring DC and AC parameters. The purpose of the invention is to simplify the device and improve accuracy. The goal is realized through the use of probabilistic analog-to-digital converters containing a pseudo-random number generator, a comparator, and pulse counters, as a digital-to-analogue converter of a single-bit capacitive digital-to-analogue converter on at least three keys transduced on two transducers, and two multipliers on two transponders, and two multipliers on two transponders, and two multipliers on two transponders, and two multipliers, and two amplifiers. same capacity. 1 tab. 1 il.

S

The invention relates to digital measuring and computing technology and can be used in instruments for measuring DC and AC parameters.

The purpose of the invention is to simplify the device and improve accuracy.

The drawing shows the functional diagram of the device.

Vertical analog-to-digital converter (ADC) contains 1 clock pulse bus, 2 pseudo-random number generator, digital-analog converter 3, comparator 4, first 5 and second 6 pulse counters, output register 7, first 8 and second 9 elements, NOT elements And 10-12, delay element 13, input bus 14, output bus 15, bus 16

reference voltage and pin 17 of zero potential.

The pseudorandom number generator 2 contains an n-bit shift register 18, a decoder 19, an EXCLUSIVE OR element 20, an output 21 a generator, 2 pseudorandom numbers, an output 22 of a decoder 19.

The digital-to-analog converter 3 (D / A) contains three switches made respectively on the first 23, second 24 and third 25 field effect transistors and the first 26 and second 27 capacitors.

The device works as follows.

From the bus 1 clock pulses to the control (synchronizing) input of the generator 2 pseudo-random numbers

a sequence of square-wave pulses Pd arrives, and a sequence of numbers of length 2 -1 is formed on the shift register 19 containing the p-binary bits. If the information does not match with the n-th and i-ro, where 1 ii n of the outputs of the shift register, the EXCLUSIVE OR 20 element is triggered and the signal 1 arrives at the information input of the shift register 18 and the first output of the pseudo-random number generator simultaneously from the states of the shift register 18 and transmits it to the input of the counter 5

The signals from the first output of the generator 2 pseudo-random numbers through elements 8-11 arrive at the gates of transistors 23 and 24 at times of action F. When logical 1 appears at the gate of transistor 23 (at the gate of transistor 24 at this moment of logic O), the capacitor 26 charges When the voltage of the logical 1 Tc gate of the transistor 24 of the condensate 26 is discharged to the common bus, it becomes equal to the reference voltage EJJ. The resulting voltage on the capacitor 26 is respectively equal to E or O.

After the end of the pulse F, the transistors 23 and 24 are closed, and the trans-iHcTop 25 opens, the capacitance between the capacitors 26 and 27 is determined, and hence the division of the voltages. In case of equal capacitance of capacitors on parallel-connected capacitors, a new banner is installed: e voltage

„Ui“ ЕО-К;.,

and

(one)

new voltage value on capacitors; previous value on

45

a capacitor 26; reference voltage; coefficient taking

the value is 1 or O (in 50 dependencies on the previous state of transistors 23 and 24). cycles of shear re-;

the number is reset

55

Ki „. TO-,

i +

 + “I

where K - is the value of the most significant bit of the register at the time of dividing the voltage on capacitors 26 and 27, K. To - the value of the least significant bit of the shift register at the time of dividing voltage.

Since the shift operation of the binary number in the register is the division of a number code by two, between the output of the D / A converter 3 and the code accumulated in shift register 18 establishes -; - with a one-to-one correspondence. For a sufficiently large n, this correspondence is established independently of the initial voltage on the capacitor 26, since the sequence (2) is a continued fraction.

p v v v ii - i p. about . ip 2 4

j EO K.Chp-g j EC, K (

35 40

45

50 ;

55

and for a sufficiently large n value

Kj

- ,, tends to zero.

The correspondence between the values of a binary pseudo-random sequence of numbers at the output of a generator of 2 pseudorandom numbers and the voltages at the output of a digital-to-analog converter 3 in the proposed device is illustrated with an example for n in 3, ha 2 in the form of a table.

It follows from the table that the voltage value at the 11LP output with an error less than the value of the low-order unit corresponds to the value of the binary code of a pseudo-random number, if its first bit is taken as the high-order bit.

Comparative 4 compares the input signals received on the input bus 14 and the voltage value from output 1 (AP 3, while the output of the comparator appears at the time when the voltage from the DAC 3 exceeds the input signal, through the AND element 12 enters counter 5,

515

and upon resolution from counter 6, is written to the output register, where it is stored until the end of the next conversion cycle.

Therefore, the code value on the output bus 15 is proportional to the value of the input signal. The proportionality coefficient depends on the magnitude of the source of the reference voltage and the number of repeated pseudo-random sequences.

The methodical conversion error is the sum of the previously determined DAC error and the comparison error equal to half the value of the least significant bit unit.

Thus, the proposed device provides the limiting speed of pseudo-random A1SC conversion achievable using parallel DACs, independence of the conversion rate from the pseudo-random number, increasing the bit size and, accordingly, the accuracy of the ADC without increasing the DAC bit size, ease of implementation with the minimum number of precision elements, the possibility of realizing pseudo-constancy ADCs using the integrated semiconductor technology.

Claims (1)

Invention Formula A analog-to-digital converter containing a comparator, the first input of which is an input bus, the second input is connected to the output of a digital-to-analog converter, and the output is connected to the first input of the first And element, the output of which is connected to the counting input of the first pulse counter, the second a pulse counter, a pseudo-random number generator, a second And element, a clock pulse bus, characterized in that, in order to simplify the device and improve accuracy, two NOT elements are introduced into it, the third And element, an element delays and the output register, the pseudo-random number generator is made in the form of an n-bit shift register. -. with 0 5 0 0 five 0 166 decoder and element EXCLUSIVE OR, and digital-to-analog converter is made in the form of three keys on the field-effect transistor, each of the two storage elements on the first and second capacitors of the same capacity, while the gates of the first and second field-effect transistors are connected respectively to the outputs of the second and third elements And, source the first field-effect transistor is connected to the drain of the second field-effect transistor, with the first output of the first capacitor and the source of the third field-effect transistor, the source of the second field transistor the source is connected to the second output of the first capacitor and to the first output of the second capacitor and is a zero potential bus, the drain of the first field-effect transistor is the reference voltage source bus, the drain of the third field-effect transistor is connected to the second output of the second capacitor, and is the output of a digital-analog converter, and its gate is with the output of the first element NOT and the second input of the first element I, and the control input of the shift register is connected to the clock bus and is combined with the input of the first element NO and the first inputs of the second and third elements H, the information input of the shift register is connected to the output of the EXCLUSIVE HJH element and combined with the second input of the second element AND and through the second element NO with the second input of the third element AND the outputs of the shift register n-bits connected to the corresponding inputs of the decoder, and the outputs of the nth and i-ro (where 1 i С p) bits - with the corresponding inputs of the element CREATE-1CEE OR, the output of the decoder through the second pulse counter is connected to the first input of the output register and Valid delay element whose output is connected to the input of the first installation of the pulse counter, the output of which is connected to the input of output register vtorm, vyho / ol which are output line. 100 110 011 101 010 001 000 four 6 3 5 2 1 О go 4 6 3.75 5.5 2 2.75 1, 375 0.6873 ABOUT ABOUT +0.75 th, 5 0.75 +0.375 +0.6875