RU2777024C2 - Fast-acting parallel adc - Google Patents

Abstract

FIELD: radio electronics.

SUBSTANCE: invention relates to radio electronics; it is intended for analog-to-digital conversion of analog signals; it can be used in radiolocation and communication systems. A parallel ADC contains a high-speed key, a counter made with a count factor of four and a decoder, connected in series; the first, the second, the third, the fourth ADC, wherein decoder outputs are connected to clock inputs of ADC, while an input signal is simultaneously supplied to inputs of all ADC.

EFFECT: increase in performance of analog signal conversion.

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Description

The invention relates to radio electronics, is intended for analog-to-digital conversion of analog signals, and can be used in radar and communication systems.

Known methods of analog-to-digital conversion: the method of successive approximation, the method of bit-by-bit balancing, the method of delta-sigma ADC, the method of simultaneous reading. Closest to the proposed (prototype) is a method of simultaneous reading, which consists in a push-pull analog-to-digital conversion of the input signal, while on the first cycle the input signal is converted into a 2-bit signal, which selects the appropriate ADC with a bit width n for the second conversion cycle ; in this case, all ADCs must be built on the basis of the simultaneous reading method; the total bit depth of the ADC will be N=4n+2, while the conversion time will be equal to 2 clock intervals; the analog-to-digital converter device consists of one ADC with a capacity of 2 bits, a decoder and 4 parallel ADCs with a capacity of n; on the first cycle, the first ADC determines the interval of the input signal amplitudes, and the decoder determines the switching sequence of the remaining 4 ADCs on the second conversion cycle, depending on the amplitude of the input signal. [one].

A positive technical result is an increase in the speed of analog-to-digital conversion.

The technical result is achieved due to the fact that the principle of operation of a high-speed parallel ADC is proposed, characterized in that the ADC contains a high-speed key, a counter and a decoder connected in series; the first, second, third, fourth ADC 3, 4, 5, 6, and the decoder outputs are connected to the clock inputs of the ADC, while the inputs are the inputs of all ADCs.

The principle of operation of a high-speed parallel ADC is that the signal is simultaneously applied to 4 inputs of four parallel ADCs. The clock signal is applied to the key, counter and decoder, the outputs of which control the clock signals of the ADC. At the same time, the sampling frequency of the new ADC structure is 4 times higher compared to existing ADCs. The performance of the new ADC structure increases by the same factor.

A high-speed parallel ADC contains a high-speed key (see drawing), a counter 1 and a decoder 2 connected in series, the first, second, third, fourth ADCs 3, 4, 5, 6, and the decoder outputs are connected to the clock inputs of the ADC. The inputs are the inputs of all ADCs.

The parallel action ADC works as follows.

The input analog signal is fed simultaneously to all inputs of the ADC 3, 4, 5, 6. The clock signal passes through a high-speed switch and is fed to the clock input of the counter, which has a counting factor of 4. The signal from the output of the counter 1 is fed to the input of the decoder 2, the outputs of which are connected to the clock inputs of all ADCs. Thus, there is a serial analog-to-digital conversion in each of the parallel ADCs. At the same time, the sampling frequency of the new ADC structure is 4 times higher compared to existing ADCs. The performance of the new ADC structure increases by the same factor.

Literature

1. RF patent No. 2696557. IPC H03V 1/00, H03V 4/00. A method of analog-to-digital conversion and a device for its implementation / Ryabov I.V., Ilyin G.I., Lerner I.M. Appl. 11/21/2018. Published 08/02/2019. Bull. No. 25. - 4 s. (prototype).

Claims (1)

A high-speed parallel ADC, characterized in that it contains four parallel ADCs, the inputs of which are the analog input of the ADC and are designed to simultaneously supply an analog signal to them, a high-speed key to apply to it and transfer to the clock input of a counter made with a counting factor of four, a clock signal , a decoder connected to the output of the counter, the outputs of which are connected to the clock inputs of the ADC in such a way that a serial analog-to-digital conversion occurs in each of the parallel ADCs.

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