KR20090034669A - A method and apparatus for converting an analog signal to a digital signal - Google Patents

Abstract

An apparatus and a method for converting an analog signal into a digital signal are provided to reduce the number of preamplifiers and comparators by decreasing a comparison range through the preprocessing. A preprocessor(210) controls a comparison range of a comparator by using a switch. A first comparison unit(230) compares an input voltage and a reference voltage based on the controlled comparison range. An encoding unit(260) encodes a digital code outputted from the first comparison unit. The preprocessor includes a comparator, a flip-flop and a sample holder. The comparator compares the differential input signal. The flip-flop maintains the output of the comparator to the fixed value according to the clock signal. The sample holder outputs the differential input signal having the fixed value.

Description

A method and apparatus for converting an analog signal to a digital signal}

The demand for broadband and ultra-high speed of information is exploding all over the world, and the millimeter wave band (30-300 GHz) suitable for such a demand is being actively researched. The 20-40 GHz band, which is the boundary between the millimeter wave band and the microwave band, is currently being applied to satellite communication technologies such as LMDS in the US and B-WILL in Korea. The next higher frequency band is the 60 GHz band.

The 60 GHz band is not only capable of wideband transmission but also has a large absorption attenuation of radio waves by oxygen, and thus has various applications such as satellite communication, military use, large-capacity short-range communication system, and wireless home wiring. In particular, the 60 GHz band is far away from other UWB (3.1 GHz to 10.2 GHz) and short-range wireless communications such as WPAN (2.4 GHz), so that there is less interference and less restrictions in setting standards.

Wireless communication in the 60 GHz band uses high frequency bands, requiring an analog-to-digital converter (ADC) in the fast giga band. The flash-to-analog analog-to-digital converter used in the present invention is capable of high-speed conversion and is expected to be applied to future 60GHz band communication technology.

The flash structure used in the high-speed analog-to-digital converter has an advantage of easy high-speed operation. However, the higher the resolution, the greater the power consumption. For example, a converter with 4 bits of resolution requires 15 preamps and comparators each, while a converter with 5 bits of resolution requires 31 preamps and comparators, twice that of 4 bits. Seems to increase power consumption close to.

As such, it is necessary to adjust the number of preamplifiers and comparators in order to reduce the power consumption of higher resolution analog to digital converters.

An object of the present invention is to reduce the power consumption and area of the analog-to-digital converter.

Another object of the present invention is to adjust the comparison range of the comparator through a pretreatment process.

Another object of the present invention is to perform a more accurate comparison by performing an additional comparison process in the comparator.

Another object of the present invention is to reduce the number of preamplifiers and comparators by reducing the comparison range of comparators.

The present invention provides an apparatus for converting an analog signal into a digital signal, comprising: a preprocessor adjusting a comparison range of a comparator using a switch, a first comparing unit comparing an input voltage and a reference voltage based on the adjusted comparison range; It provides an analog-to-digital converter comprising an encoding unit for encoding the digital code output from the first comparison unit.

The new preprocessing process reduces the comparability of comparators. By reducing the comparison range, the number of preamplifiers and comparators can be reduced, and the number of preamplifiers and comparators can be reduced, thereby reducing power consumption of the analog-to-digital converter and increasing the degree of integration. In addition, when the input voltage falls within a predetermined range, the comparison process may be performed to perform a more accurate comparison. In addition, by solving the above power consumption and integration problems, it is possible to easily implement a chip for 60GHz wireless communication.

The present invention provides an apparatus for converting an analog signal into a digital signal, the apparatus comprising: a preprocessor adjusting a comparison range of a comparator using a switch; a first comparing unit comparing an input voltage and a reference voltage based on the adjusted comparison range; It provides an analog-to-digital converter comprising an encoding unit for encoding the digital code output from the first comparison unit.

The preprocessor may further include a flip-flop for maintaining a constant value of the comparator and a sample holder for outputting the differential input signal at a constant value according to a comparator and a clock signal comparing the differential input signal. It is characterized by including.

In addition, the present invention is characterized in that the switch is adjusted based on the output value of the flip-flop.

In addition, the present invention is characterized in that the output value of the sample holder to the opposite phase by using the switch.

In addition, the present invention is characterized in that the comparison range is divided into an upper region and a lower region on the basis of the intermediate voltage.

The present invention may further include a second comparator configured to perform an additional comparison process when the input voltage falls within a predetermined range.

The present invention also provides a method of converting an analog signal into a digital signal, the method comprising: adjusting a comparison range of a comparator using a switch, comparing the input voltage with a reference voltage based on the adjusted comparison range, and It provides an analog-to-digital conversion method comprising the step of encoding the output digital code based on the comparison range.

Hereinafter, the configuration and operation of the embodiments of the present invention with reference to the accompanying drawings, the configuration and operation of the present invention described by the drawings will be described as one embodiment, whereby the technical spirit of the present invention And its core composition and operation are not limited.

In addition, the terminology used in the present invention was selected as a general term widely used as possible now, in a specific case will be described using terms arbitrarily selected by the applicant. In such a case, since the meaning is clearly described in the detailed description of the part, it should not be interpreted simply by the name of the term used in the description of the present invention, and it should be understood that the meaning of the term should be understood and interpreted. .

Many of the signals in nature change continuously over time. We need to convert these signals into digital values for computer processing. Devices that perform these functions are called analog-to-digital converters. There are various types of analog-to-digital converters such as a parallel comparator type, a short slope type, a twin slope type, and a sequential approximation type. Among them, a parallel comparator analog-to-digital converter is also called a flash analog-to-digital converter. Since the flash-type analog-to-digital converter is capable of high speed conversion, the flash-type analog-to-digital converter may be used in advanced technologies in various fields in the future. Accordingly, the present invention seeks to provide several embodiments of more efficient analog-to-digital converters.

1 is a block diagram of an analog-to-digital converter as an embodiment to which the present invention is applied.

The analog-to-digital converter includes a sample holder unit 110, a reference voltage generating unit 120, a pre-amplifier unit 130, and a comparator unit. 140 may include an encoding unit 150.

First, the sample holder 120 follows an input value in one phase of a clock so that the comparator 140 easily compares an incoming signal quickly. In the opposite phase, the sample holder 120 uses a constant voltage value. It plays a role. In addition, by maintaining the input value at a constant voltage value, the comparison unit 140 can perform a more clear comparison by reducing the error as much as possible. The reference voltage generator 120 may generate a plurality of reference voltages having different levels through the resistor string. For example, the reference voltage generator 120 may generate a constant reference voltage that can be compared with an input value that enters the comparator 140 through the preamplifier 130.

The preamplifier 130 may provide an amplification effect of the input signal. For example, the comparator 140 may amplify a difference value between the input value and the reference voltage value so that the comparison unit 140 may compare the input value with the reference voltage value more accurately. The comparator 140 compares the difference between the input value amplified by the preamplifier 130 and the reference voltage value and outputs the digital value of 1 and 0. FIG. For example, the output of the comparator 140 outputs a voltage of logic 1 when the input voltage is higher than the reference voltage. In this case, the output of the comparator 140 may be called a thermometer code because the boundary between successive 1s and 0s is clear in an ideal case. For example, a 6-bit resolution analog-to-digital converter will output 63 digital codes (thermometer codes). Finally, the 6-bit digital output can be obtained through the encoding unit 150. As the encoding unit 150, for example, a fat-tree encoder may be used.

The preamplifier 130 and the comparator 140 require a predetermined number of preamplifiers and comparators according to the resolution of the analog-to-digital converter. Minimizing the number of the preamplifier and the comparator may not only reduce power consumption but also facilitate an integrated circuit configuration. Various methods may be used to minimize the number of the preamplifier and the comparator. For example, the lower the range of the voltage to be compared in the comparator 140 can reduce the number of the preamplifier and the comparator. Therefore, as an embodiment of the present invention, look at various embodiments for reducing the comparison range of the comparison unit 140.

2 is a block diagram of an analog-to-digital converter as an embodiment to which the present invention is applied.

The analog-to-digital converter illustrated in FIG. 2 includes a preprocessor 210, a reference voltage generator 220, a first comparator 230, a second comparator 240, a comparator output corrector 250, and an encoding. It may include a portion 260.

The preprocessor 210 receives an analog differential signal of INP (Input Positive) and INN (Input Negative) as an input value, and performs a preprocessing process to lower the comparison range in the comparator. For example, when passing through the preprocessor 210, the comparison range of 1V may be reduced to 0.5V. The principle for lowering the comparison range will be described in detail with reference to FIGS. 3 and 4. As such, as the comparison range is reduced, the first comparator 230 may reduce the number of preamplifiers and the number of comparators. For example, an nbit flash analog-to-digital converter would be 2n ?? One comparator may be required. Thus, for a 6-bit flash analog-to-digital converter, 63 comparators are needed. However, when passing through the preprocessor 210, the number of comparators can be reduced to 33 (excluding the dummy area), which is half of the number of comparators. This will be described in detail with reference to FIG. 3.

When the number of comparators is reduced through the preprocessor 210, the output value of the preprocessor 210 may become unstable around the center voltage CM. Therefore, there may be a need for a method to minimize this phenomenon. For example, instability can be corrected by additionally performing a comparison process within a range around the center voltage CM. That is, a comparison between the first comparator 230 and the overlapping range of the center comparator 230 through an additional comparator (second comparator 240) enables a more accurate comparison.

Specifically, referring to FIG. 2, assuming that the unstable range is from REFDN to REFUP around the center voltage CM, the second comparator 240 newly performs a comparison process with respect to the range from REFDN to REFUP. Will be performed. A certain number of preamps and comparators may be additionally needed to perform the new comparison process. Here, REFUP may mean a maximum value of an unstable region, and REFDN may mean a minimum value of an unstable region. The unstable region may be determined by experiment or may be determined by predetermined information. For example, a range corresponding to 10% of the range from the center voltage CM to the highest reference voltage positive (hereinafter referred to as REFP) may be set as the REFUP value. The range corresponding to 10% of the range from the center voltage CM to the lowest reference voltage value (hereinafter, referred to as REFN) may be set as the REFDN value. In addition, the maximum value and the minimum value of the unstable region may be set differently for the upper region and the lower region of the center voltage.

Therefore, the comparison between the first comparison unit 230 and the second comparison unit 240 may be performed more accurately with respect to the range from REFDN to REFUP.

The reference voltage generator 220 may generate a plurality of reference voltages having different levels through a resistor string. At this time, it may not function but may require a formally form, which is called a dummy region. For example, referring to FIG. 2, a region between REFP and REFP_D (REFerence voltage positive dummy) and a region between REFN and REFN_D (REFerence voltage negative dummy) may be viewed as a dummy region.

Output values output through the first comparator 230 and the second comparator 240 are converted into digital codes (thermometer codes) by the original number through the comparator output corrector 250. For example, in the case of a 6-bit flash analog-to-digital converter, if 33 comparators are used in the first comparator 230 and 9 comparators are used in the second comparator 240, 42 output values are output. Can be. The 42 output values may be converted into 63 digital codes through the comparator output corrector 250. In this case, the comparator output corrector 250 may use, for example, a bubble error corrector.

The encoder 260 receives the converted digital code and finally outputs a digital output of a desired nbit resolution. The encoder 260 may detect a position of a boundary point where 1 and 0 of the digital code intersect, and output a unique code value corresponding to the position. At this time, the irregular mixing of 1 and 0 near the boundary point of the digital code is called bubble error. Therefore, the comparator output corrector 250 may correct the bubble error.

3 is an embodiment to which the present invention is applied and shows an internal circuit diagram of the preprocessor 210.

The preprocessor 210 may include a comparator 211, a flipflop 212, a sample holder 213, and a switch 214, 215, 216, 217. The comparison range of the comparators 140, 230, and 240 may be reduced through the preprocessor 210, and the number of preamplifiers and comparators may be reduced by reducing the comparison range.

First, differential inputs of INP and INN may be simultaneously applied to the comparator 211 and the sample holder 213. The comparator 211 compares the difference between the INP and the INN while sampling the input from the sample holder 213. For example, when INP> INN, 1 may be output to COMP, which is an output value of the comparator 211. When INP <INN, 0 may be output to COMP, which is an output value of the comparator 211. In the hold mode, the sample holder 213 outputs a frequency of a fast input to a constant value with little change. Therefore, when the sample holder 213 is in the hold mode, the SH_P and SH_N output values are output, and these values may be applied to a plurality of switches, respectively. For example, in FIG. 3, a total of four switches 214, 215, 216, 217 may be formed, and the SH_P and SH_N output values may be applied to two switches, respectively. Among the plurality of switches, the first switch 214 and the fourth switch 217 may be turned on at the same time, and the second switch 215 and the third switch 216 may be turned on at the same time. The switches are turned on or off via a Q bar signal that is the opposite of Q exiting the flip-flop 212. In FIG. 4, the internal circuit of the preprocessor 210 is described in detail.

4 illustrates an input and output waveform for explaining the operation of the preprocessor 210 as an embodiment of the present invention.

Referring to the operation waveform of FIG. 4, when INP> INN (section 1), COMP, which is an output value of the comparator 211, has 1, and finally Q is 1 and Q bar is 0 through the flip-flop 212. Have. When Q is 1, the first switch 214 and the fourth switch 217 are turned on, and the second switch 215 and the third switch 216 are turned off. Accordingly, the output values SH_P and SH_N of the sample holder 213 come out as OUTP and OUTN, which are output values of the preprocessing unit 210, without change.

On the contrary, when INP < INN (section 2), COMP, which is an output value of the comparator 211, has 0, and output Q of the flip-flop 212 has 0 and Q bar has 1. Since Q is 0, the second switch 215 and the third switch 216 are turned on, and conversely, the first switch 214 and the fourth switch 217 are turned off. In this case, SH_P and SH_N, which are output values of the sample holder 213, are connected to OUTN and OUTP, which are output values of the preprocessing unit 210, respectively, so that an output having an opposite phase of a desired signal is output.

OUTP ?? which is the last output waveform of FIG. In the OUTN waveform, the region (section 2) between the dashed lines is the region where INP <INN and has a phase opposite to the actual signal phase. This is the second waveform of FIG. In the INN waveform, the transducer's original comparison range is 1 V, while the last waveform, OUTP ?? The waveform of OUTN is always greater than the center voltage (CM), so the comparison range is reduced to half of 0.5V. Therefore, the number of preamplifiers and comparators used in the preamplifier 130 and the comparator 140 can be reduced by half by the comparison range reduced by half. However, when a more accurate comparison is performed by adding a comparator to an unstable region, the number of comparators may be increased by an additional amount.

As mentioned above, preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and those skilled in the art can improve other various embodiments within the spirit and technical scope of the present invention disclosed in the appended claims below. Changes, substitutions or additions will be possible.

1 is a block diagram of an analog-to-digital converter as an embodiment to which the present invention is applied.

2 is a block diagram of an analog-to-digital converter as an embodiment to which the present invention is applied.

3 is an embodiment to which the present invention is applied and shows an internal circuit diagram of the preprocessor 210.

4 illustrates an input and output waveform for explaining the operation of the preprocessor 210 as an embodiment of the present invention.

Claims (9)

In the device for converting an analog signal into a digital signal, A preprocessor adjusting a comparison range of the comparator by using a switch; A first comparing unit comparing an input voltage and a reference voltage based on the adjusted comparison range; And An encoding unit for encoding the digital code output from the first comparing unit Analog-to-digital converter comprising a. The method of claim 1, wherein the preprocessing unit, Comparators Comparing Differential Input Signals A flip-flop for keeping the output value of the comparator constant according to a clock signal; Sample holder for outputting the differential input signal to a constant value Analog-to-digital converter comprising a. The method of claim 2, And the switch is adjusted based on the output value of the flip-flop. The method of claim 2, And using the switch, output value of the sample holder to be out of phase. The method of claim 1, The comparison range is divided into an upper region and a lower region based on the intermediate voltage. The method of claim 1, If the input voltage falls within a predetermined range, the analog-to-digital converter further comprises a second comparison unit for performing an additional comparison process. In the method for converting an analog signal into a digital signal, Adjusting a comparison range of the comparator using a switch; Comparing an input voltage and a reference voltage based on the adjusted comparison range; And Encoding the output digital code based on the comparison range Analog-digital conversion method comprising a. The method of claim 7, wherein The comparison range is divided into upper region and lower region based on the intermediate voltage. The method of claim 7, wherein If the input voltage falls within a predetermined range, the analog-to-digital conversion method characterized in that for performing additional comparison process.

Images