JP2003032117A - Integral type analog to digital converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a single integral type analog/digital converter that uses a low frequency analog/digital conversion clock in order to monitor and measure an integral value of battery charging/discharging currents with low power consumption and extended dynamic range and measures an integral value even from a bipolar input current. SOLUTION: The analog/digital converter uses an integrator to integrate a current in response to a signal input, allows a constant current source to supply or extract a constant current to or from the integrator depending on the output polarity of the integrator when the integral value of the input signal reaches a prescribed value in a direction of decreasing its integral value and allows an up-down counter to count up or count down a count only for a period of the constant current flowing.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integral type A / D converter for measuring a direct current, and more particularly to an integral type A / D converter suitable for measuring an integrated value of a charge / discharge current of a battery. / D converter. 2. Description of the Related Art Notebook personal computers and personal portable terminals (PDs)
A), a battery is frequently used as a power source for various electric devices such as a digital still camera (DSC), a smart phone, an electric vehicle, and a power-assisted bicycle. [0003] These batteries, for example, lithium-ion batteries used in notebook personal computers, may explode if overcharged, which exceeds the rating at the time of charging. Excessive discharge will result in deterioration of the charge / discharge characteristics. [0004] In order to avoid such a situation and sufficiently exhibit the performance of the battery, it is necessary to perform charge and discharge control suitable for charge and discharge characteristics. For this reason, measuring devices for monitoring the charge and discharge states of the battery have been used. A conventional measuring device applies a charge / discharge current (for example, 0.5 mA to 15 A) that varies over a wide range to a voltage (5 μV).
To 150 mV), amplify the converted voltage, sample and hold, convert to a digital signal with a multi-bit (for example, 10-bit) successive approximation A / D converter, and perform averaging processing and the like. It is composed of a microcontroller unit (MCU) and the like. In this conventional measuring apparatus, an integrated value of the charging / discharging current is obtained based on a product of time and a discrete value obtained at a predetermined sampling period. It is difficult to improve the accuracy of the current integrated value measurement due to the fact that the range is wide and affected by continuous minute current and noise. Further, since the operation time of the MCU that consumes a relatively large current is long, it has been difficult to reduce power consumption. Further, as shown in FIGS. 3 and 4, an integration type A / D converter for integrating a continuous value and performing A / D conversion has been conventionally known. 3 and 4, first, the integration circuit 301 has the integration output Ea at zero voltage (this state is referred to as a "reset state"). In this state, the start pulse s is applied, and the flip-flop 3
When 03 is set, only the switch S1 is turned on (the switch S2 remains off) and connected to the input signal Ei side. The integration circuit 301 starts integration of the input signal Ei, and a first integration period Ts, which is a reference period, starts and the slope −E
i / RC output Ea is generated, and the output Ea is compared with the comparison voltage −ΔV
When t is exceeded, a comparison pulse p is generated. As a result, the AND circuit 306 is opened, and the counter 304 starts counting clock pulses of the clock pulse generation circuit 305. After a certain time Ts, the count value of the counter 304 reaches the overflow value Nm,
An overflow pulse r is output, and the flip-flop 303 is reset. Therefore, the switch S1 is turned off,
Only the switch S2 is turned on, switching to the reference voltage −Es side starts the second integration period T, and the integration circuit 301 performs integration of the gradient Es / CR which is opposite to the previous one. When the output Ea returns to the comparison voltage −ΔVt, the comparison circuit 302 is inverted, and the AND circuit 306 is closed. During this time, counter 3
04 counts again from 1 after the overflow, and the count value N when the AND circuit 306 is closed is equal to the input signal Ei.
Is proportional to As described above, the input signal E is output by the integrating circuit 301.
i is integrated for a reference period Ts, and then the integration circuit 301 is switched to a reference voltage −Es having a polarity opposite to that of the input signal Ei, and the integrated value is returned to zero. Since the first half integrated voltage value of the integrating circuit 301 is proportional to the value of the input signal Ei, and the second half reverse integration time T is also proportional to the value of the input signal Ei.
By counting clock pulses during this period, A / D
You can do the conversion. This conventional integral type A
The / D converter has the advantage that the circuit can be configured at low cost and is less susceptible to noise. However, this conventional A / D converter has a limitation on the number of bits when the value of the input current varies over a wide range, such as the charge / discharge current of a battery. It is difficult to achieve high accuracy due to
In order to end the A / D conversion operation quickly while performing the conversion over a wide range, it is necessary to use an A / D conversion clock as a high-frequency clock, so that it is difficult to reduce power consumption. Have. Further, there is a problem that the case where the polarity of the input current fluctuates between the positive polarity and the negative polarity cannot be dealt with, and the input current cannot be continuously integrated. In view of the above problems of the conventional apparatus, the present invention provides a low power consumption using a low frequency A / D conversion clock to monitor and measure the integrated value of the charge / discharge current of the battery. It is an object of the present invention to provide an integrating A / D converter capable of shortening the time until the end of A / D conversion and expanding the dynamic range. It is another object of the present invention to provide an integrating A / D converter that can measure an integrated value with a single unit even for positive and negative input currents. [0014] According to the first aspect of the present invention, an integral type A / D is provided.
The converter includes an integrator including an amplifier, a capacitor connected between an input terminal and an output terminal of the amplifier, and an input resistor connected to an input terminal of the amplifier, and an inverting input of the amplifier of the integrator. First constant current means for flowing a constant current in response to a command signal, and second constant current means for flowing a constant current in response to the command signal from the inverting input;
Generating a first comparison output when the output of the integrator exceeds a predetermined positive voltage, and generating a second comparison output when the output of the integrator exceeds a predetermined negative voltage; And a comparing means for generating a third comparison output when the output of the integrator reaches zero voltage, counting up according to an up command signal, down-counting according to a down command signal, and timely counting the count value. An up / down counter to be output, the first comparison output, the second comparison output, and the third comparison output are input, and the first constant current means, the second constant current means, Control means for supplying each command signal to the up / down counter, wherein a command signal is provided to the first constant current means and a down command signal is provided to the up / down counter in response to the first comparison output. Stopping the command signal and the down command signal in response to the third comparison output, and sending a command signal to the second constant current means and an up command signal to the up / down counter in response to the second comparison output. Respectively, and the command signal and the up command signal are stopped according to the third comparison output. According to the present invention, in the integration type A / D converter for monitoring and measuring the integrated value of the charge / discharge current of the battery, the A / D conversion is started during the integration of the input signal. The time until the end of the conversion can be shortened. If the time is not shortened, the A / D conversion clock can be set to a low frequency to reduce the current consumption. Further, when the integrated value of the input signal reaches a predetermined value, a constant current flows in or out in a direction to reduce the integrated value, so that the dynamic range of A / D conversion can be expanded. For this reason, the input signal of the same level is A /
At the time of D-conversion, high precision can be achieved by adjusting the gain of an amplifier or the like. Further, according to the output polarity of the integrator, a constant current flows out or flows in a direction to reduce the integrated value, and the up / down counter is up-counted or down-counted. However, the integrated value can be measured by one device. Embodiments of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a diagram showing a configuration of an integrating A / D converter according to an embodiment of the present invention. In FIG. 1, an input signal Vin is a voltage proportional to a charging current or a discharging current of a battery, and is obtained, for example, as a voltage drop of a current detecting resistor.
It fluctuates in a wide range of ± 150 mV.
During the integration period of the input signal Vin, the switch SW1 and the integrator 10 are turned on by the control signal TC1.
Ai via the high-resistance input resistor Ri
Is supplied to the inverting input terminal. The input signal Vin is input to the inverting input terminal of the amplifier Ai of the integrator 10 via the resistor Ri, and the constant current I2 is supplied from the power supply voltage Vcc by the constant current source I2.
d is supplied via the switch SW3. The switch SW3 is connected between the time when the output voltage of the integrator 10 exceeds the predetermined positive value Ep and the time when it reaches zero voltage, or the time when the integrator 1
It is turned on from the time when the output voltage of 0 is positive and the integration period of the integrating A / D converter ends to the time when it reaches zero voltage. A constant current Iu is supplied to the inverting input terminal of the amplifier Ai of the integrator 10 from the constant current source I1 to the ground voltage Vgnd via the switch SW2. The switch SW2 is connected between the time when the output voltage of the integrator 10 exceeds the negative predetermined value Em and the time when the output voltage of the integrator 10 reaches zero, or the time when the output voltage of the integrator 10 is negative and the integration period of the integrating A / D converter is changed. Is turned on from the end of the operation to the point when the voltage reaches zero voltage. The constant current Iu and the constant current Id usually have the same current value, but the magnitude is determined by the magnitude of the input current due to the input signal Vin and the output dynamic range of the integrator. That is, the output of the integrator generated by the difference between the charge accumulated in the capacitor Ci due to the input current by the input signal Vin and the charge accumulated in the capacitor Ci by the integration period T0 is determined to be smaller than the dynamic range. You. That is, {(Vin / Ri) −Iu} × T0 / Ci ≦ integrator 1
The output dynamic range of 0 The integrator 10 is composed of an amplifier Ai, a resistor Ri, and a capacitor Ci. A resistor Ri is connected to an inverting input terminal of the amplifier Ai. A capacitor Ci is connected between the capacitors and functions as an integrating amplifier. The non-inverting input terminal of the amplifier Ai is connected to the ground voltage Vgnd or a predetermined bias voltage. A switch SW4 is connected between the terminals of the capacitor Ci, and the switch SW4 is momentarily closed at the beginning of a new integration period to eliminate the residual charge. When the integration period is set continuously, it is not closed to maintain the continuity of the measurement. The first comparator Cp has a non-inverting input terminal receiving the output voltage c of the integrator 10 and an inverting input terminal receiving a predetermined voltage E.
When p is supplied and the output voltage c exceeds the voltage Ep, a first comparison output e is output. In the second comparator Cm, an output voltage c of the integrator 10 is supplied to an inverting input terminal, a negative voltage Em having a predetermined value is supplied to a non-inverting input terminal, and the output voltage c is a voltage Ep.
Is output in the negative direction, the second comparison output f is output. In the third comparator Cz, the output voltage c of the integrator 10 is supplied to the non-inverting input terminal, the ground voltage Vgnd or a predetermined bias voltage is supplied to the inverting input terminal, and the output voltage c is positive, negative, or higher than the predetermined voltage. Or the third comparison output d
Is inverted. Since the third comparator Cz is for determining the zero crossing of the output voltage c, any device can be used as long as it can perform this function. The control logic means 20 receives the first comparison output e, the second comparison output f, the third comparison output d, and the timing signal, and outputs an up-count signal LO1 and a down-count signal LO2. Also, it outputs a data output command signal LO3. The up-count signal LO1 is output from when the second comparison output f is output until the third comparison output d is inverted, or when the third comparison output d is low (the output voltage of the integrator 10 corresponds to a negative value). ) And from the end of the integration period of the present integral A / D converter until the third comparison output d is inverted to high. Further, the down count signal LO2 is the first
From the time when the comparison output e is output to the time when the third comparison output d is inverted, or when the third comparison output d is high (the output voltage of the integrator 10 is positive) and the integration of the present integration type A / D converter is performed. It is turned on from the end of the period until the third comparison output d is inverted to low. The up / down counter 30 has an up count terminal U, a down count terminal D, a count output terminal O, and a reset terminal R. To the reset terminal R, a timing signal for resetting the count value when a new integration period starts is applied. If the integration period is set continuously, the count value at that time is output and reset to keep the continuity of the measurement, and the count is subsequently performed. The clock signal is input to the up-count terminal U while the switch SW5 is closed by the up-count signal LO1, and counts up. The clock signal is input to the down-count terminal D while the switch SW6 is closed by the down-count signal LO2, and counts down. The register 40 receives the count value of the up / down counter 30 when the switch SW7 is closed, and additional information indicating the data content of the count value.
For example, data is output with a sign indicating positive or negative. A control signal is applied to the switch SW7 so as to be turned on when the count value corresponding to one integration period is completed. When the integration period is set continuously, the switch SW7 is turned on at the end of the integration period, and the count value at that time is output. The clock pulse generator 50 supplies a clock signal voltage, which is a time reference of the present apparatus, to the up / down counter 30 and the timing controller 60. The timing controller 60 receives a clock signal voltage and an external operation signal as required, generates various timing signals, and supplies them to required portions. The timing signal TC1 is output during the integration period and supplied to the switch SW1 and the control logic unit 20. The timing signal TC2 is output at the moment when a new integration period starts, and is supplied to the switch SW4 and the up / down counter 30. The timing signal TC3 is A /
This is an operation timing signal for D conversion and supplied to the control logic means 20. In addition, a timing signal can be formed and used as needed. Now, the integral type A / D in this embodiment
The operation of the converter will be described with reference to the timing chart of FIG. The following description relates to the operation during one integration period. The timing controller 60 receives a clock signal voltage from the clock pulse generator 50 and an external command signal. When the integration period starts at time point t1, a timing signal TC1 is supplied from the timing controller 60 to the switch SW1, and the switch SW1 is closed during the integration period. At the same time, the timing signal TC2 is given from the timing controller 60 to the switch SW4 and the up / down counter 30, and the residual charge of the capacitor Ci is discharged and the count value of the up / down counter 30 is reset. After the start of the integration period, integration is performed by the integrator 10 according to the input signal Vin (potential at point a), and the potential at point c, which is the output, increases in the negative direction according to the input signal Vin of positive polarity. . At time t3 when the potential at the point c exceeds the bias voltage Em of the second comparator Cm, the second comparison output f rises and is applied to the control logic means 20. In the control logic means 20, the second comparison output f and the timing signal T indicating the A / D conversion operation timing are output.
An up-count signal LO1 is generated under an AND condition with C3. The up-count signal LO1 is first supplied to the switch SW5 and is closed. While the switch SW5 is closed, the clock signal voltage from the clock pulse generator 50 is supplied to the up-count terminal U of the up-down counter 30, and the count value of the up-down counter 30 is counted up. At the same time, the up-count signal LO1 is supplied to the switch SW2 to close.
While the switch SW2 is closed, the constant current Iu flows out of the capacitor Ci of the integrator 10. In other words, the difference between the current flowing in response to the input signal Vin and the constant current Iu charges the capacitor Ci or charges the capacitor Ci.
From the battery. When the constant current Iu is discharged, the potential at the point c gradually recovers. When the potential drops below the bias voltage Em of the second comparator Cm, the second comparison output f falls. However, in this state, the circuit operation is still changed. There is no. At time t4 when the potential at the point c further recovers and reaches the zero potential of the third comparator Cz, the third comparison output d is inverted and applied to the control logic means 20. The control logic means 20 stops the up-count signal LO1 by inverting the third comparison output d. As a result, the switch SW5 is opened, the up-counting operation of the up / down counter 30 is stopped, the switch SW2 is opened, and the outflow of the constant current Iu is stopped. In this way, the discharging of the constant current Iu and the up-counting are performed in parallel with the integration of the input signal Vin, and the A / D conversion is performed during the integration of the input signal Vin. The operation in the period from time t4 to time t7 in FIG. 2 is the same as the operation described above, and the description is omitted. In FIG. 2, when the negative input signal Vin (potential at point a) is generated at time t8, the integrator 1
The potential at the point c, which is an integrated output of 0, is a negative input signal Vin.
Increases in the positive direction. At time t9 when the potential at the point c exceeds the bias voltage Ep of the first comparator Cp, the first
The comparison output e rises and the control logic means 2
0 is applied. In the control logic means 20,
At the time point t10 when the AND condition between the first comparison output e and the timing signal TC3 as the A / D conversion operation timing is generated, the down-count signal LO2 is generated. The down-count signal LO2 is supplied to the switch SW6 to be closed. While the switch SW6 is closed, the clock signal from the clock pulse generator 50 is supplied to the down count terminal D of the up / down counter 30, and the count value of the up / down counter 30 is counted down. At the same time, the down-count signal LO2 is supplied to the switch SW3 to close. While the switch SW3 is closed, the constant current Id is
Flows into the capacitor Ci. In other words, a current having a difference between the current according to the input signal Vin and the constant current Id is charged to the capacitor Ci or discharged from the capacitor Ci. When the constant current Id is charged, the potential at the point c gradually recovers. When the potential drops below the bias voltage Ep of the first comparator Cp, the first comparison output e falls. In this state, the circuit operation is still changed. There is no. When the integration period ends at the time point t11 during the recovery of the potential at the point c due to the charging of the constant current Id, the timing signal TC1 from the timing controller 60 is turned off and the switch SW1 is opened at the time point t11. You. However, at this time point t11, the A / D conversion operation is being performed, and the A / D conversion operation is continued even after the integration period ends. Then, the time point t1 when the potential at the point c further recovers and reaches the reference potential (zero potential) of the third comparator Cz.
At 2 the third comparison output d is inverted and applied to the control logic means 20. Control logic means 2
At 0, the down-count signal LO2 is stopped due to the inversion of the third comparison output d. As a result, the switch SW6 is opened, the down-counting operation of the up / down counter 30 is stopped, the switch SW3 is opened, and the inflow of the constant current Id is stopped. Further, the control logic means 20 supplies the data output command signal LO3 to the switch SW7. The up-count pulse i and the down-count pulse j during this period are as shown in FIG. 2, and the resulting count data k (time t11 or time t12) of the up-down counter 30 is integrated measurement during the integration period. The data is stored in the register 4 via the switch SW7.
Input to 0. The register 40 outputs the data with the input count data and additional information indicating the data content, for example, a sign indicating positive or negative. Although not shown in the timing chart of FIG. 2, the output voltage of the integrator 10 is equal to that of the second comparator Cm.
If the integration period ends with the bias voltage Em (or the bias voltage Ep) of the first comparator Cp remaining at a low value without exceeding the bias voltage Em (or the bias voltage Ep), it is determined that the integrated value in this state becomes an error. Need to be avoided. Therefore, the time t11 at which the integration period ends
In accordance with the inversion state (positive to negative or negative to positive) of the third comparison output f of the third comparator Cz, the switch SW
2. Close the switch SW5 to perform the outflow and up-count of the constant current Iu, or close the switches SW3 and SW6 to perform the inflow and down-count of the constant current Id. This count is the third comparison output d of the third comparator Cz.
Is terminated when is inverted again. In this embodiment, in the integration type A / D converter for monitoring and measuring the integrated value of the charging / discharging current of the battery, the A / D conversion is performed during the integration of the input signal Vin proportional to the charging / discharging current of the battery. Since the conversion, that is, the counting operation is started, the clock TC3 of the A / D conversion can be set to a low frequency, and the A / D after the integration period is completed.
The time until the end of the conversion can be reduced. Further, when the integrated value c of the input signal Vin reaches the predetermined values Em and Ep, the constant currents Iu and Id flow in or out in a direction to reduce the integrated value c.
The dynamic range of A / D conversion can be expanded. For this reason, when the input signal Vin of the same level is A / D-converted, high precision can be achieved by adjusting the gain of an amplifier or the like. Further, according to the output polarity of the integrator 10, the constant currents Iu and Id flow out or in the direction of decreasing the integrated value c, and the up / down counter 30 is counted up or down. The integrated value can be measured by one unit even for the input current of the polarity. Next, the operation when the integration period is set continuously will be described. This operation will be described focusing on differences from the operation in one integration period. Immediately after the end of one integration period, the next integration period starts. In this case, at the end of one integration period, the switch SW7 is closed, the count value of the up / down counter 30 at that time is output to the register 40, and after this output, the count value of the up / down counter 30 is reset once. The other operating conditions do not change significantly with the end of one integration period.
SW6 is also in the normal operation state of the integrating A / D converter. At each end of each integration period, the count data corresponding to the integration period, that is, the integrated value of the input signal is sequentially output from the register 40. As described above, it is possible to integrate input signals for a plurality of continuous integration periods, which could not be expected with the conventional integrating A / D converter. According to the present invention, in the integrating A / D converter for monitoring and measuring the integrated value of the charging / discharging current of the battery, the A / D conversion is started while the input signal is being integrated. Therefore, the time until the end of the A / D conversion can be shortened. If the time is not shortened, the current consumption can be reduced by setting the A / D conversion clock to a low frequency. Further, when the integrated value of the input signal reaches a predetermined value, a constant current flows in or out in a direction to reduce the integrated value, so that the dynamic range of A / D conversion can be expanded. For this reason, the input signal of the same level is A /
At the time of D-conversion, high precision can be achieved by adjusting the gain of an amplifier or the like. Further, according to the output polarity of the integrator, a constant current is caused to flow out or flow in the direction of decreasing the integrated value, and the up / down counter is counted up or down. However, the integrated value can be measured by one device.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a configuration of an integrating A / D converter according to an embodiment of the present invention. FIG. 2 is a timing chart of the integration type A / D converter according to the embodiment of the present invention. FIG. 3 is a diagram showing a configuration of a conventional integrating A / D converter. FIG. 4 is a timing chart of a conventional integrating A / D converter. DESCRIPTION OF SYMBOLS 10 Integrator 20 Control logic means 30 Up / down counter 40 Register 50 Clock pulse generator 60 Timing controller Vin Input signal Iu, Id Constant current Ri Input resistance Ai Amplifier Ci Capacitor Cp First comparator Cm Second comparison Device Cz third comparator

Claims (1)

Claims: 1. An integrator comprising an amplifier, a capacitor connected between an input terminal and an output terminal of the amplifier, and an input resistor connected to an input terminal of the amplifier. First constant current means for flowing a constant current into the inverting input of the amplifier according to a command signal in accordance with a command signal; second constant current means for flowing a constant current from the inverting input in response to a command signal; A first comparison output is generated when the output exceeds a predetermined positive voltage, a second comparison output is generated when the output of the integrator exceeds a predetermined negative voltage, and the integrator is also generated. A comparison means for generating a third comparison output when the output of the inverter reaches zero voltage; an up-counter for counting up according to an up command signal, down-counting according to a down command signal, and outputting a count value in a timely manner. And the first comparison output, the second comparison output, and the third comparison output. The first constant current unit, the second constant current unit, and the up / down Control means for supplying each command signal to the counter; providing a command signal to the first constant current means and a down command signal to the up / down counter in response to the first comparison output; The command signal and the down command signal are stopped according to the output, and the command signal is given to the second constant current means and the up command signal is given to the up / down counter according to the second comparison output, respectively. (3) An integral type A / D converter, wherein the command signal and the up command signal are stopped according to the comparison output.