RU2460210C1 - "analogue-digital-analogue" integrating converter - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: device has an input signal source, adders, an integrator, relay elements, n proportional links, n switch elements, a reference digital code source and a code subtracting unit.

EFFECT: faster operation and accuracy of the analogue-digital-analogue converter.

10 dwg

Description

The device relates to the field of computer technology and can be used in automation systems for direct and inverse conversion of an analog signal into a digital code.

Known analog-to-digital Converter (ADC) by the push-pull integration method, containing an integrator, key elements, pulse generators, counter, memory register, delay element (Volovich G.I. Circuitry of analog and analog-to-digital electronic devices. / G.I. Volovich . - M.: Dodeka-XXI Publishing House, 2005. - 459 p.).

The known device has insufficient accuracy, which is a consequence of the open nature of its structure.

There is a method of analog-to-digital conversion by sequential time-wise actions of bitwise balancing from a high order to a low order and the scheme of its implementation in the form of a multitude of ADCs with the generally accepted term "bitwise balancing". With all the variety of such ADCs, they contain an input signal source, a device for its comparison (the first adder) with the output signal of a digital-to-analog converter (DAC), the code inputs of which are simultaneously the output code of the entire ADC and are controlled by a ring distributor, which itself is controlled by the output of the comparison device. The correct code is generated and periodically fixed at the end of each cycle of the clock distributor (Temnikov F.E. Theoretical foundations of information technology. / Temnikov F.E., Afonin V.A., Dmitriev V.I. - M .: Energy, 1979 . - 512 s. See p. 118, 119, fig. 3-20, 3-21).

The disadvantage of this device is its increased complexity, reduced performance due to the delay for the cycle time of the ring distributor, the cyclical nature of the output of the conversion results.

Closest to the proposed device is a multi-zone deployment transducer containing serially connected input signal source, the first adder and integrator, the output of which is connected to the inputs of a group of an odd number of relay elements, the outputs of which are connected to the inputs of the second adder, the output of which is connected to the output of the device and the second input of the first adder (SU No. 1183988 of April 27, 1984, publ. 07.10.85. Bull. No. 37).

The device is used to convert an analog signal into a multi-zone signal with a frequency-pulse-width-modulation (PWM).

In its original form, the prototype device cannot operate in the mode of converting an analog signal to a digital signal followed by a reverse digital-to-analog conversion (DAC).

To convert the output signal of the prototype device into code, it is necessary to include a smoothing filter at its output and directly the ADC of one or another operating principle.

Such a structure will have low accuracy and reduced speed, since it is almost impossible to match the amplitude value of the ripple at the output of the smoothing filter during CWP, which can then be taken into account as a constant value of the conversion error with the clock frequency of the ADC.

Thus, the well-known technical solution when constructing an ADC based on it will be characterized by low speed and low accuracy.

At the same time, the well-known technical solution relates to closed-loop control systems, which makes it possible, with appropriate circuitry additions, to organize on its basis a high-precision integrating Analog-Digital-Analogue converter.

An object of the invention is to increase the speed and accuracy of the ADC-DAC on the basis of the well-known integrating multi-zone pulse-frequency pulsed deployment converter.

The problem is solved in that the integrating Converter "Analog-Digital-Analog" contains serially connected input signal source, the first adder, integrator and the first relay element from the group containing the nth number of relay elements, and n = 1, 2, 3 ... an integer, a second adder, the output of which is connected to the analog output of the device and connected to the second input of the first adder, the digital outputs of the device are characterized by the fact that the nth number of proportional links, n-1 additional adders, are introduced into it, n the number of key elements, the source of the reference digital code and the device for subtracting codes, moreover, the output of each relay element through the corresponding proportional link is connected to the corresponding input of the second adder, and also connected to the input of the corresponding key element, the output of each key element is connected to the first group of device inputs subtracting codes, the second group of inputs of which is connected to the corresponding outputs of the source of the reference digital code, the outputs of the device for subtracting codes are connected to the corresponding digital outputs of the Analog-Digital-Analog converter, while the output of each of the additional adders is connected to the input of each relay element, starting from the second, the first input of each of the additional adders is connected to the output of the previous of the n-th number of proportional links, the second the input of the first additional adder is connected to the output of the integrator, and the second input of each of the subsequent additional adders is connected to the output of the previous additional adder.

The proposed device provides high speed and accuracy of the ADC-DAC.

The stated technical problem is achieved due to the fact that the ADC and DAC channels are covered by a general negative feedback, as well as an integrator in the direct control channel of the device, which increases the accuracy of the converter with reduced bit capacity, increases speed, eliminates the discreteness of the result. Accuracy with a decrease in bit depth is provided by pulse-frequency-pulse-width modulation between the discrete samples of the output code.

The invention is illustrated by drawings:

Figure 1 - functional diagram of the proposed device;

Figure 2, 3, 4, 5 - timing diagrams of the signals of the integrating Converter "Analog-Digital-Analog";

Figa, b - amplitude and modulation characteristics of the integrating Converter "Analog-Digital-Analog";

7 is an example of a circuit diagram of a 4-bit converter;

Fig - waveforms of the Converter signals (an example of a specific implementation of the proposed system).

The structure of the integrating Converter "Analog-Digital-Analog" (figure 1) includes a series-connected first adder 1, integrator 2, the first relay element 3-1, the first proportional link 4-1 with a gain of 2 ^n-1 and the second adder 5 sequentially connected an additional third adder 6-1, a second relay element 3-2 and a second proportional link 4-2 with a gain of 2 ^n-2 , sequentially connected a fourth additional adder 6-2, a third relay element 3-3 and a third proportional link 4-3 with odds Silene 2 ^n-3 series-connected n-th additional adder 6-n, n-th relay unit 3-n and n-th 4-n proportional element with a gain of 2 ^0, as well as of a device includes keys 7-1 , 7-2, ..., 7-n, the inputs of which are connected to the corresponding outputs of the relay elements 3-1, 3-2, ..., 3-n, and the outputs of the keys 7-1, 7-2, ..., 7-n are connected with the first group of inputs of the device for subtracting codes 8, the outputs of which are the “Digital outputs” of the integrating Analog-Digital-Analog converter, and the source of the reference digital code 9 connected to the second input I’ll give a device for subtracting codes 8. Moreover, the output of the second adder 5 is the “DAC output” of the “Analog-Digital-Analog” integrating converter and is simultaneously connected to the first input of the first adder 1, the second input of which is connected to the input signal source - the “input” of the integrating converter “ Analog-Digital-Analog. " The first input of the third additional adder 6-1 is connected to the output of the integrator 2, and the second input of the third additional adder 6-1 is connected to the output of the first proportional link 4-1. The first input of the fourth additional adder 6-2 is connected to the output of the third additional adder 6-1, and the second input of the fourth additional adder 6-2 is connected to the output of the second proportional link 4-2. The first input of the n-th additional adder 6-n is connected to the output of the fourth additional adder 6-2, and the second input of the n-th additional adder 6-n is connected to the output of the third proportional link 4-3. The outputs of the proportional links 4-2, 4-3, ..., 4-n are connected to the corresponding inputs of the second adder 5.

The links of the integrating Converter "Analog-Digital-Analog" (figure 1) have the following characteristics.

Adders 1, 6-1, 6-2, ..., 6-n contain two inputs with a single transmission coefficient for each of them and perform the operation of subtracting signals.

The integrator 2 has a transfer function W (p) = 1 / Tr, where T is the integration time constant. With a discrete change in the input action, the output signal of the integrator 2 changes linearly with a sign that coincides with the sign of the signal at its input.

Relay elements 3-1, 3-2, ..., 3-n are made with a hysteresis loop symmetrical with respect to “zero”. Their output signal varies discretely within ± A. However, the ultimate speed is achieved with relay elements without hysteresis, when it is difficult to describe the sequence of their work.

The proportional units 4-1, 4-2, ..., 4-n are implemented with amplification factors that vary according to the discharge weight of the converted code with an arbitrary base, but more often with a binary code proportional to 2 ^n-1 , 2 ^n-2 , ..., 2 ^0, respectively. Here n is the number of bits of the binary code. The largest coefficient of the proportional link 2 ^n-1 corresponds to the weight of the highest bit of the binary code, and the smallest 2 ⁰ corresponds to the weight of the least significant bit.

The adder 5 has the nth number of inputs with a single transmission coefficient for each of the inputs and performs the operation of summing the signals. The number of inputs of the adder is chosen equal to the number of bits n of the converted binary code.

The keys 7-1, 7-2, ..., 7-n convert the bipolar output pulses of the relay elements 3-1, 3-2, ..., 3-n into unipolar for the subsequent coordination of the outputs of the relay elements 3-1, 3-2, ... , 3-n with digital inputs of the code subtractor 8. Each key has a zero on / off threshold and a non-inverting input-output characteristic.

The device for subtracting codes 8 performs the operation of bitwise subtraction from code N ₁ generated at the output of keys 7-1, 7-2, ..., 7-n, code N ₂ specified by the source of digital code 9, and can be performed as on the basis of standard microcircuits, and based on programmable controllers.

Figure 1-6 adopted the following notation:

X _I - the input signal of the integrating Converter ("input" of the device);

Y _and - the output signal of the integrator 2;

Y _o - the output signal of the adder 5 ("analog output" of the device);

± А · 2 ^n-1 , ± А · 2 ^n-2 , ± А · 2 ^n-3 , ..., ± А · 2 ⁰ - maximum signal levels at the output of proportional links 4-1, 4-2, 4-3 , ..., 4-n, respectively;

± b - switching thresholds of relay elements 3-1, 3-2, ..., 3-n;

± A - the amplitude of the output pulses of the relay elements 3-1, 3-2, ..., 3-n;

Q _n-1 , Q _n-2 , Q _n-3 , ..., Q ₀ —digits of the digital code at the output of the Analog-Digital-Analog integrated converter;

N ₁ is a digital code at the output of keys 7-1, 7-2, ..., 7-n;

N ₂ is a digital code specified by the source of digital code 9;

N ₃ - digital code at the output of the integrating Converter "Analog-Digital-Analog."

The principle of operation of the device is as follows.

The “Analog-Digital-Analog” integrating converter is a closed system, therefore, in the steady-state mode of operation, the signal level at the input of the converter X _BX must always be balanced by the output voltage Y _EXT DAC. This is only possible with the appropriate (desired) DAC code. When the DAC bit depth does not provide the required conversion accuracy between the levels, the frequency-pulse-width-modulation mode between these levels begins. However, the averaged integral accuracy is always ensured due to the presence of an integrator in the direct control channel. As a result, the amplitude characteristic (Fig. 6a) will always be linear, and the appearing frequency-pulse-width modulation between the samples is indicated by the modulation characteristic in Fig. 6b. Extreme speed is obtained at a zero width of the hysteresis loops of relay elements 3-1 - 3-n, when the self-oscillation frequency is extremely high (infinitely large). In this case, the order of the elements will be the most unexpected, indescribable, chaotic, but the correspondence of the output code to the input signal will always be ensured. This has been verified by experimental research.

Apparently, such an “indescribable chaos” in the work of the proposed device did not allow to approach a similar solution earlier, since the concept of “clocking” was always introduced in the ADC, which determined the strict order of work and the hierarchy of ADC elements for the conversion cycle (see F.E. Temnikov) .

Consider the operation of the device in the presence of hysteresis in the relay elements 3-1 - 3-n.

For an integrating converter, the input signal can be represented as the expression X _BX = ± Δ (k + 0.5 m),

- вес единицы младшего разряда преобразуемого кода в аналоговой форме; А - амплитуда выходных импульсов релейных элементов 3-1, 3-2, …, 3-n;

- максимальное значение двоичного цифрового кода в десятичной системе счисления, формируемого на выходе ключей преобразователя 7-1, 7-2, …, 7-n; А_max=А·N_max - максимальная амплитуда на выходе преобразователя; k=0, 1, 2, …,

- целые числа, соответствующие десятичным числам преобразуемого кода; m - коэффициент, учитывающий изменение входного сигнала на интервале Δ(-1,0≤m≤1,0).Where

- unit weight of the least significant bit of the converted code in analog form; And - the amplitude of the output pulses of the relay elements 3-1, 3-2, ..., 3-n;

- the maximum value of the binary digital code in the decimal number system generated at the output of the converter keys 7-1, 7-2, ..., 7-n; And _max = A · N _max - the maximum amplitude at the output of the Converter; k = 0, 1, 2, ...,

- integers corresponding to decimal numbers of the converted code; m is a coefficient that takes into account the change in the input signal in the interval Δ (-1.0≤m≤1.0).

Consider the principle of operation of the converter for the input signal X _BX = 0, when the numbers k = 0 and m = 0.

We assume that the relay element (RE) 3-1, forming the highest bit of the converted code, is in a "positive" state (fig.2b). Then the amplitude at the output of the proportional link (PZ) 4-1 is equal to And 2 ^n-1 . To fulfill the equality X _BX = Y _o, all other RE 3-2, 3-3, ..., 3-n in the system are forced to switch to the negative position (Fig.2c-d), then the total signal at the output of the adder 5 Y _OUTPUT = A (2 ^n-1 -2 ^n-2 -2 ^n-3 -, ..., -2 ⁰ ) = A (fig.2e). The condition of equality X _BX = Y _OUT is impossible for X _BX = 0, therefore, the signal Y _AND at the output of the integrator 2 begins to linearly decrease under the action of voltage -A from the output of the first adder 1 (Fig.2a), and when the equality Y _AND (t ) = - b the first RE 3-1 switches to the negative state (Fig.2b), and the remaining RE 3-2, 3-3, ..., 3-n - to the positive (Fig.2c-d). Here b is the switching threshold of relay elements 3-1, 3-2, ..., 3-n. As a result, the total signal at the output of the adder 5 Y _OUT = A (-2 ^n-1 +2 ^n-2 +2 ^n-3 -, ..., +2 ⁰ ) = - A

Thus, at X _BX = 0, the integrating converter is constantly in the switching mode of all relay elements with the carrier frequency f ₀ = 1 (4b Т _И ,), where b = b, А is the normalized value of the switching thresholds РЭ 3-1, 3 -2, ..., 3-n; T _And - the integration time constant of the integrator 2.

The keys 7-1, 7-2, ..., 7-n convert the bipolar output pulses of the relay elements 3-1, 3-2, ..., 3-n into unipolar for the subsequent coordination of the outputs of the relay elements 3-1, 3-2, ... , 3-n with digital inputs of the device for subtracting codes 8 (Fig. 1). A positive signal level at the output of RE 3-1, 3-2, ..., 3-n corresponds to a logical signal “1” at the output of the keys 7-1, 7-2, ..., 7-n, and a negative level corresponds to a logical signal “0” "(Figb-d, lc). As a result, when X _BX = 0, at the output of the keys 7-1, 7-2, ..., 7-n, two values of the binary code N ₁ (FIG. 2zh-k) are formed, equal to: (N _max +1) / 2 and ( N _max -1) / 2.

The code subtraction device (UVK) 8 performs the operation of bitwise subtraction from the code N ₁ generated at the output of the keys 7-1, 7-2, ..., 7-n, the code N ₂ specified by the source of the digital code (ICC) 9 so that the digital the code at the output of the integrating converter N ₃ = N ₁ -N ₂ was zero. Take the value of the code N ₂ = (N _max +1) / 2, then when X _BX = 0, the output code of the converter N ₃ in decimal form will be 0 or -1 (fig.2l-o). As a result, a static error is generated at the output of the analog-to-digital converter (ADC), which is equal to the unit of the least significant bit of the converted code N ₃ . With a large number of bits of the integrating Converter "Analog-Digital-Analog" (n≥8), this error has virtually no effect on the accuracy of the ADC and can be neglected.

For other values of k and m = 0, the converter operates similarly to the case with numbers k = 0 and m = 0, when at least one of the relay elements 3 is necessarily in the switching mode with the carrier frequency f ₀ = 1 / (4b T _И ) -1, 3-2, ..., 3-n.

Consider the operation of the Converter for other values of m other than zero and varying in the range of 1.0 <m <1.0, and k = 0, when X _BX = ± A · m. For these values, the device switches to the frequency-pulse-width-modulation (CWPM) mode, in which the switching frequency of the RE 3-1, 3-2, ..., 3-n decreases in accordance with the expression f = f ₀ · (1-m ² ) (fig.3b-d). The state of codes N ₁ and N ₃ at the output of the keys 7-1, 7-2, ..., 7-n and the output of the converter, respectively (Fig. 3), remains the same as for the case k = 0 and m = 0 (Fig. 2).

For m = 1 and any other integer values of k, the switching frequency of RE 3-1, 3-2, ..., 3-n becomes equal to zero and an established process occurs in the ADC when X _BX = Y _OUT. So, for example, when X _BX = A (k = 0), the first RE 3-1 switches to the positive state (Fig.4b), and the remaining RE 3-2, 3-3, ..., 3-n to the negative position ( figv-e). As a result, the total signal at the output of the adder 5 Y _OUT = A (2 ^n-1 -2 ^n-2 -2 ^n-3 -, ..., - 2 ⁰ ) = A (Fig. 4e) is balanced by the input action X _BX = A. The voltage at the output of the integrator 2 reaches a steady-state value Y _AND {t) = b (figa) so as to constantly keep the first RE 3-1 in a positive state (fig.4b). The digital code N ₁ at the output of the keys 7-1, 7-2, ..., 7-n is equal to the value (N _max +1) / 2 (fig.4zh-k), and the code at the output of the converter N ₃ = 0 (Fig. 4l-o).

. Пусть X_BX=А·N_max, тогда все РЭ 3-1, 3-2, …, 3-n переключаются в положительное состояние (фиг.5б-д). В результате суммарный сигнал на выходе сумматора 5 Y_ВЫХ=А(2^n-1+2^n-2+2^n-3+, …, +2⁰)=А·N_max (фиг.5е) уравновешивается входным воздействием Х_BX=А·N_max. Напряжение на выходе интегратора 2 достигает установившегося значения Y_и(t)=(N_max-1)+b (фиг.5а) так, чтобы постоянно удерживать все РЭ 3-1, 3-2,…, 3-n в положительном состоянии (фиг.5б-д). Все выходы ключей 7-1, 7-2, …, 7-n находятся в состоянии логической «1» (фиг.5ж-к), что соответствует максимальному коду N₁=N_max. При вычитании из кода N₁ кода N₂=(N_max+1)/2 получаем код на выходе преобразователя N₃=(N_max-1)/2 (фиг.5л-о).The integrating converter works similarly for other values of k and m = 1. For example, the maximum possible value k = (N _max -1) / 2 will correspond to the maximum level of the input signal

. Let X _BX = А · N _max , then all RE 3-1, 3-2, ..., 3-n switch to a positive state (fig.5b-d). As a result, the total signal at the output of the adder 5 Y _OUTPUT = A (2 ^n-1 +2 ^n-2 +2 ^n-3 +, ..., +2 ⁰ ) = А · N _max (Fig. 5e) is balanced by the input action X _BX = A · N _max . The voltage at the output of the integrator 2 reaches a steady-state value of Y _and (t) = (N _max -1) + b (figa) so as to constantly keep all RE 3-1, 3-2, ..., 3-n in a positive state (Fig.5b-d). All outputs of the keys 7-1, 7-2, ..., 7-n are in the logical state “1” (Fig.5zh-k), which corresponds to the maximum code N ₁ = N _max . When subtracting from the code N _{1 the} code N ₂ = (N _max +1) / 2, we obtain the code at the output of the converter N ₃ = (N _max -1) / 2 (Fig.5l-o).

When X _BX = -A · N _max , on the contrary, all RE 3-1, 3-2, ..., 3-n switch to the negative state when the voltage at the output of the adder 5 changes sign and becomes equal to Y _OUT = -A (2 ^n-1 +2 ^n-2 +2 ^n-3 +, ..., +2 ⁰ ) = - А · N _max . All outputs of the keys 7-1, 7-2, ..., 7-n are in the logical "0" state, which corresponds to the minimum code N ₁ = 0. Subtracting from the code N _{1 the} code N ₂ = (N _max +1) / 2, we obtain the output code N ₃ = - (N _max +1) / 2.

и модуляционная

характеристики интегрирующего преобразователя «Аналог-Цифра-Аналог» в относительных единицах приведены на фиг.6а, б соответственно. Здесь

- нормированное значение входного сигнала, отнесенного к максимальной амплитуде на выходе преобразователя А_max=А·N_max; f=f/f₀ - нормированное значение частоты выходных импульсов РЭ 3-1, 3-2, …, 3-n, отнесенной к несущей частоте f₀=1/(4b Т_И) при нулевом значении сигнала на входе АЦП.Amplitude

and modulation

the characteristics of the integrating Converter "Analog-Digital-Analog" in relative units are shown in figa, b, respectively. Here

- the normalized value of the input signal related to the maximum amplitude at the output of the transducer A _max = A · N _max ; f = f / f ₀ is the normalized value of the frequency of the output pulses RE 3-1, 3-2, ..., 3-n, referred to the carrier frequency f ₀ = 1 / (4b Т _И ) at a zero value of the signal at the ADC input.

Figure 7 shows a fragment of a circuit diagram of a 4-bit converter (without a code subtractor). The functional purpose of the elements of the circuit diagram, which does not require additional explanations, is also indicated there.

On Fig shows the waveform of the Converter. Fig-a corresponds to the case of a zero value of the input signal. With a harmonic input (Fig. 8b), the output signal of the DAC has the form of a stepwise approximated sine wave. The distortion of the shape of the “steps” is caused by the properties of a digital oscilloscope.

Thus, the introduction into the circuit of additional adders 6-1-6-n, proportional links 4-1 - 4-n, keys 7-1 - 7-n and a device for subtracting codes 8 with a source of digital code 9 allows implementing the integrating ADC method and DAC with feedback loop, which greatly improves the accuracy of the converter as a whole.

The considered converter is supposed to be offered to manufacturers of integrated circuits for its serial production on an integrated basis.

Claims (1)

Integrating Converter "Analog-Digital-Analog", containing sequentially connected input signal source, the first adder, integrator and the first relay element from the group containing the nth number of relay elements, and n = 1, 2, 3 ... integer, second adder the output of which is connected to the analog output of the device and connected to the second input of the first adder, digital outputs of the device, characterized in that the nth number of proportional links, n-1 additional adders, n-th number of key elements, are input into it a reference digital code and a code subtraction device, wherein the output of each relay element through a corresponding proportional link is connected to the corresponding input of the second adder, and also connected to the input of the corresponding key element, the output of each key element is connected to the first group of inputs of the code subtractor, the second group of inputs of which connected to the corresponding outputs of the source of the reference digital code, the outputs of the device for subtracting codes are connected to the corresponding digital outputs the Analog-Digital-Analog converter, wherein the output of each of the additional adders is connected to the input of each relay element, starting from the second, the first input of each of the additional adders is connected to the output of the previous of the n-th number of proportional links, the second input of the first additional adder connected to the output of the integrator, and the second input of each of the subsequent additional adders connected to the output of the previous additional adder.

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