RU2464702C1 - Ramp-type pulse-number analogue-to-digital converter - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: device has a voltage-to-pulse frequency converter, two AND logic elements, a binary counter, a memory register, a code comparator, a clock-pulse generator, a digital inverter and a delay element.

EFFECT: high noise immunity of the device.

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Description

The invention relates to the field of computer technology and can be used in automation systems to convert an analog signal into a digital code.

Known analog-to-digital converter (ADC) with bitwise balancing (Opadchiy Yu.F., Gludkin OP, Gurov AI Analog and digital electronics (full course): a textbook for high schools. Gludkina. - M .: Hot line. - Telecom, 2007, - 768 p.), Containing a memory register and a register of successive approximations, an analog comparator, a digital-to-analog converter, logic elements, a clock generator, an input signal source.

The known ADC has low noise immunity, which requires the inclusion of a smoothing filter at the input, limiting the ADC bandwidth.

A multi-zone deployment converter is known which contains an input signal source, a first adder and an integrator, the output of which is connected to the inputs of a group of an odd number of relay elements, the outputs of which are connected to the inputs of the second adder, the output of which is connected to the output of the device and to the second input of the first adder ( SU 1183988 USSR, G06G 7/12. Deployment amplifier / Tsytovich LI - No. 3734334/24, announced April 27, 84. Publish. 07.10.85. Bull. No. 37).

With certain circuit additions, this integrating device can operate in ADC mode, however its bandwidth will be determined not only by the frequency, but also by the amplitude of the converted signal.

Closest to the proposed technical solution is an ADC of a pulse-type type (Volovich GI Circuitry of analog and analog-digital electronic devices. - M .: Publishing House "Dodeka-XXI", 2005, - 459 p.), Containing series-connected a voltage to pulse frequency converter (VLF), a binary counter, a memory register, and a clock pulse generator connected to the R-input of the binary counter and to the C-input of the memory register.

The disadvantage of the prototype device is the asynchronous rewriting of data from a binary counter to the memory register, when rewriting clock pulses are generated at arbitrary time periods and are determined by the parameters of the clock generator. This mode of operation of the ADC leads to the formation of “extra” overwriting cycles that occur when the codes are equal in the binary counter and the memory register.

At the same time, it is obvious that redundant switching in digital circuits leads to a decrease not only in their noise immunity, but also in the noise immunity of neighboring functional nodes, since in the process of generating a pulse signal, pulse interference always occurs, for example, through power supply circuits.

Thus, the prototype device is characterized by low noise immunity.

The invention is based on a technical problem aimed at improving the noise immunity of a number-pulse ADC by optimizing the number of cycles of rewriting data from a binary counter to a memory register.

The indicated technical problem is solved in that an integrating number-pulse analog-to-digital converter containing a voltage to pulse frequency converter, the input of which is the "input" of the device, a clock pulse generator, and also a binary counter and a memory register connected in series, the outputs of which are digital According to the invention, a “delay” element, “NOT” logic element and “2I” logic element, as well as sequentially including data of the code comparison device and the second logic element “2I”, the output of which is connected to the C-input of the memory register, the first group of inputs of the code comparison device connected to the outputs of the binary counter, and the second group of inputs of the code comparison device connected to the outputs of the memory register, generator output clock pulses is simultaneously connected to the second input of the second logic element “2I”, the input of the logic element “NOT” and the input of the delay element, the output of which is connected to the R-input of the binary counter, the output zovatelya voltage pulse frequency is connected to the second input of "2i" the first NAND gate, whose output is connected to the C input of the binary counter.

As a result, the stated technical problem is achieved due to the fact that a delay element, a logic element “NOT” and a first logic element “2I”, as well as a device for comparing codes and a second logic element “2I” are sequentially included in the device. The delay element eliminates the simultaneous installation in the binary counter of zero initial conditions and the recording of data in the memory register due to their different transient times. The logical element "Not" and the first logical element "2I" prevent the passage of pulses from the output of the voltage converter to the pulse frequency to the counting C-input of the binary counter at the time moments of the formation of clock pulses from the output of the clock generator. Data is transferred from the counter to the memory register only if their contents are not equal, which is achieved by introducing a code comparison device and the second logical element 2I. As a result, the number of inclusions of elements that overwrite data in the ADC is optimized, and its noise immunity increases.

Thus, the proposed device has a high noise immunity.

The invention is illustrated by drawings:

Figure 1 - functional diagram of the proposed device;

Figure 2 is an example implementation of a code comparison device;

Figure 3 - characteristic "input-output" of the IF.

The structure of the integrating number-pulse analog-to-digital converter (Fig. 1) includes sequentially connected IFs 1, the first logic element 2 of the 2I function, binary counter 3, memory register 4, code comparison device (USC) 5 and the second logic element 6 function "2I", the output of which is connected to the C-input of the memory register 4, as well as a clock pulse generator 7, a logic element 8 of the function "Not" and a delay element 9, the output of which is connected to the R-input of the binary counter 3. Moreover, the second group of inputs 5 code comparison devices ene to the outputs of the binary counter 3, a memory output register 4 is a digital "output" device. The output of the clock 7 is simultaneously connected to the second input of the second logic element 6 of the "2I" function, the input of the logic element 8 of the function "NOT" and the input of the delay element 9, the output of which is connected to the R-input of the binary counter 3. The output of the logic element 8 of the function " NOT "connected to the second input of the first logic element 2 of the function" 2I ", the input of the IF 1 is the" input "of the device.

USK 5 (figure 2), for example, contains a group of logic elements 10 of the “Equivalence” function, the outputs of which are connected to the inputs of the logic element 11 of the function “nI-NOT”, the output of which is the output of USK 5. The first inputs A0, A1, ..., Ai of the group of logic elements 10 of the "Equivalence" function are connected to the corresponding outputs of the memory register 4, and the second inputs B0, B1, ..., Bi of the group of logic elements 10 of the function "Equivalence" are connected to the corresponding outputs of the binary counter 3.

ADC elements have the following characteristics.

ELF 1 is reversible and converts the analog input signal to a pulse frequency, which increases linearly with increasing amplitude of the input action (figure 3). The contour of the formation of a significant discharge on the structure of the ADC (figure 1) is not shown in order to simplify it.

Logic elements 2, 6 of the “2I” function generate a logical “1” signal at the output only if the input signals have a logical “1” level.

Binary counter 3 is a summing counter and increases its contents by a unit of the least significant digit synchronously with the leading edge of the pulse at the C input. When the trailing edge of the pulse acts on the R-input, counter 3 goes into the “zero” state in all digits.

The memory register 4 records data from its D-inputs synchronously with the leading edge of the pulse at the C-input.

USK 5 switches to the logical “1” state in case of inequality of codes coming from the outputs of binary counter 3 and memory register 4.

The clock generator 7 generates high-frequency pulses of short duration with a stable frequency for overwriting data from the binary counter 3 in the memory register 4.

The signal level at the output of the logic element 8 of the function "NOT" is opposite to the level of the input signal.

The delay element 9 shifts in time the synchronization pulse from the output of the clock pulse generator 7 by the value of "τ", leaving its amplitude and duration unchanged.

Logical elements "Equivalence" of group 10 (figure 2) form the output signal of a logical "1" with the coincidence of the level of bits Ai, Bi of the compared codes.

The logic element 11 of the function "NAND" is switched to the state of the logical "1" provided that there is a "1" at all its inputs. If at least one of the inputs of the logic element 11 forms a logical "0", the output signal takes the state "1".

The principle of operation of the device is as follows.

IF 1 converts the input analog signal to a frequency of pulses that are fed to the C-input of the binary counter 3 through logic element 2 of the 2I function. Logic element 2 of the 2I function is opened by the logic 1 signal from the output of logical element 8 of the Not function since there is no signal at the output of the clock 7.

In case of inequality of the codes from the outputs of the binary counter 3 and the memory register 4, USK 5 is in the logical “1” state, but this “1” does not go to the C-input of the memory register 4 due to the zero value of the signal at the output of the clock generator 7, when where the logical element 6 of the function "2I" forms a signal of a logical "0".

At the time of the formation of the clock pulse from the output of the clock 7, the logic element 2 of the “2I” function is closed by the signal of the logic “0” from the output of the logic element 8 of the “NOT” function and the logic element 6 of the function “2И” is opened, resulting in data from the binary counter 3 are copied to memory register 4. As soon as the contents of the binary counter 3 and memory register 4 become equal, USK 5 switches to the logical “0” state.

With a time delay of “τ”, the binary counter 3 “resets”, and the counting process is repeated. At the same time, data is written to the memory register 4 only if the contents of the subsequent clock of converting the input signal into code differs from the contents of memory register 4 for the previous clock cycle of the ADC.

Thus, by optimizing the cycles of rewriting data from the binary counter 3 to the memory register 4, the noise immunity of the ADC is increased.

Industrial applicability.

The considered device is supposed to be used in the temperature controller of the drying chamber of the electric shop at Chelyabinsk Pipe-Rolling Plant OJSC.

Claims (1)

An integrating number-pulse analog-to-digital converter, comprising a voltage to pulse frequency converter, the input of which is the “input” of the device, a clock generator, as well as sequentially connected binary counter and memory register, the outputs of which are the digital “output” of the device, characterized in that a delay element, a logic element “NOT” and a first logic element “2I”, a series-connected device for comparing codes and a second logic element 2I, the output of which is connected to the C-input of the memory register, the first group of inputs of the code comparison device connected to the outputs of the binary counter, and the second group of inputs of the code comparison device connected to the outputs of the memory register, the output of the clock generator is simultaneously connected to the second the input of the second logical element "2I", the input of the logical element "NOT" and the input of the delay element, the output of which is connected to the R-input of the binary counter, the output of the voltage converter to the pulse frequency with connected to the second input of the first logical element "2I", the output of which is connected to the C-input of the binary counter.

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