US2933722A

US2933722A - Phase shift-to-non-numeric signal train converter

Info

Publication number: US2933722A
Application number: US676670A
Authority: US
Inventors: Steinman Leon Harold
Original assignee: Litton Industries of California
Current assignee: Litton Industries of California
Priority date: 1957-08-06
Filing date: 1957-08-06
Publication date: 1960-04-19
Anticipated expiration: 1977-04-19

Description

2 sheets-smet 1 I I I I I I I I I I I I I I I I I l I I I I I I I I I I I I I I I I I I I I I \\-I k\.\ N s L. H. STEINMAN PHASE SHIFT-TO-NON-NUMERIC SIGNAL TRAIN CONVERTER April 19, 1960 Filed Aug. 6, 1957 April 19, 1960 L. H. sTElNMAN 2,933,722

PHASE SHIFT-TO-NON-NUMERIC SIGNAL TRAIN CONVERTER United States Patent PHASE SHIFT-TO-NN-NUMERIC SIGNAL TRAIN CONVERTER Leon Harold Steinman Los Angeles Calif sd @naar te Litton Industries of alifornia, Bei'ei'ly Hiilhs,D alif.

Application August 6, 1957, Serial No. 676,670

11 Claims. (Cl. 340-347) I The invention relates to a phase sliifttoiion-numeric signal train converter and more particularly to a phase shift-to-difunction converter for converting a phase shifted signal to a difunction signal train wherein the value of tne signal train is proportional to the phase shift of the phase shifted signal.

ln contrast to conventional digital computing machines whichhoperate upon binary or binray-coded signals representing weighted binary digits, there is a class of com puters which perform operations upon and in response to non-numeric signal trains. One type of non-numeric signal train which is becoming more and more widely used is a difunction signal train which comprises a sequence of bivalued signals, each signal of the train representing either a rst number N1 or a second number N2. For ease of description, difunction signal trains only will be hereinafter discussed in connection with the invention. However, it is to be specifically understood that the principles o-f the invention apply equally well to all types of non-nurneric signal trains.

A difunction signal train or other non-numeric signal train is readily distinguishable from a conventional binary or bnarycoded signal train. Whereas in a binary or binary-coded signal train, each signal of the train has a Weight or significance dependent upon its position in the signal train in accordance with a pre-assigned number code; in contrast, each equi-valued signal of the difunction signal train has equal significance wherever it may appear. Accordingly, a difunction signalY train may be termed a nonnurnerical representation of the quantity which the train represents, since the signals are not weighted according to any numbering system, or in other words, have no radix as this term is customarily employed.

lt is conducive to simplicity in explanation of the difunction converter of theV present invention to assign at the outset convenient algebraic numbers to the signals of a difunction signal train. Accordingly, it is assumed hereinafter that the signals of a difunction train are assigned a set of values, where the values are -l-l and 1, since both positive and negative information may be conveniently represented by such a signal train. Gener ally, as hereinbefore stated, the signals of a difunction train may be considered as having a set of values N1 and N2.

Some examples of the extremely useful application of difunction signals trains in the solution of mathematical operations and in the eld of automatic controls are described and illustrated in several copending U5. patent applications, as for example, in copending US. patent application, Serial No. 388,780, for Electronic Digital Differential Analyzer, by Floyd G. Steele, tiled October 28, 1953, there is described a digital differential analyzer` employing difunction signal trains for communicating between the integrators contained therein. Similarly, copending U.S. patent application, Serial No. 311,609, for Computer and Indicator System, by Floyd G. Steele, ,tiled September 26, 1952, and issued August 4, 1959, as

U.S.atent No. 2,89,040, discloses the application of difunction representation to the field of process control and also discloses electronic computing circuits which operate directly to perform mathematical operations by combining difunction signals.

ln order to fully realize the potential of difunction computing techniques, especially as utilized in applications where it is necessary to accurately sense the rotated position of a shaft, there is a need for conversion devices which can transform a phase shifted signal, wherein the magnitude of the phase shift represents the position of the shaft, to an equivalent difunction signal train. This is true since resolvers or other similar phase shifting de vices are utilized to sense the rotated position of a shaft. These devices are utilized almost exclusively for this purpose because they are extremely accurate and reliable and have an unusually long operating life. Therefore, if difunction computing techniques are to be utilized in applications concerned with rotated shaft positions, it is necessary that the phase shifted output of the resolver or similar devices be converted to a difunction signal train.

T he present invention provides a phase shift to difunction converter whereby a phase shifted signal is converted to a pulse width modulated signal and then directly to a difunction signal train. lt should be noted that while it would appear necessary to convert the pulse width modulated signal to an intermediate DC. signal (direct current) before the pulse Width modulated signal can be converted to a difunction signal train, this is unnecessary in the phase shift-toadifunction converter of the present invention. rtherefore, the time lag or delay associated with a filter used in D C. conversion is not required. The present invention, therefor provides a conversion system which is suitable for use with high speed computers since a rapid rate of conversion can be achieved and maintained by a converter mechanized invaccordance with the teachings of the invention. j

In the preferred embodiment of the invention a phase shifted. signal and a reference signal are applied to a pulse width modulator which is responsive to the applied signals to generate a pulse width modulated signal where in the pulse width in each cycle of the signal is proportional to the phase shift of the phase shifted signal. According to the invention, each pulse of the pulse Width signal is represented as a high level positive potential pulse which is bounded at both beginning and end by` a low level negative potential. rlhe pulse width modulated signal is applied to a difunction converter which is responsive to the pulse width signal to generate' a difunction signal train wherein the value of the difunction train is proportional to the average value of the pulse width modulated signal.

Any one of a number of pulse width modulators known to the art can be utilized as the pulse width modulator. The pulse vw'dth modulated signal is applied to a difunction converter which integrates the pulse width signal in an integrator to form an integrated current signal from Which is subtracted a standard signal, which is developed by a standard signal source, the standard signal having an amplitude representative of the difunction signal generated by a sensing element. The integrated current signal is applied to the sensing element which isresponsive thereto to gene-rate a -i-l difunction signal if the integrated current signal is greater than a predetermined reference level and a l difunction signal if the integratedcurrent signal is less than the predetermined value. In this manner the converter will generate a difunction signal train whose value is proportional to the average value of the pulse width signal.

ln a second embodiment of the present invention a pulse width modulator and a difunction generator co;-

operate in such a manner that the difunction generator generates a difunction signal train without the necessity of a standard signal and thereby without a standard signal source. In this embodiment of the invention the pulse width modulated signal is generated in response to a phase shifted signal and a reference signal when the value of the inegrated current signal has a first predetermined relationship with a predetermined reference level and is responsive to the reference signal and the inverted phase shifted signal when the value of the 1ntegrated current signal has a second predetermined 1e lationship to the predetermined reference level. It should be herein mentioned, however, that the second embodiment Aof the invention can further be mechanized to be responsive Vto the phase shifted signal and the reference signalwhen the integrated current signal has Va second predetermined relationship to the predetermined reference level. A difunction generator vresponsive to the rpulse width signal to generate a ydifunction signal Ytrain Aintegrates the pulse width signal in an integrator which generates the integrated current signal. 'The integrated current `signal is sampled by a sensing element which generates a +1 difunction signal when the integrated current signal value has the first predetermined relationship with the predetermined reference level and generates a l difunction signal when the value of the integrated current signal has the second predetermined relationship with the predetermined reference level. The resultant difunction signal train has a value which is proportional to the average value of the pulse width modulated signal.

It is, therefore, an object of the present invention to provide a phase shift to non-numeric converter wherein a phase shifted signal is converted to pulse width modulated signal and then directly to a difunction signal train.

A further object of the present invention is to provide a phase shift-to-non-numeric converter wherein a phase shifted signal may be converted to a difunction .signal train at a high rate of conversion.

Still another object of the present invention is to provide a phase shift-to-difunction converter wherein the value of the difunction signal train is proportional to the average value of the pulse width modulated signal.

It is also an object of the present invention to provide a phase shiftto-non-numeric converter that is responsive to a phase shifted signal and a reference signal when an integrated current signal has a first predetermined relationship with a predetermined reference level and is responsive to one of the two input signals and the inverted signal of the other input signal when the integrated cur- .rent signal has a second predetermined relationship with the predetermined reference level.

The novel featureswhich are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages thereof, will be better understood from the following description considered in connection with the accompanying drawings in which several embodiments of the invention are illustrated by way off example. It is to be expressly understood, however, that the drawings ar'e for' the purpose of illustration and description only, and not intended as a definition of the limits of the invention.

Fig. l is a partly block and partly circuit diagram of -the basic elements of the preferred embodiment of the generated by the invention plotted against a common time axis.

With reference ,now to the drawings, wherein ,like or corresponding parts are designated with like reference numerals throughout the several figures, there is shown in Fig. l a partially block and partially circuit diagram of a preferred embodiment of a phase shift-to-di function converter of the invention. The converter is operable in response to an applied phase shifted signal Sp and an applied reference signal Rp to generate a difunction signal train wherein the value (average value) of the difuncton signal train is proportional to the shift relative to the reference of the phase shifted signal.

As shown in Fig. l, signal source 11 generates the phase shifted signal and the reference signal which are applied over correspondingly designated conductors 8 and En, respectively, to a pulse width modulator 15. (For purposes of facilitating and clarifying description, each conductor will be hereinafter' similarly designated in terms of the signal applied over the conductor.) Pulse width modulator l5 is responsive to the applied Sp and Rp signals to generate a pulse width modulated signal Q wherein the pulse width in each cycle of the pulse width modulated signal is proportional to the phase of the phase shifted signal with respect to the reference signal. The pulse width modulated signal Q is applied to a difunction generator 17, which is responsive tothe applied signal Q to generate the difunction signal train at a terminal 19 wherein the value of the difunction signal train is proportional to the average value of the pulse width signal Q.

Referring now with particularity to the preferred embodiment of the invention shown in Fig. 1, signal source 11 can be any one of a number of well known conventional sensing devices whereby sensed information is conveyed by means of a phase shift. For example, signal source 11 could be an AC resolver attached to a rotating shaft wherein the rotated position of the shaft is sensed as the magnitude of the phase shift of the resolver output signal.

As shown in Fig. l, the phase shifted signal SI, is applied to the pulse width modulator at a square ampliiier 21 and the reference signal Rp is applied to the pulse width modulator at a squaring amplifier 23. Squaring amplifier 21 squares the phase shifted signal which is then applied to a differentiating circuit 25, while squaring amplifier 23 squares the reference signal which is then applied to a differentiating circuit 27. Differentiating circuit 25 generates a negative pulse actuating signal As whenever the phase shifted signal goes from a high to a low voltage level while differentiating circuit 27 generates a negative pulse lactuating signal Ar whenever the reference signal goes from a high to a low voltage level. Actuating signal AS and actuating signal Ar are then applied to a bistable flip-flop Q, which is responsive to the actuating signals to generate the pulse width moduiated signal, the pulse width modulated signal being clamped accurately at high and low voltage levels E2 and El by a clamping circuit 32. Since the converter, as shown in Fig.1, is for convenience referenced to ground potential, the E2 and El voltages will be equal voltages above and below ground potential, respectively.

Continuing with a more thorough description of the pulse width modulator, the squaring amplifiers 21 and 2,3 to which the phase shifted signal and reference signal are applied, respectively, are the same in both function and structure. Both squaring amplifiers generate a waveform tending to conform to the general shape of the applied rwaveform but having vertical sides, a flat top and a flat bottom or, as commonly designated yin the art, they have a square waveform. As hereinbefore mentioned, the converter is referenced to ground potential so that for A.C. input signals which alternately go from a positive high level to a negative low level, the squared signals will have a flat top ata positive voltage and a at bottom at some negative voltage.

Numerous circuits are known to the art whereby a suitable squaring amplifier can be mechanized. For example, the mechanization of a suitable squaring amplifier is described in detail in copending U.S. patent application, Serial No. 676,654-, for Pulse Width Modulator, by Daniel L. Curtis, tiled August 6,-1957, and issued November 17, 1959, as U.S. Patent No. 2,913,675. The squared phase shifted signal and reference signal from squaring

amplifiers

21 and 23 are applied to differentiating circuits 25 and 2.7, respectively.

The squared phase shifted signal is applied to difierentiating circuit 25 at one side'of a capacitor 3S, while the other side of capacitor 35 is coupled to a terminal 37. Terminal 37 is coupled through resistor 39 to ground and to the cathode of a diode 41, while the anode of diode 41 is coupled to actuating conductor As. In operation, when the squared phase shifted signal is at its high voltage level, one side of capacitor 35 becomes charged to the positive high level. Therefore, when the squared phase shifted signal then goes to its low negative voltage level, capacitor 3S discharges rapidly, causing a negative pulse to appear on actuating conductor As. When the squared phase shifted signal is at its low negative voltage, one side of capacitor 35 charges to the negative low level and when the squared phase shifted signal again changes to its high voltage level, the capacitor discharges rapidly and a positive pulse would be formed on actuating conductor As but for diode 41, which will be back biased when the positive pulse is applied to its cathode electrode. Therefore, diode 41 will not pass the positive pulse to actuating conductor AS. Actuating signal As is, therefore, generated whenever the phase shifted signal goes from its high level to its low level. It is to be specifically noted that the present invention is not limited to formation of the actuating signal Whenever the input signal to differentiating circuits 25 goes from a high to a low level, but includes an embodiment wherein the actuating signal can be formed when the input signal goes from a low to a high level. This embodiment can be mechanized, for example, by reversing diode 41.

Diferentiating circuit 27 is identical in operation and structure to differentiating circuit 25 except the applied signal is the reference signal. Therefore, actuating signal A, is generated whenever the squared reference signal goes from its high level to a low level. Actuating signals As and Ar, as hereinbefore mentioned, are applied over actuating conductors A5 and Ar, respectively, to the bistable fiip-vop Q.

Flip-Hop Q has a pair of inputs hereinafter designated the S input and Z input, respectively. Flip-flop Q produces an output signal Q having a first positive voltage level and a second negative voltage level, both levels being equal in magnitude but opposite in polarity in accordance with the state of the flip-lliop, output signal Q comprising the pulse width modulated signal. In operation tilip-op Q is responsive to the application of an input signal to its S-input for being set to its set state and to the application of an input signal to its Z input for being set to its zero state. When flip-flop Q is in its set state, output signal Q will be at its first positive level. Conversely, when flip-flop Q is in its zero" state, signal Q will be at its second negative level. The detailed structure for one suitable form of flip-flop can be found on page 13 of the March 1955 issue of Transactions of The Institute of Radio Engineers Professional Group on Electronic Computers in an article entitled Transistor Circuitry for Digital Computers, by L. C. Wanlass.

As shown in Fig. l, actuating signal As is applied to theS input of filip-Hop Q and actuating signal A, is applied to the Z input of flip-flop Q. Therefore, the generation of actuating pulse A, will cause signal Q to go to its iirst level while the generation of actuating pulse Ar will cause signal Q to go to its second level.

Since actuating pulses As and A, will be generated only when the phase shifted signal and the reference signal change voltage level from a high level to a low level, and since the time lapse between such a change in level in the phase shifted signal with respect to such a change in the reference signal is proportional to the phase shift, the width of each pulse of the pulse width signal will be proportional to the phase shift of the corresponding cycle of the phase shifted and reference signals.

As shown in Fig. l, pulse width signal Q is applied to clamping circuit 32 which in response thereto clamps the first level of signal Q at an upper limit voltage E2 and the second level of signal Q at a negative voltage E1. As hereinbefore mentioned, voltage El is equal and opposite in polarity to voltage E2. As shown in Fig. 1, signal Q is applied to the clamping circuit at a terminal 34, the terminal being coupled further to the cathode of a diode 36 which clamps signal Q at voltage E2 since a source of voltage E2 is applied to the an'ode of diode 36. Terminal 34 is also coupled to the cathode of a diode 38 which clamps signal Q at voltage E1 since a source of voltage El is applied to the anode of diode 38. As hercinbefore mentioned, the pulse width modulated signal Q is then applied to the difunction converter which generates a difunction signal on terminal 19, wherein the value of the difunction train is proportional to the average value of the pulse width modulated signal.

Referring now with particularity to difunction converter 17, shown in Fig. l, the converter includes four basic elements, namely: an integrator 33 which integrates the applied signal Q with respect to time; a sensing element coupled to the integrator by a conductor 45 and operative to sample during each difunction signal period the integral developed and for generating a +1 valued difunction signal Whenever the integral exceeds a predetermined referencelevel and a -l valued difunction signal whenever the integral is less than the reference level; a standard signal source 87 coupled to the sensing element by a conductor 47 and operative in response to each difunction signal generated for developing a standard feedback signal Si representative of the value of the difunction signal generated, the standard signal being applied back to integrator 33 in such a manner as to subtract the standard signal from the integral developed therein; and a timing signal source 39 for generating a timing signal tp, which is applied over conductor tp to sensing element 8S. Timing signal tp is a periodically recurring clock or timing signal which synchronizes the operation of the converter to delimit or mark-off successive difunction signal periods.

As shown in Fig. l, integrator 33 includes a capacitor 5l and a charging resistor 43 in series therewith having values such that the combination presents a conventional RC integrator circuit to the applied pulse width signal Q. Resistor 43 functions to produce a scaled current proportional to the voltage of the applied pulse width signal Q, this current being integrated by capacitor 41. ITherefore, in actuality the current flowing through resistor 43 is summed along with the standard signal, applied over conductor Sf to capacitor 81, the resultant difference current being integrated by capacitor 81. The integrated signal formed in capacitor 81 is then applied over conductor 4S to sensing element S5 which will generate the -1-1 difunction signal or -1 difunction signal, depending upon whether the integrated signal is greater or smaller than the predetermined reference level.

lf the integrated current signal is greater than the predetermined reference level, the sensing element will generate the +1 difunction signal. Standard signal source 87 will then generate the scaled standard signal of -1 value that Will be summed in capacitor 81, thereby reducing the value of the integrated current signal by 1. If the integrated current signal is less than the predetermined reference level, the sensing element will geni erate the -l difunction signal and a standard signal S; of -l-l value will be generated by the standard signal source thereby increasing the value of the integrated current -signal by l.

in this manner the converter will generate a difunction signal train at terminal 19 wherein the Value of the difunction train will be proportional to the average value of the pulse width signal Q. For example, a phase shift of 180 will produce the pulse width signal with a pulse Widti of 1/2 a cycle which in turn will generate a difunction signal train of alternate -l-l and -l difunctien to give a value of zero. A more detailed discussion of the structure and operation of the elements of difunction generator 17 will not be given herein since an excellent detailed discussion of the operation and structure of these elements may be found in copending US. patent application, Serial No. 592,963, filed June 21, 1956, for Apparatus for Analog-to-Difunctiou Conversion, by Daniel L. Curtis, vissued May 5, Y1959, as U.S. Patent No. 2,885,663.

lt should be noted that in the preferred embodiment of the invention the period of the phase shifted and reference input signals and the period of timing signals tp should be the same. However, no relationship need exist between the two periods if a D.C. (direct current) filter is interposed between the pulse width modulator and the difunction generator to convert pulse width modulated signal Q to a D.C. signal.

Referring now to Fig. 2, there is shown a second embodiment of a phase shift to difunction converter of the present invention wherein pulse width modulator and difunetion converter 17 have common or shared elements. The difunction converter and the pulse width modulator thereby are so coordinated that the converter can be mechanized Without a standard feedback signal and thereby without a standard signal source. According to the basic theory of operation of the invention, pulse width modulator 15 is responsive in a first mode of operation to phase shifted signal Sp and reference signal Rp to generate pulse Width modulated signal Q wherein the integrated increment in value of each cycle of pulse width modulated signal Q is equal to Y+l, where Y is the value of the difunction signal train. in a second mode of operation, pulse width modulator 15 is responsive to phase shifted signal Sp and reference signal Rp to generate pulse Width modulated signal Q wherein the increment in value of each cycle of pulse modulated signal Q is equal to Y-l. The pulse Width modulator is operable in the first mode of operation when a -l difunction signal is being generated and operable in the second mode of operation when a -l-l difunction signal is being generated. In this manner the 'standard feedback signal is derived directly and is included within pulse width modulated signal Q.

As shown in Fig. 2, phase shifted signal Sp and reference signal Rp are generated by phase shifted and reference signal source 11 and are applied over conductors Sp and Rp to pulse width modulator 1S. Pulse width modulator 15 is responsive to the two applied Sp and Rp input signals to generate a pulse width modulated signal Q wherein the pulse width of each cycle of the pulse width modulated signal is proportional to the phase of the phase shifted signal. The pulse width signal Q is applied to difuuction generator 17, which is responsive to the applied signal Q to generate the difunction signal train at terminal 19, wherein the value of the difunction signal trr-L'n is proportional to the average value of the pulse width signal Q.

Referring now with particularity to the second embodiment of the invention shown in Fig. 2, signal source 11 is shown as an A.C. resolver circuit. As hereinbefore mentioned, the invention is specifically not limited to a resolver source, but any one of many sources of phase shifted signal well known in the art may be utilized. The resolver circuit comprises three major components: a conventional resolver with a stator and rotor element generally designated 51, a 90 phase shifter 53, and a reference-signal generator 55. Reference-"signal generator 55 generates reference signal Rp which is applied to one stator winding `of the resolver and to the phase shifter which generates a signal corresponding to the reference signal but with a 90 phase shift, this signal then being applied to a second stator winding. The rotor element, which is coupled to a shaft 52, is responsive to the activated stator windings, to generate phase shifted signal Sp, the magnitude of the phase shift depending upon the angular position of the rotor coil. The phase shifted signal and reference signal generated by signal source 11 are applied over conductors Sp and Rp, respectively, to pulse width modulator 15.

As shown in Fig. 2, pulse width modulator 15 includes eight basic elements, namely: -a squaring amplifier 21 which squares the applied phaseY shifted signal; an inverter 57 which is responsive to the applied phase -shifted signal to generate an inverted phase shiftedsignal Sp1; a selecting gate 59 responsive to the applied Sp and ,Sp1 signals and a pair of feedback signals -f and f, to be hereinafter discussed, to generate a selection signal S corresponding either to the Sp or Sp1 signals; an actuating gate 69 which is responsive to a clock pulse signal C1, from a clock pulse signal source not shown and the selection signal to generate an actuating signal As; a squaring amplifier Z3 which squares the applied reference signal Rp; an actuating gate 71 which is responsive to clock pulse signal C1 and the reference signal to generate an actuating signal A1.; a bistable flip-flop Q to whichlis applied the actuating signals Ar and As, the dip-flop being responsive thereto for generating the pulse width modulated signal Q; and a clamping circuit 32 responsive to the application of pulse width signal Q to accurately clamp signal Q at its high and low voltage levels E2 and E1, respectively.

Continuing with a. more thorough description of pulse width modulator 15, squaring

amplifiers

21 and 23 generate squared signals alternately going from a positive high level to a negative low level corresponding to the alternations of their respective input signals, each output `signal having a flat top at the positive level and a at bottom at the negative level, as shown in Figs. 3a and 3b. Inverter 57 is a conventional inverting amplier well known in the art and is responsive to the applied squared phase shifted signal Sp to generate the inverted signal Sp1 which corresponds tothe squared phase shifted signal with an additional 7 phase shift.

As shown in Fig. 2, selecting gate 59 is responsive to bilevel feedback signals f and y?, to generate selectionsignal S corresponding to either squared phase shifted signal Sp or squared inverted phase shifted signal Sp1. B -ilevel feedback signals and f, each have a high and low voltage level, the signals being complementary. Inverted signal Sp1 is applied to selecting gate 59 at one input of an and gate 63, while squared phase shifted signal Sp is applied to the selecting gate at one input of an and gate 65. Feedback signal f is applied to a second input of and gate 63 while feedback signal )Tis applied to a second input of gate 65. (As shown in Fig. 2, the and gates are depicted by hoods with a dot therein.) An and gateas is well known in the art, is operable so that a rst level output signal is generated when all the input signals are first level signals and conversely generates a second level signal if any one or more of the input signals are second level signals. More specifically, as utilized in the invention, a high level signal is generated when all the input signals are high level signals and conversely a lov.r level signal is generated when any one or more of the input signals are at the low level.

Therefore, gate 63 generates a bilevel signal correspending to the inverted signal Sp1 when feedback signal f is at its high level, -while gate 65 will not generate a signal corresponding to squared Aphase shifted Vsignal Sl,

since feedback signal will be at a low level. When feedback signal f is Aat :its low level, :gate `63r-wil1 ,not

generate a signal corresponding to the invertedsignal, but gate 65 will generate a signal corresponding to vsquared phase shifted signal.

The output of

gates

63 and 65 then are applied to an or gate 67 which generates selection signal S which Will `correspond to whichever input signal is at its high level. k(As shown in Fig. 2, an or gate is represented by a hood with a plus sign therein.) An or gate is well known in the art so that one skilled therein would be -acquainted with a number of ways to mechanize an for gate as well as the hereinbefore mentioned and gates. Selection signal S of or gate 67 then is applied to and gate 69 along with clock pulse signal C1. Clock pulse signal C1 comprises a series of periodic negative pulses, whose amplitude is somewhat less than the low level of selections signal S generated by gate 67. It is clear gate 69 will generate a negative actuating pulse signal As whenever selection signal S from gate 67 is at a high level and will generate no such pulses when the bilevel signal is atgits low level.

Directing attention again to squaring amplifier 23, the squared reference signal output of the squaring amplifier is applied to an and gate 71 which is identical in structure and function to the hereinbefore mentioned and gates. Clock pulse signal C1 is also applied to gate 71 so that gate 71 generates negative actuating pulses (which form actuating signal Ar) whenever squared reference lsignal Rp is at a high level, as hereinbefore described `in connection` with gate 69. Actuating signals Ar" and AS are applied after generationover conductors Ar and Agrespectively to the S and Z inputs Yof bistable prop Q f 1 y Flip-flop Q is responsive to the applied Ar and As signals to generate the pulse width modulated signal Q, as hereinbefore described in connection with the preferred embodiment of the invention. The pulse width modulated signal is then applied over conductor Q to clamping circuit 32 which in response thereto, as hereinbefore explained, clamps the first level of signal Q at upper limit voltage E2 and the second level of signal Q at negative voltage El.

Directing attention now to the overall operation of pulse width modulator 15, there is shown in Figs. 3a,

.3b 3g a series of waveforms, plotted on a common ,time axis, shown as they would be generated by pulse width modulator when the phase shift rof the phase shifted signal Sp is 90. In Fig. 3a there is shown reference signal input Rp and corresponding squared reference output signal Rp of squaring amplifier 23, shown byv and solid lines, respectively. There is shown in Fig. 3c

inverted squared phase shifted output signal Sp1 of inverter 57, and there is shown in Figs.,3d and 3e the waveforms of pulse width modulated signal Q when the pulse modulator is operating in the first and second modes of operation, respectively, and selection signal S of gate 59 is phase shifted signalSp and inverted phase shifted signal Sp1, respectively.

Directing attention to Fig. 3d, the pulse width signal is at its low level El during the first quarter of a period since the reference signal is at its high level so that the flip-flop will be set by actuating pulses Ar, thereby generating a low level signal. During the next quarter period both the phase shifted and the reference signals are at their high levels so that flip-flop Q will change its stateevery clocking period in response to actuating pulses Ar and As. This changing of states is due to the fact a conventional 'flip-flop will change its state when concurrently pulsed at both its inputs, thereby causing sig- .nal Q to changelevels at a frequency equal to the clocking pulse frequency, as shown in Fig. 3d. The average value of this quarterperiod of the signal will be subassenza stantially equal to zero, sincethe reference potential is at` ground potential, and, therefore, this alternating area is herein considered not to be an area of a plurality of small pulse widths but an area of zero level potential or, in other words, a no pulse area. During the third quarter of the period shown, signal Q is at its high level E2 since the phase shifted signal is at its high level, and therefore, actuating signal AS is generated. During the last quarter of period T signal Q remains at its high level since both the reference signal and phase shifted signals are at their low level values so that no actuating pulses are generated. In Fig. 3e there is shown a waveform of pulse width modulated signal Q as it would be generated by pulse width modulator 15 when it is operating in the second mode of operation, or 'in other words, when selection signal S is the inverted phase shifted signal Sp1. During the rst quarter of a period, pulse width modulated signal Q has a value of zero, while during the next half of a period it has a value of El. In the final quarter period pulse modulated signal Q has a value of E2. Since El and E2 are equal in magnitude but opposite in polarity the integrated value of one cycle of pulse Width modulated signal Q is 1A E1, while the integrated value of one cycle of pulse modulated` signal Q produced when the modulator is in the first mode of opera tion, shown in Fig. 3d, Yis 1.41. E2. As will be hereinafter v disclosed, the value of the difunction signal train for a 90"'. phase shift is zero and the integrated value over one complete cycle of E1 and E2 voltages is scaled by a scaling resistor 41 to represent the values +4 and -4, respectively. Therefore, with a 90 phase shift the incremental integrated value of each cycle of pulse width modulated signal Q produced when pulse width modulator 15 is operating in the rst and second mode of applied signal Q with respect to time; sensing element coupled to the integrator and operative to sample during, each difunction signal period the integral developed for generating a +1 valued difunction signal whenyeverzthe integral exceeds a predetermined reference level and a( -k-l valued difunction signal whenever the integral is less than the predetermined reference level, the sensing element further generating feedback signal f corresponding to the difunction signal and the complementary feedback signal selecting gate 59 which is responsive to yfeedback signals f and? to generate selection signal S corresponding to the phase shifted when feedback signal is Yat its high level and corresponding to the inverted phasefshifted signal when feedback signal f is at its high levelactuating gate 69 which is responsive to selection signals and the clock pulse C1 to generate an actuating signal As; bistable flip-flop Q which is responsive in part tothe applied AS signal to generate pulse width modulated signal Q; clamping circuit 32 coupled between flip-flop Q and integrator 33 for clamping the pulse Width signal Q; and a timing signal source 39 for generating a timing signal tp, which is applied over conductor tp to sensing element 85. Timing signal tp is a periodically recurring clock or timing signal Whose period is equal to the periods of the input signals Sp and Rp. In operation the timing signal synchronizes kthe operation of the converter to delimit or mark-off successive difunction signal periods.

As shown in Fig. 2, selecting gate 59, gate 69, clamping circuit 32,' and flip-flop Q are the same element as hereinbefore referred to as elements of the pu se width modulator 15 and therefore are mutual or shared elements.

Integrator V33, sensing .element 8.5, .and ,Signal source 39 have been,hereinbeforementioned in connection with the preferred embodiment of the invention and will Vnot be further discussed here except to point out minor differences in the structure and operation.

Sensing element 85 generates feedback signal f, which corresponds to the difunction signal train, and complementary feedback signal y?, both of which the element did not generate in the preferred embodiment. However, the structure and operation of the element is still substantially identical `to that in the preferred embodiment. For a detailed discussion of the structure and operation of sensing element 85 reference is again made to copending U.S. patent application, Serial No. 592,963,

filed lune 21, 1956, for Apparatus for Analog-to-Difnnedon Conversion, by Daniel `L.Curtis.

Directing attention now to the operation of difunction generator E7, if a +1 difunction signal is being generated, feedback signal f will be at its high level and feedback signal Yywill be at its Alo-w level, so that vselection signal S will correspond to the phase shifted signal. Selecting gate 59I will continue responsive to the phase shifted signal until the integrated current signal of capacitor 81 becomes less than the predetermined reference level. When the integrated current signal falls below the predetermined level sensing element 85 will generate a -l difunction signal and feedback signal f will change to its low level and feedback signal f will change to its high level. Selecting gate 59 will now not generate selection signal S corresponding to the invertedphase shifted sig- `nal Sp1, but to the phase shifted signal Sp. In this manner, the +1 or -1 value of the generated difunction signals will be subtracted from capacitor l41 and a difunction signal train will be generated at terminal 19 wherein the value of the difunction train will be proportional to the average value of the phase shift represented by pulse width modulated signal Q.

Referring now to Figs. 3f and 3g, there is shown in Fig. 3 f a waveform, plotted on a common time axis with Figs. 3x1-3e, of the incremental integrated current charge deposited on capacitor 41 by one cycle of pulse width modulated signal Q of Fig. 3d. In Fig. 3g, there is shown a waveform similar to that in Fig. 3d except the waveform represents the incremental integrated current charge deposited on capacitor 41 by one cycle of pulse width modulated signal Q of Fig. 3e. It can be seen that one complete cycle of pulse width modulated signal Q shown in Figs. 3d and 3 e will deposit on capacitor 41 an incremental integrated current charge of +1 and .-1 values,

respectively.

In operation, vif we assume an existing charge on capacitor 41 of -1/2 and that pulse width modulator 15 is operating in the first -rnode of operation then after the production of one cycle of the pulse width modulated signal (as shown in Fig. 3d) the total charge on capacitor 41 will be +1/2. This is -true since the incremental integrated current charge due to one cycle of the pulse width modulated signal Q of Fig. 3d is deposited on capacitor 4l in accordance with the waveform of Fig. 3f. As shown in Fig. 3f, at the end of one cycle of a charge of +1 is deposited on capacitor 41 and this +1 value added to the -1/2 value charge already on capacitor 41 gives a total charge of +1/2 value. In addition, the difunction generator has produced a +1 difunction signal since feedback signal f must lbe at a high level for pulse width modulator to be operable inthe rst inode of operation.

lf the predetermined reference level of sensing element 85 is fixed at zero potential, then at the start .of the next difunction period a .-1 difunction signal is generated and feedback signal f goes low and feedback signal f goes to its high level. Therefore, pulse width modulator 15 is operable in the second mode of operation, producing pulse width v:modulated signal Q, Shown in Fig. 3e. The

pulse width vsignalsln'wvu .in Eig. 3e will Jcause an integrated :current charge to be deposited on V,capacitor- 4'1, as shown in Fig. 3g. As shown in Fig. 3g, the yi11- cremental integrated current charge dueto one cycle of signal Q is l. This value added to the +1/z value already present on capacitor 41 gives a total charge of -1/2. At this point the feedback signals will again change as the predetermined reference level of zero was passed and a +1 difunction signal will be produced. This process will continue -as long as the input signal has a phase -shiftand results in a difunction signal train of alternate +1 and -1 value signals or an average value `of zero.

`In a similar manner, as hereinbeforeset forth to illustrate that a 90 phase shftresults in la difunction signal train of zero value, it can be shown that a phase shift of 0, 30, 60, 120, 15.0, 180 give .a Ydifunction signal train 4of the value +1, -2/3, -1/3, 1/3, l Arespectively.

Directing attention to a difunction signal, generally, as hereinbefore described, va difunction signal train is composed of N1 valued and N2 valued signals and the value of the Ydifunction signal train is given by the following equation:

where Y is the value of the difunction signal train and n1 and n2 are the numberof N1 valued difunction signals andNZ'valued difunction signals in the train, respectively. The increment in value of each integrated cycle of the pulse width modulated signal generated by the inverted phase shifted signal Sp1 and reference signal Rp is given by the following equation:

where V1 is the value of the integrated cycle. Further, the increment in value of each integrated cycle of pulse width modulated signal Q generated by phase shifted -signal SD and reference signal Rp is given by the following equation:

VFY-N2 (3) -where V2 is the value of the integrated cycle. In the case of a bipolar signal where N1 and 'N2 are assigned the values of +1 and -1, respectively, Equations 1, 2 and 3 reduce to the following, respectively:

Further, in the second embodiment of the invention the relationship ofthe -phase Yshift of phase shifted signal Q and the value of the difunction signal train is given by the lfollowing equation:

where 0 is the value of the phase shift in degress.

It is to be expressly understood, of course, that numerous other modifications and alternations may be made have been inverted and used with feedback signal f and instead of thephase shiftedsignal, as ,shown in Fig. 2, i

13 What is claimed as new is: l. An analog converter for converting an analog signal to a non-numeric signal train having a value related to the value of the analog signal, said converter comprising: a signal source for generating a phase shifted signal and a reference signal in response to the analog signal, said phase shifted signal having a phase shift with respect to said reference signal representative of the magnitude of the analog signal; pulse width modulator means responsive to said phase shifted signal and said reference signal to generate a pulse width modulated signal, the pulse width of each cycle of said pulse width modulated signal being related to the phase shift of the phase shifted signal; and non-numeric generator means responsive to said pulse modulated signal to generate a non-numeric signal train, the value of said non-numeric signal train being proportional to the average value of the pulse width modulated signal.

2. The combination defined in claim 1 wherein said signal source further comprises a resolver, said resolver being responsive to the analog signal for generating said phase shifted signal and said reference signal.

3. A difunction converter for converting an applied phase shifted signal, whose phase is shifted with respect to an applied reference signal, to a difunction signal train having a value proportional to the phase shift of the phase shifted signal, said converter comprising: pulse width modulator means responsive to the applied phase shifted signal and applied reference signal to generate a pulse width modulated signal, the pulse width of each cycle of said pulse width modulated signal being related to the phase shift of the applied phase shifted signal; and difunction generator means responsive to said pulse width modulated signal to generate a difunction signal train having a value proportional to the average value of the pulse width modulated signal.

4. The combination defined in claim 3 wherein said pulse width modulator means includes an inverter for generating an inverted signal of a predetermined one of the applied signals and output means responsive to the applied phase shifted signal and the applied reference signal in a first mode of operation to generate saidpulse width modulated signal and responsive to said inverted signal of the predetermined applied signal and the other of the applied signals in a second mode of operation to generate said pulse width modulated signal.

5. The combination defined in claim 4 wherein said difunction generator means includes a sensing element coupled to said modulator means for generating a first bilevel feedback signal having either a high or low level and said output means further includes apparatus responsive to said feedback signal for operating in said first and second modes of operation when said feedback signal is at the high and low level.

6. The combination defined in claim 4 wherein said difunction generator means includes a sensing element coupled to said modulator means for generating a first bilevel feedback signal and a second b ilevel feedback signal having high and low levels, said output means being responsive to said feedback signals for operating in said first mode of operation when said first feedback signal and said second feedback signal are at their high and low levels, respectively, and to be operable in its second mode of operation when said first feedback signal and said second feedback signal are at their low and high levels, respectively.

7. The combination definded in Aclaim 4 wherein said di- Y function generator means includes a sensing element ing a plurality of signals of predetermined numerical values N1 and NZ, said converter comprising: a signal source responsive to the analog signal for generating a phase shifted signal and a reference signal, the phase of said phase shifted signal being shifted a predetermined amount proportional to the magnitude Y with respect to said reference signal; pulse width modulator means responsive to said phase shifted signal and said reference signal for operating in a first mode of operation to generate a pulse width modulated signal having an integrated value in each cycle of said pulse width modulated signal proportional to (Y-N1), and for operating in a second mode of operation to generate said modulated signal having an integrated value in each cycle of said pulse width modulated signal proportional to (Y-N2); and difunction generator means responsive to said pulse width modulated signal to generate a difunction signal train having a value proportional to the average vlue of the pulse width modulated signal and to generate a bilevel feedback signal, said feedback signal being applied to said modulator means, said modulator means being responsive thereto to be operable in said first or second mode of operation in accordance with the level of said feedback signal.

9. An analog converter for converting an analog signal having a numerical magnitude Y to a difunction signal train representative of the magnitude Y and having a plurality of signals of predetermined numerical values N1 and N2, said converter comprising: a signal source responsive to the analog signal for generating an applied phase shifted signal and an applied reference signal, the phase of said applied phase shifted signal being shifted with respect to said applied reference signal, the magnitude of said phase shift being related to the magnitude of Y; inverter means responsive to a predetermined one of said two applied signals to generatea complementary signal of said predetermined applied signal; pulse width modulator means responsive to said phase shifted signal and said reference signal in a first mode of operation for generating a pulse width modulated signal having an integrated value in each cycle of said pulse width modulated signal of (Y-N2) and responsive to said complementary signal and the other of said two applied signals in a second mode of operation for generating a pulse Width modulated signal having an integrated value in each cycle of said pulse width modulated signal of (Y-N1); and difunction generator means responsive to said pulse width modulated signal for generating the difunction signal train having a value proportional to the average value of the pulse width modulated signal and for generating a, feedback signal, said modulator means being coupled to said generator means and responsive to said feedback signal for switching between said modes of operation.

1f). A difunction converter for converting an applied signal having a magnitude Y to a difunction signal train having N1 and N2 valued difunction signals, the value of the difunction signal train being equal to the magnitude Y of the applied signal, said converter comprising: first selectively actuable means responsive to the applied signal to generate a first signal having an average value of Y-N1; second selectively actuable means responsive to the applied signal to generate a second signal having an average value of Y-N2; integrator means responsive to said first and second signals for producing in response thereto an integrated signal representing the integral of the applied signals; difunction generator means responsive to the integrated signal to generate the difunction signal train having N1 valued signals when said integrated signal is greater than a predetermined level and having N2 valued signals when said integrated signal is less than said predetermined level; and third means responsive to each difunction signal for selectively actuating said first or second means in accordance with the value of the difunction signal.

11. A difunction converter for converting an applied phase shifted signal, having a phase shift with respect to an applied reference signal representative of a numerical magnitude Y, to a difunction signal train, representative of a magnitude Y, having a plurality of signals of predetermined numerical Values N1 and N2, said converter comprising: inverter means responsive to a predetermined one of the two applied signals to generate an inverted signal of the predetermined applied signal; pulse width modulator means selectively actuable in response to the application of a predetermined actuating signal for switching between a rst mode and a second mode of operation, said pulse width modulator being responsive in said rst mode of operation to the applied phase shifted and reference signals to generate a pulse width modulated signal having an integrated value in each cycle of said pulse width modulated signal of (Y-N2) and responsive in said second mode of operation to said inverted signal of the predetermined applied signal andthe other of the two applied signals to generate a pulse width modulated signal having an integrated value in each cycle of said pulse width modulated signal of (Y-N1); and difunction generator means responsive to said pulse width modulated signal for generating a difunction signal train having a value proportional to the average value of the pulse width modulated signal and for generating said predetermined actuating signal.

References Cited in the le of this patent UNITED STATES PATENTS