RU2420788C1 - Data output control system - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: data output control system has first and second interfacing units, a register, a memory unit, a computer and an additional register. The system also has a code comparator, a code subtractor, a reference frequency generator, a code converter, a digital-to-analogue converter, a controlled frequency divider, a first and a second 3-input AND element, a bidirectional counter, an input and an output bus.

EFFECT: wider field of use owing to obtaining analogue data at the output of the system.

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Description

The present invention relates to computer technology and can be used in the design of research process control systems, in particular, in the development of an automated complex designed to determine the physicomechanical properties of materials by kinetic indentation.

A device for controlling data output in start-stop mode [1]. There is also known a device for controlling data output in start-stop mode, which is the closest technical solution to the claimed alleged invention [2].

The disadvantage of this device is the presence at its output of data only in digital form codes.

The aim of the invention is to obtain at the output of the device data in analog form.

This goal is achieved in that in a data output control system comprising a first pairing unit 3, a second pairing unit 2, a register 5 and a memory unit 4, the first input of the register 5 being connected to the first output of the first pairing unit 3, and the second input to the output of memory unit 4, the input of the first interface unit 3 and the first output of the second interface unit 2 are interconnected, additionally connected are computers 1, additional register 6, and also a code comparison circuit 7, a code subtractor 8, a reference frequency generator 9, a 10 k converter are connected Dov controlled divider 11 frequency. The first and second logical elements 3I 12 and 13, respectively, a reverse counter 14, a digital-to-analog converter (DAC) 15, an input bus 16, and an output bus 17 are also introduced. Bidirectional input-output of the computer 1 is connected to the bidirectional input-output of the second block 2 pairings. The second output of the second interface unit 2 is connected to the first input of the memory unit 4, the second input of the memory unit 4 is connected to the second output of the first interface unit 3. The third output of the first conjugation unit 3 is combined with the first input of the additional register 6 and the fourth input of the reversible counter 14. The second inputs of the additional register 6, circuit 7 for comparing codes, a code subtractor 8 and a reverse counter 14 are combined and connected to the output of register 5. The first inputs the code subtractor 8 and the code comparison circuit 7 are interconnected and connected to the output of the additional register 6. The output of the code subtractor 8 is combined with the first input of the code converter 10, the output of which is connected to the second the controlled frequency divider 11, the first input of the controlled frequency divider 11 is connected to the output of the reference frequency generator 9. The output of the controlled frequency divider 11 is connected to the third input of the first logical element 12 3I, as well as to the third input of the second logical element 13 3I. The first output of the code comparison circuit 7 is connected to the first input of the first logic element 12 3I, the second output of the code comparison circuit 7 is connected to interconnected second inputs of the first logic element 12 3I and the second logic element 13 3I. The third output of the code comparison circuit 7 is connected to the first input of the second logical element 13 3I, as well as the third input of the subtractor 8. The output of the second logical element 13 3I is connected to the third input of the reverse counter 14. The first input of the reverse counter 14 is combined with the output of the first logical element 12 3I. The third output of the first interface unit 3 is connected to the fourth input of the reverse counter 14, and the output of the reverse counter 14 is combined with the input of the DAC 15, the output of which is connected to the output bus 17. The second input of the code converter 10 is connected to the third output of the second interface unit 2. The second input of the first block 3 interface is combined with the input bus 16, and the output of the DAC 15 is connected to the output bus 17.

Consider the operation of the data output control system for its specific application in an automated complex designed to determine the physicomechanical properties of materials by the kinetic indentation method.

As the computer 1, a personal computer is used, compatible with the IBM PC and having a PCI expansion slot. The hardware of the interface unit 2 provides data exchange with the computer 1 via the PCI exchange protocol via bi-directional input-output. On the bus that connects the bidirectional inputs and outputs of the computer 1 and block 2 interface, codes are transmitted address, data and commands, as well as control signals.

When you turn on the automated complex and, accordingly, the hardware of the system that is part of this complex, a RESET signal will be generated on the PCI bus, which will set the electronic and mechanical elements of the system in a state of readiness for work.

At the beginning of the indentation cycle, the program controlling this cycle, launched in the computer 1, sets the code of the timestamp period through the third output of the interface unit 2 at the second input of the code converter 10, and also writes an array of data codes to the memory unit 4 through the second output. This array of data codes is a digital code for data codes that define the algorithm for performing the indentation cycle. After completion of writing the array of data codes to the computer memory unit 4, by the command of the control program, through the second interface unit 2, a signal will be generated at the first input of the first interface unit 3, which is interpreted by the interface unit 3 as the signal that the indentation cycle itself begins. With the arrival from the input bus 16 to the second input of the first block 3 of the time stamp signal, the first coupler 3 generates a signal on its third output, which writes the code from the output of register 5 to additional register 6 and to the reverse counter 14. Then, at the end of this signal, the first the interface unit 3 will form a signal for reading a data code from the memory unit 4 at its second output. After the time required to read the data code from the memory unit 4, the first interface unit 3 will generate a signal at its first output, which will write the data code read from the memory unit 4 into register 5. Scheme 7 for comparing codes depending on the value of the output data code of register 5 (code A) and the value of the output data code of the additional register 6 (code B) generates one of three possible signals. If the value of code A is greater than the value of code B, then at the first output of the code comparison circuit 7, a signal enabling the operation of the first logic element 12 3I will be generated. If the value of code A is less than the value of code B, the third output of the third logic element 13 3I signal will be generated at the third output of the code comparison circuit 7. If the value of code A is equal to the value of code B, at the second output of the code comparison circuit 7 a prohibiting operation of the first logical element 12 3I and the second logical element 13 3I signal will be generated. If the values of code A and code B are not equal, the second output of the code comparison circuit 7 will generate a permitting operation of the first logical element 12 3I and the second logical element 13 3I signal. Subtractor 8 generates at its output a module of the difference between the values of code A and code B. For this, the subtractor 8, in the absence of a signal at its third input, sums the “unit” with the value of code A and the inverse value of the value of code B, and sums up the signal at its third input the value of code A with the inverse value of the value of code B and the subsequent inversion of the result. The code converter 10 represents as one of the variants of implementation in this complex a read-only memory (ROM), to the address inputs of which a code of the magnitude of the difference module from the output of the subtractor 8, as well as a code of the magnitude of the timestamp period from the third output of the second pairing unit 2 are installed and installed reading mode. Codes are prerecorded in this ROM, when read and fed to the second input of the controlled frequency divider 11, the latter generates a pulse sequence at its output that is numerically equal to the value of the difference module code and independent of the size of the code for the time stamp period. The first timestamp that came after the command started the indentation proper to the second input of the first pairing unit 3 starts the time stamp record from the output of register 5 (the RESET signal sets the “zero code” at the output of register 5) to the reverse counter 14 and additional register 6, after which at the output of register 5 and, accordingly, at the second inputs of the subtractor 8, additional register 6, circuit 7 for comparing codes, as well as at the second input of the reverse counter 14, a digital code of the analog value of the indenter the surface of the material before the arrival of the next timestamp. Suppose the value of this output code is 137, and the timestamp period is 6 ms, (the range of timestamps in a particular application is set from 1 to 256 ms in 1 ms increments), then the code comparison circuit 7 at its first output will generate a signal allowing the operation of the first logical element 12 3I, and at the output of the subtractor 8 and, accordingly, at the second input of the controlled frequency divider 11, a code will be set, the value of which is 137. With this code, at its second input, the controlled frequency divider 11 will form the next pulse duration with a repetition period equal to 43.79 μs. The pulse repetition period from the output of the reference frequency generator 9 should be equal to 319.67 ns. The pulses from the output of the controlled frequency divider 11, passing through the first logical element 12 3I to the first (summing) input of the reverse counter 14 for the period of the time stamp, i.e. in 6 ms, the value of the output code will be increased from a “zero” value to 137. Thus, the aforementioned change in the output code of the reverse counter 14 for the time stamp period will be performed not “stepwise”, but in 137 cycles of the minimum change. The output voltage of the DAC 15, which converts the value of the input code, will also change not "stepwise", but over 137 clock cycles of increase by one of its least significant digit in each clock cycle. The output of the DAC 15 is connected to the input of the power generator (voltage-force converter), (not shown in the drawing), so the change in the magnitude of the force will be similar to the above. If during the indentation process the value of code A will be less than the value of code B, the pulses from the output of the controlled frequency divider 11 through the second logic element 13 will go to the third (subtracting) input of the reverse counter 14 and reduce the value of its output code by the value of the code module of the difference of the current time stamp. The subtraction process is similar to the summation process described above. If in the process of indentation, code A is equal to code B, the signal from the second output of the code comparison circuit 7 will prohibit the operation of the first logic element 12 3I and the second logical element 13 3I, while the output code of the reverse counter will not change.

Thus, the introduction of additional components into the system with their relationships ensures that the output of the system data in analog form.

Information sources

[1] British Patent, G4A, No. 1264096, 1972.

[2] Copyright certificate of the USSR, cl. G06F 3/04, No. 583423, 1976.

Claims (1)

A data output control system comprising a first interface unit, a second interface unit, a register and a memory unit, the first input of the register being connected to the first output of the first interface unit, and the second input to the output of the memory unit, the first input of the first interface unit and the first output of the second unit conjugations are interconnected, characterized in that it is additionally connected to a computer, an additional register, a code comparison scheme, a code subtractor, a reference frequency generator, a code converter, a controlled frequency divider, first and the second logical elements 3I, a reversible counter, a digital-to-analog converter, input and output buses, the bi-directional input-output of the computer connected to the bi-directional input-output of the second interface unit, the second output of the second interface unit connected to the first input of the memory unit, the second input of the memory unit connected with the second output of the first interface unit, the third output of the first interface unit is combined with the first input of the additional register and the fourth input of the reverse counter, the second inputs of the additional reg For example, the code comparison circuits, the code subtractor and the reverse counter are interconnected and connected to the register output, the first code subtractor inputs and the code comparison circuits are interconnected and connected to the additional register output, the code subtractor output is combined with the first input of the code converter, the output of which connected to the second input of the controlled frequency divider, the first input of the controlled frequency divider is connected to the output of the reference frequency generator, the output of the controlled frequency divider is connected to the third at the input of the first logical element 3I, as well as the third input of the second logical element 3I, the first output of the code comparison circuit is connected to the first input of the first logical element 3I, the second output of the code comparison circuit is connected to the combined second inputs of the first logical element 3I and the second logical element 3I, the third output of the code comparison circuit is connected to the first input of the second logic element 3I, as well as to the third input of the code subtractor, the output of the second logic element 3I is connected to the third input ohms of the reverse counter, the first input of the reverse counter is combined with the output of the first 3I logic element, the output of the reverse counter is combined with the input of the digital-to-analog converter, the second input of the code converter is connected to the third output of the second interface unit, the second input of the first interface unit is combined with the input bus, the output of the digital-to-analog converter connected to the output bus.