JP2003032114A - Integral type analog to digital converter and charger using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integral type analog/digital converter that uses a low frequency analog/digital conversion clock in order to monitor and measure an integral value of battery charging/discharging currents with low power consumption and extended dynamic range. SOLUTION: The analog/digital converter uses an integrator to integrate a current in response to a signal input, allows a constant current source to supply (or extract) a constant current to (from) the integrator depending on the output polarity of the integrator when the integral value of the input signal reaches a prescribed value or in a prescribed periodic timing in a direction of decreasing its integral value and allows a counter to count up (or count down) a count only for a period of the constant current flowing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integral A / D converter for measuring a direct current, and more particularly to an integral A / D converter suitable for measuring an integrated value of a charge / discharge current of a battery, and the integral A / D converter. The present invention relates to a charger using a D converter.

[0002]

2. Description of the Related Art Notebook computers, personal mobile terminals (PD
BACKGROUND ART A), a digital still camera (DSC), a smart phone, an electric car, a battery is widely used as a power source for various electric devices such as an electrically assisted bicycle.

In these batteries, for example, batteries such as lithium-ion batteries used in notebook computers, there is a risk of bursting if overcharged by exceeding the rating during charging, and conversely, the capacity is reduced. If the discharge is exceeded, the charging / discharging characteristics will deteriorate.

In order to avoid such a situation and to bring out the full performance of the battery, it is necessary to carry out charging and discharging control suitable for the charging and discharging characteristics, and at the same time, to make it convenient when the mounted set is used. Therefore, a measuring device for monitoring the charge / discharge state of the battery has been conventionally used.

The conventional measuring device uses a charging / discharging current (for example, 0.5 mA to 15 A) that varies over a wide range as a voltage (5 μV).
To 150 mV), the converted voltage is amplified, sample-held, converted into a digital signal by a multi-bit (for example, 10-bit) successive approximation A / D converter, and averaged. It is composed of a microcontroller unit (MCU) and the like.

In this conventional measuring apparatus, since the integrated value of the charging / discharging current is obtained based on the product of the discrete value obtained at each predetermined sampling cycle and the time, there is an error in the integrated value, and the dynamic value of the input signal. Since the range is wide and it is affected by continuous minute current and noise, it has been difficult to improve the accuracy of current integrated value measurement. Further, since it is necessary to repeat the measurement by averaging processing or the like in order to obtain practical accuracy, the operation time of the MCU that consumes a relatively large current becomes long, and it is difficult to reduce the power consumption.

FIG. 7 shows the configuration of a conventionally known integral type A / D converter for performing continuous value integration and A / D conversion, and its timing chart is shown in FIG. 7 and 8, the integrating circuit 701 is initially reset and the integrated output Ea is at zero voltage. In this state, when the start pulse s is applied and the flip-flop 703 is set, the switch S1 is turned on, the switch S2 is turned off, and the input signal Ei is connected. The integration circuit 701 starts integration of the input signal Ei, and the first integration period Ts, which is a reference period, starts and the slope −Ei / R.
When the output Ea of C is generated and the output Ea exceeds the comparison voltage −ΔVt, the comparison pulse p is generated.

As a result, the AND circuit 706 is opened and the counter 704 starts counting the clock pulses of the clock pulse generation circuit 705. After a certain time Ts, the count value of the counter 704 reaches the overflow value Nm,
Flip-flop 703 by overflow pulse r
Is reset.

Therefore, this time, the switch S1 is turned off,
The switch S2 is turned on, the reference voltage is switched to the −Es side, the second integration period T is started, and the integration circuit 701 performs integration of the slope Es / CR opposite to the previous one. And output Ea
Is returned to the comparison voltage −ΔVt, the comparison circuit 702 is inverted,
The AND circuit 706 is closed. During this time, the counter 704
Is counting from 1 again after overflow,
The count value N when the AND circuit 706 is closed is a value proportional to the input signal Ei.

In this way, the input signal E in the integrating circuit 701 is
i is integrated only for the reference period Ts, then the integration circuit 701 is switched to the reference voltage −Es having a polarity opposite to that of the input signal Ei, and the integration value is integrated back to zero. Since the integrated value of the first half of the integrating circuit 701 is proportional to the value of the input signal Ei, the backward integration time T of the latter half is proportional to the value of the input signal Ei. By counting clock pulses during this period, A / D conversion is performed. It was done. This conventional integration type A / D converter has an advantage that the circuit can be constructed at a low cost and is hardly affected by noise.

[0011]

However, this conventional A / D converter is limited by the dynamic range when the value of the input current changes over a wide range such as the charging current or the discharging current of the battery. It is difficult to achieve high accuracy, and it is difficult to reduce power consumption because the A / D conversion clock must be a high-frequency clock in order to end the A / D conversion operation quickly. Have a point.

In view of the problems of these conventional devices, the present invention uses a low-frequency A / D conversion clock to monitor and measure the integrated value of the charging / discharging current of the battery, while reducing power consumption. It is an object of the present invention to provide an integration type A / D converter that can achieve higher speed, shorten the time until the end of A / D conversion, and expand the dynamic range.

[0013]

An integral type A / D according to claim 1
The converter includes an integrator composed of an amplifier, a capacitor connected between an input terminal and an output terminal of the amplifier, and an input resistor connected to the input terminal of the amplifier, and an input terminal of the amplifier that responds to a command signal. Constant current means for inflowing or outflowing a constant current, comparing means for generating a comparison output when the output of the integrator exceeds a predetermined voltage, and counting according to the count command signal, and the count value is timely. A counter for outputting the comparison output, the constant current means according to the comparison output, and a control means for supplying each command signal to the counter, and the constant current according to the comparison output. A command signal is given to the means and a count command signal is given to the counter.

According to the integral type A / D converter of claim 1, since the A / D conversion is started during the integration of the input signal, the clock of the A / D conversion can be set to a low frequency, and It is possible to shorten the time until the end of the / D conversion.

Further, when the integrated value of the input signal reaches a predetermined value, a constant current is made to flow in or out so as to reduce the integrated value, so that the dynamic range of A / D conversion can be expanded. Therefore, input signals of the same level are
When the D conversion is performed, it is possible to improve the accuracy by adjusting the gain of an amplifier or the like.

An integrating A / D converter according to a second aspect of the present invention is an integrator comprising an amplifier, a capacitor connected between an input terminal and an output terminal of the amplifier, and an input resistance connected to the input terminal of the amplifier. Constant current means for flowing a constant current into or out of the input terminal of the amplifier according to a command signal, and generating a first comparison output when the output of the integrator exceeds a predetermined first voltage, Similarly, a comparator that generates a second comparison output when the output of the integrator reaches a predetermined second voltage, a counter that counts according to a count command signal, and outputs a count value in a timely manner;
The comparison output and the second comparison output are input, the constant current means and the control means for supplying each command signal to the counter according to the comparison output are provided, and the constant output means is provided according to the first comparison output. A command signal is given to the current means and a count command signal is given to the counter, and the command signal and the count command signal are stopped according to the second comparison output.
It is characterized by

According to the integral type A / D converter of the second aspect, the same effect as that of the A / D type converter of the first aspect is exhibited, and the integrator output exceeds the predetermined first voltage. Counting starts at a predetermined second voltage (eg,
Since the count is stopped when the voltage reaches (zero voltage), the input signal can be A / D converted with high accuracy. Further, even when the integrator output oscillates in the vicinity of the predetermined second voltage, the constant current means is not wastefully switched, so that an error caused by noise during switching is small.

An integrating A / D converter according to a third aspect of the present invention is the integrating A / D converter according to the second aspect, in which the output of the integrator rises when the output of the integrator exceeds a predetermined first voltage. Similarly, the output of the integrator is the second
A comparator having a hysteresis characteristic that falls when a voltage is reached is provided, and a command signal is given to the constant current means and a count command signal is given to the counter according to the output of the comparator.

According to the integral type A / D converter of the third aspect, the same effect as that of the A / D type converter of the second aspect can be obtained, and the comparing means is one comparator having a hysteresis characteristic. , Can be configured simply.

An integrating A / D converter according to a fourth aspect of the present invention is an integrator comprising an amplifier, a capacitor connected between an input terminal and an output terminal of the amplifier, and an input resistor connected to the input terminal of the amplifier. A constant current means for flowing a constant current into or out of the input terminal of the amplifier according to a command signal, and a comparison output for generating a comparison output when the output of the integrator exceeds a predetermined voltage near zero voltage. A means, a counter that counts according to a count command signal, and outputs a count value in a timely manner, the comparison output is input, and the presence or absence of this comparison output is monitored for each predetermined cycle, and according to the monitoring result, The constant current means and the control means for supplying each command signal to the counter are provided, and when the comparison output is present in a predetermined cycle, the constant current means is instructed to send the command signal to the counter. Provides an instruction signal respectively, to stop the command signal and the count command signal by said comparison output is exhausted, characterized in that.

According to the integral type A / D converter of the fourth aspect, the same effect as that of the A / D type converter of the first aspect can be obtained. Further, since the constant current means and the counter are operated in accordance with the monitoring result of the comparison output in every predetermined cycle, the constant current means is not wastefully switched, and the error occurrence due to the noise at the time of switching is avoided, which is simple. It can be configured in various ways.

An integrator type A / D converter according to a fifth aspect of the present invention is an integrator comprising an amplifier, a capacitor connected between an input terminal and an output terminal of the amplifier, and an input resistor connected to the input terminal of the amplifier. Constant current means for flowing a constant current into or out of the input terminal of the amplifier according to a command signal, and generating a first comparison output when the output of the integrator exceeds a predetermined first voltage, Similarly, a comparator that generates a second comparison output when the output of the integrator reaches a predetermined second voltage, a counter that counts according to a count command signal, and outputs a count value in a timely manner;
The comparison output and the second comparison output are input, and the constant current means and the control means for supplying each command signal to the counter according to the comparison output and the predetermined cycle signal are provided, and the first comparison output is provided. Accordingly, a command signal is given to the constant current means, and a count command signal is given to the counter,
The command signal and the count command signal are stopped according to the second comparison output, and the second comparison output is generated at a predetermined cycle, and each command signal is supplied to the constant current means and the counter. If not, a command signal is given to the constant current means and a count command signal is given to the counter, and the command signal and the count command signal are stopped according to the second comparison output.

According to the integral type A / D converter of the fifth aspect, the same effect as that of the A / D type converter of the second aspect can be obtained. Furthermore, since the constant current source and the counter are operated according to the monitoring result of the second comparison output every predetermined period,
The constant current discharge and the counting operation are started at the earlier of the first comparison output and the timing of the predetermined cycle. Therefore, the time required to complete the A / D conversion after the end of the integration period can be minimized.

A charger according to a sixth aspect is characterized in that the integrating A / D converter according to the first to fifth aspects is used as a monitoring device for a battery charging current and / or discharging current.

According to the charger of the sixth aspect, the integrated value of the charging current or the discharging current of the battery can be measured with high accuracy and economically.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an integrating A / D converter according to the first embodiment of the present invention, and FIG. 2 is its timing chart.

This integration type A / D converter integrates the input signal Vin during the integration period T0 (t1 to t10 in FIG. 2) and performs A / D conversion. The integration period T0 can be set independently or continuously. First, the case of setting the integration period independently, which is a basic operation, will be described.

In FIG. 1, the input signal Vin is a voltage proportional to the charging current or discharging current of the battery, and is obtained as a voltage drop of the current detecting resistor, for example, 5 μV to
It fluctuates within a wide range of 150 mV. The input signal Vin is supplied to the integrator 10 via the switch SW1 which is closed in the ON state by the control signal TC1 during the integration period T0.

The integrator 10 includes a differential amplifier Ai and an input resistor Ri connected to the inverting input terminal of the amplifier Ai.
And a capacitor Ci connected between the inverting input terminal and the output terminal of the amplifier Ai.

At the inverting input terminal of the amplifier Ai, the constant current Iu is supplied to the ground voltage Vgnd by the constant current source I1.
Are supplied via the switch SW2. The switch SW2 outputs the output of the integrator 10 from when the output voltage of the integrator 10 exceeds a predetermined negative voltage Em which is a predetermined first voltage to when it reaches a predetermined second voltage, for example, zero voltage. The absolute value of the voltage is lower than the predetermined value Em and the main integration type A /
It is turned on from the time when the integration period T0 of the D converter ends until the zero voltage is reached.

Hereinafter, in the embodiments of the present invention, the output voltage of the integrator 10 will be described as an absolute value. Further, in the present invention, the ground voltage Vgnd can be replaced with a predetermined bias voltage, and other voltages related to the ground voltage Vgnd can be changed corresponding to the replacement.

The magnitude of the constant current Iu is determined by the magnitude of the input current by the input signal Vin and the output dynamic range of the integrator. That is, the output of the integrator, which is generated by the difference between the input current of the input signal Vin and the charge accumulated in the capacitor Ci during the integration period T0, is determined to be within the dynamic range. It That is, {(Vin / Ri) -Iu} × T0 / Ci ≦ integrator 1
Output dynamic range of 0

The non-inverting input terminal of the amplifier Ai is connected to the ground voltage Vgnd. Further, a switch SW4 is connected between the terminals of the capacitor Ci, and this switch SW4 is momentarily closed in order to erase the residual charge when a new integration period T0 starts. When the integration period T0 is continuously set, the integration period T0 is not closed to maintain continuity of measurement.

The output voltage c of the integrator 10 is supplied to the inverting input terminal of the first comparator Cm, and the negative voltage Em having a predetermined value is supplied to the non-inverting input terminal thereof, so that the output voltage c exceeds the voltage Em. At some time, the high-level (H-level) first comparison output f is output. In the second comparator Cz, the output voltage c of the integrator 10 is supplied to the non-inverting input terminal, the ground voltage Vgnd is supplied to the inverting input terminal, and the output voltage c becomes a low level in response to the output voltage c becoming slightly larger than zero. The (L level) second comparison output d is output. Since the second comparator Cz is for determining a predetermined voltage such as near the zero voltage of the output voltage c, it suffices if it can fulfill this function.

The control logic means 20 receives the first comparison output f, the second comparison output d, the timing signal TC1, etc., and outputs the up-count signal LO1.

This up-count signal LO1 is output from when the first comparison output f is output (L → H) to when the second comparison output d is not output (L → H), or the second
The comparison output d is output (L), and the main integration type A /
It is turned on for a period from the time when the integration period T0 of the D converter ends until the second comparison output d is no longer output (L → H).

The counter 30 has a clock input terminal U for counting up, a count output terminal O and a reset terminal R. A timing signal TC2 for resetting the count value when a new integration period T0 starts is applied to the reset terminal R. In addition, when the integration period T0 is continuously set, in order to maintain the continuity of the measurement, the count value k at that time is output, the count value k is reset, and then the counting is continuously performed. The counter 30 can also be configured as a down counter.

The clock signal CLK is input to the up-counting clock input terminal U while the switch SW5 is closed by the up-count signal LO1, and the counter 30 counts up.

The register 40 receives the count value k of the counter 30 when the switch SW7 is closed, and stores additional information indicating the data content of the count value, for example, information such as a sign indicating positive / negative and the number of integrations. Attach and output the data. A control signal is applied to the switch SW7 so that the switch SW7 is turned on at the time when the count value corresponding to one integration period T0 is adjusted, that is, at the time t11 when the A / D conversion ends. When the integration period T0 is continuously set, the switch SW7 is turned on at the end time t10 of the integration period,
The count value at that time is output.

The clock pulse generator 50 supplies the clock signal CLK, which is the time reference of the present apparatus, to the counter 30 and the timing controller 60.

The timing controller 60 receives the clock signal CLK and an external operation signal as necessary, creates various timing signals TC1 to TCn, and supplies them to respective required locations. The timing signal TC1 is continuously output during the integration period and supplied to the switch SW1 and the control logic means 20. Timing signal TC
2 is output at the instant when a new integration period T0 starts and is supplied to the switch SW4 and the counter 30. The timing signal TC3 is an A / D conversion operation timing signal and is supplied to the control logic means 20. The timing signal TC4 is a signal having a constant cycle as shown in FIG. If necessary, form timing signals,
Can be used.

Now, the operation of the integral type A / D converter according to the first embodiment will be described with reference to the timing chart of FIG. The following description relates to the operation in one integration period T0.

The timing controller 60 is supplied with a clock signal CLK from the clock pulse generator 50 and a command signal from the outside. Integration period T0 starts t1
Then, the timing controller 60 applies the timing signal TC1 to the switch SW1 to close it during the integration period. At the same time, the timing signal TC2 is given from the timing controller 60 to the switch SW4 and the counter 30 to discharge the residual charge of the capacitor Ci and reset the count value of the counter 30 to set it to the initial state.

After the start of the integration period T0, the input signal Vin
When the (a point potential) is input (t2), integration is performed by the integrator 10 according to the input value, and the c point potential that is the output thereof gradually decreases in the negative direction according to the positive input signal Vin. growing. At time t3 when the potential at point c exceeds the bias voltage Em of the first comparator Cm, the first comparison output f is output (L → H) and applied to the control logic means 20. The control logic means 20 takes in the first comparison output f at the rising edge of the timing signal TC3, which is the A / D conversion operation timing, and takes up the up count signal L.
O1 is generated.

The up-count signal LO1 first closes the switch SW5. The clock signal CL from the clock pulse generator 50 while the switch SW5 is closed.
K is supplied to the clock input terminal U for counting up of the counter 30, and the count value of the counter 30 is counted up. At the same time, the up count signal LO1 is
The switch SW2 is closed. The constant current Iu flows out from the capacitor Ci of the integrator 10 while the switch SW2 is closed. In other words, the difference current between the current flowing in according to the input signal Vin and the constant current Iu is the capacitor Ci.
Is charged or discharged from the capacitor Ci.

Due to the discharging of the constant current Iu, the potential at the point c gradually decreases, and when it falls below the bias voltage Em of the first comparator Cm, the first comparison output f is not output (H → L).
However, there is still no change in circuit operation in this state. The second comparison output d is not output (L → H) at time t4 when the potential at the point c further decreases and reaches the zero potential which is the determination voltage of the second comparator Cz. In the control logic means 20, since the second comparison output d is no longer output,
The up count signal LO1 is stopped. As a result, the switch SW5 is opened, the up-counting operation of the counter 30 is stopped, the switch SW2 is opened, and the outflow of the constant current Iu is stopped.

In this way, discharging and up-counting by the constant current Iu are performed in parallel with the integration of the input signal Vin, and A / D conversion is performed during the integration of the input signal Vin.

The operation between time points t4 and t7 in FIG. 2 is the same as that described above except that the value of the input signal Vin is different, and therefore the description thereof is omitted.

Next, referring to FIG. 2, the operation when a minute input signal Vin (potential a) is input after the time t8 will be described. In this case, the potential at the point c, which is the integrated output of the integrator 10, gradually increases in the negative direction according to the minute input signal Vin. However, the potential at the point c is the first comparator C
If the input signal Vin (potential at point a) disappears at time t9 before exceeding the voltage Em of m, the potential at point c is maintained as it is.

At the end time t10 of the integration period T0, since the second comparison output d of the second comparator Cz is output, from the time t10 when the integration period T0 of the main integration type A / D converter ends. Switch SW2 and switch S
W5 is closed and the constant current Iu flows out and counts up. This count is the second comparison output d of the second comparator Cz.
Ends at time t11 when is no longer output. Further, the control logic means 20 uses the data output command signal L
O3 is given to the switch SW7.

The up-count pulse i during this period is as shown in FIG. 2, and the resulting count data k of the counter 30 (time t11) is input to the register 40 as the integrated measurement data of the integration period T0.

In the register 40, the input count data and additional information indicating the data content thereof, for example, information such as positive and negative signs and the number of integrations, are added and data is output.

In the embodiment shown in FIG. 1, the comparison means is composed of the first comparator Cm and the second comparator Cz, but instead of this, the output c of the integrator 10 has a predetermined value. A single comparator having a hysteresis characteristic that rises when the voltage Em exceeds one voltage Em and then falls when the output c of the integrator 10 reaches a predetermined second voltage such as zero voltage can be provided.

Even if a single comparator having this hysteresis characteristic is used as the comparison means, the same effect can be obtained.
The comparison means can be simply configured.

Further, as the comparison means in the embodiment of FIG. 1, a single comparator having a simple operation characteristic such that a comparison output is generated only while the output c of the integrator 10 exceeds a predetermined voltage is used. It is also possible to make the comparison means simpler.

When a single comparator having this simple operation characteristic is used as the comparing means, the predetermined voltage is set to a value as small as possible in order to reduce the A / D conversion error. However, from this fact, when the output c of the integrator 10 oscillates in the vicinity of a predetermined voltage, the switch SW2 of the constant current source is frequently switched, and an error due to noise at the time of switching is generated. Since it may occur, it is desirable to decide whether or not to adopt it in consideration of the characteristics of the input signal.

As described above, in the integral type A / D converter for monitoring and measuring the integrated value of the charge / discharge current of the battery, the input signal V proportional to the charge / discharge current of the battery is used.
Since the A / D conversion, that is, the counting operation is started during the integration of in, the clock TC3 of the A / D conversion can be set to a low frequency, and the time until the A / D conversion is completed after the integration period is completed is shortened. can do.

Further, when the integrated value c of the input signal Vin reaches the predetermined value Em, the constant current Iu is caused to flow in a direction to reduce the integrated value c, so that the dynamic range of A / D conversion can be expanded. . Therefore, when A / D-converting the input signal Vin of the same level, it is possible to improve the accuracy by adjusting the gain of an amplifier or the like.

Next, the operation when the integration period T0 is continuously set will be described. This operation will be described focusing on the points different from the operation when one integration period is set independently.

Immediately after the end of one integration period, the next integration period is started. In this case, in order to prevent the count value of the counter 30 from overflowing due to the count in the plurality of integration periods T0, the switch SW7 is closed and the count value of the counter 30 at that time is registered at the end of each integration period T0. 40, and the count value of the counter 30 is reset.
The signal instructing the integration period T0 is supplied from the timing controller 60 as the timing signal TCn.

In order to maintain the continuity of the measurement even when the integration period T0 is continuously set, the operation states other than the output of the count value are not changed even after the end of one integration period. Each switch SW1 ~
Both SW6 are continuously placed in the normal operation state. That is, at the end of one integration period, the main integration type A /
Even if the operation status of the D converter is at any time (t1 to t9) in the timing chart of FIG.
The operating state at that time continues, and nothing is changed by the end of the integration period.

However, as described above, at each end of each integration period T0, the count data corresponding to the integration period T0,
That is, the integrated value of the input signal is sequentially output from the register 40. When the integrator 10 has some integral output at the end of a certain integral period T0, the count value corresponding to the integral output is included in the output of the next integral period.

As described above, according to the integral type A / D converter of the embodiment of the present invention, it is possible to input a plurality of continuous integral periods, which cannot be expected in the conventional integral type A / D converter. The signals can be integrated.

FIG. 3 is a timing chart of the integrating A / D converter according to the second embodiment of the present invention.
The configuration of the integral type A / D converter according to the second embodiment is the same as the configuration diagram according to the first embodiment in FIG. 1, and is not used in the first embodiment and is constant. The only difference is that a timing signal TC4, which is a periodic signal, is used. Therefore, only the points different from the first embodiment of FIG. 1 will be described, and the description of other points will be omitted for simplicity.

In the second embodiment, the timing signal TC4 generated from the timing controller 60 at a constant cycle T is the control logic means 20.
Is supplied to.

The control logic means 20 as the control means has a first comparison output f of H level generated when the output c of the integrator 10 exceeds a predetermined voltage Em, and
L generated when the output c of the integrator 10 reaches zero voltage
The second comparison output d of the level and the timing signal TC4 generated at a constant period T are input, and the switch SW2 of the constant current source I1 and the counter 30 are input in accordance with these signals.
Each command signal is supplied to the switch SW5.

The contents of the control are, firstly, as in the first embodiment, according to the first comparison output f, the constant current source I.
1 switch SW2 and counter 30 switch SW5
And the up count signal LO1 is stopped in accordance with the second comparison output d.

Then, the first comparison output f and the second comparison output d
The second comparison output d is generated every time the timing signal TC4 generated at a constant period T is generated in parallel with the control based on
Is generated, and the switch SW2 of the constant current source I1 is generated.
Also, it is determined whether or not the both conditions that the up count signal LO1 is not supplied to the switch SW5 of the counter 30, that is, the A / D conversion operation is not performed, are met.

Regarding whether or not these two conditions are met,
Looking at FIG. 3 by way of example, at time t during the integration period
When the timing signal TC4 is generated between 1 and t9, both conditions do not match.

When the timing signal TC4 is generated between the time points t9 and t10 during the integration period, both conditions that the second comparison output d is generated and the A / D conversion operation is not performed are satisfied. There is. In response to the establishment of these two conditions, the control logic means 20 applies the up-count signal LO1 to the switch SW2 of the constant current source and the switch SW5 of the counter 30, respectively, and starts the A / D conversion operation. The output c of the integrator 10 according to this A / D conversion operation
Decreases and the second comparison output d is no longer generated at the time t10 when the output c becomes almost zero voltage. This second
In response to the generation of the comparison output d, the up-count signal LO1 is turned off, and the A / D conversion operation ends.

Thus, the integral type A / of the second embodiment is
In the D converter, in addition to the A / D type converter of the first embodiment, the constant current source I1 and the counter 30 are operated in accordance with the monitoring result of the comparison output d for each predetermined period T to operate the A / D converter.
Integrator 1 starts the D conversion operation and stops the A / D conversion operation.
The output c of 0 has become zero voltage, that is, the second comparison output d
Is not output anymore. Therefore, A / D
The conversion operation is performed according to the first comparison output f or in a predetermined cycle T.
Since it is started according to the timing of, it is possible to minimize the time until the completion of A / D conversion after the end of the integration period.

FIG. 4 is a diagram showing the configuration of an integrating A / D converter according to the third embodiment of the present invention, and FIG. 5 is its timing chart.

The configuration of the integral type A / D converter according to the third embodiment shown in FIG. 4 is the same as that of the output of the integrator 10 in the configuration diagrams according to the second embodiment of FIGS. The first comparator Cm, which generates the first comparison output f when c exceeds the predetermined voltage Em, is deleted, and the content of control depends on the first comparison output f. This is to omit the control for applying the up-count signal LO1 to the switch SW2 and the switch SW5 of the counter 30 and stopping the up-count signal LO1 according to the second comparison output d.

Other configurations and control contents are the same as those in the second embodiment. Therefore, only the points different from the second embodiment of FIGS. 1 and 3 will be described, and the description of other points will be omitted for simplicity.

In the third embodiment, as a comparison means, a comparator which generates an L-level comparison output d when the output c of the integrator 10 exceeds a predetermined voltage near zero voltage. Only Cz is used.

The timing signal TC4 generated from the timing controller 60 at a constant cycle T is supplied to the control logic means 20.

The control logic means 20 as the control means receives the comparison output d generated when the output c of the integrator 10 reaches zero voltage, the timing signal TC4 generated at a constant cycle T, and the like. In response to each of these signals, the up-count signal LO1 is supplied to the switch SW2 of the constant current source and the switch SW5 of the counter 30.

The control content is such that the comparison output d is generated every time the timing signal TC4 generated at a constant period T is generated.
Is generated, that is, the output c of the integrator 10 has a certain value, and the switch SW of the constant current source I1.
2 and the switch SW5 of the counter 30 are not supplied with the up-count signal LO1, that is, it is determined whether or not both conditions that the A / D conversion operation is not being performed are met.

Regarding whether or not both of these conditions are met,
Looking at FIG. 5 by way of example, at time t during the integration period
When the timing signal TC4 of 3, t6, t10 is generated, both conditions are satisfied that the comparison output d is generated and the A / D conversion operation is not in progress.

In response to the establishment of these two conditions, the control logic means 20 supplies the up-count signal LO1 to the switch SW2 of the constant current source I1 and the switch SW5 of the counter 30 at the time t3 (t6, t10) A / A, respectively. The D conversion operation starts. The output c of the integrator 10 decreases in accordance with this A / D conversion operation, and the second comparison output d is no longer generated at the time t4 (t7, t11) when the output c becomes almost zero voltage state.

When the second comparison output d is no longer generated, the up count signal LO to the switch SW2 of the constant current source I1 and the switch SW5 of the counter 30 is generated.
1 is turned off, and the A / D conversion operation ends.

When the timing signal TC4 is generated at times other than the times t3, t6, and t10, the comparison output d is not generated at all, or the A / D conversion operation is already in progress. It never enters D conversion operation.

In this way, the integral type A / of the third embodiment is
In the D converter, the constant current source I1 and the counter 30 are operated according to the monitoring result of the comparison output d to start the A / D conversion operation for each timing signal TC4 given in a constant cycle, and the A / D conversion operation is performed. Is stopped when the output c of the integrator 10 becomes zero voltage, that is, when the output signal of the comparator Cz is no longer output. Therefore, since the A / D conversion operation is started at the timing of the predetermined cycle T,
It is possible to shorten the time until the A / D conversion is completed after the integration period ends.

Further, since the switch SW2 of the constant current source I1 is not wastefully switched, an error caused by noise at the time of switching can be avoided, and the comparison means can be configured only by the comparator Cz, so that the integral type The configuration of the A / D converter can be simplified.

FIG. 6 is a diagram showing the configuration of an integral type A / D converter according to a modification of the embodiment of the present invention.

In the first to third embodiments, the input signal Vin is explained as a positive unipolar signal. When the integrating A / D converter of the present invention is used for integrated measurement of current values such as a charging current and a discharging current of a battery, not only in the case of positive unipolarity, but of course an input signal of negative polarity or It is necessary to support both positive and negative polarity input signals.

Even in such a case, the modification of the present embodiment is such that the integral type A / D according to the first to third embodiments described above.
FIG. 6 shows that a converter can be applied, and a concrete configuration when applied to the first embodiment is shown in FIG.
Is illustrated in.

In the modified example of FIG. 6, as shown by the broken line in the figure, a structure for supporting bipolar input is added and a part of the structure is changed. Hereinafter, these additions and changes will be mainly described.

In the figure, the input signal Vin is a voltage proportional to the charging current or discharging current of the battery, and is obtained as a voltage drop of the voltage detection resistor, for example, ± 5 μV.
It fluctuates within a wide range of ± 150 mV.

The inverting input terminal of the amplifier Ai of the integrator 10 is further supplied with the constant current Id from the power supply voltage Vcc by the constant current source I2 via the switch SW3. This switch SW3 has a positive output voltage E of the integrator 10 which is a predetermined value.
It is turned on from the time when it exceeds p to the time when it reaches the zero voltage, or until the time when the output voltage of the integrator 10 is positive and the integration period T0 of the main integration type A / D converter ends and reaches the zero voltage. . The constant current Id usually has the same current value as the constant current Iu.

The comparator Cp has an integrator 1 at its non-inverting input terminal.
The output voltage c of 0 is a positive voltage E of a predetermined value at the inverting input terminal.
p is supplied, the output voltage c of the integrator 10 is a positive voltage Ep
When it exceeds, the third comparison output e is output.

The control logic means 20 receives the third comparison output e in addition to the first comparison output f, the second comparison output d and the timing signal, and receives the up count signal LO1.
And a down count signal LO2.

This up-count signal LO1 is output from when the first comparison output f is output until the second comparison output d is inverted, or when the second comparison output d is low (the output voltage of the integrator 10 corresponds to negative). ) And from the time when the integration period of the main integration type A / D converter ends until the second comparison output d is inverted to high.

The down count signal LO2 is the third
From when the comparison output e is output to when the second comparison output d is inverted, or when the second comparison output d is high (the output voltage of the integrator 10 corresponds to positive) and the integration of the main integration type A / D converter is performed. It is turned on from the end of the period until the second comparison output d is inverted to low.

The counter 30 is an up / down counter. The up / down counter 30 includes a clock input terminal U for counting up, a clock input terminal D for counting down, a count output terminal O, and a reset terminal R.
have. The reset terminal R has a new integration period T
A timing signal TC2 is applied to reset the count value when 0 starts. When the integration period is set continuously, in order to maintain the continuity of the measurement, the count value at that time is output, the count value is reset, and then the counting is continuously performed.

The clock signal CLK is input to the up-counting clock input terminal U while the switch SW5 is closed by the up-counting signal LO1 to up-count. The down count clock input terminal D has a switch SW depending on the down count signal LO2.
While 6 is closed, clock signal CLK is input and down counts.

The integrator 10, register 40, clock pulse generator 50, timing controller 60, etc. are the same as those in the first embodiment.

Now, the integration type A / D in this embodiment
The operation of the converter is basically the same as the timing chart of FIG. 2, but when the input signal Vin has a negative polarity, the components indicated by the broken line in the figure function. That is, it operates as follows.

When the negative polarity input signal Vin (potential a) is generated, the potential c point, which is the integrated output of the integrator 10, increases in the positive direction in accordance with the negative input signal Vin.
When the potential at the point c exceeds the bias voltage Ep of the third comparator Cp, the third comparison output e rises and is applied to the control logic means 20. The control logic means 20 generates the down count signal LO2 when the AND condition between the third comparison output e and the timing signal TC3 which is the A / D conversion operation timing is established.

The down count signal LO2 is first supplied to the switch SW6 to close it. While the switch SW6 is closed, the clock signal CLK from the clock pulse generator 50 is supplied to the down count clock input terminal D of the up / down counter 30, and the count value of the up / down counter 30 is down counted. At the same time, the down count signal LO2 is supplied to the switch SW3 to close it. While switch SW3 is closed,
The constant current Id flows into the capacitor Ci of the integrator 10.
In other words, the current and the constant current I corresponding to the input signal Vin
A current having a difference from d is charged in the capacitor Ci or discharged from the capacitor Ci.

By charging the constant current Id, the potential at the point c gradually recovers, and when it falls below the bias voltage Ep of the third comparator Cp, the third comparison output e falls, but in this state the circuit operation is still changed. There is no.

By the charging of this constant current Id, the potential at the point c is further recovered, and when the zero potential of the second comparator Cz is reached, the second comparison output d is inverted and applied to the control logic means 20.

In the control logic means 20, the second
The down count signal LO2 is stopped by the inversion of the comparison output d. As a result, the switch SW6 is opened, the down-counting operation of the counter 30 is stopped, and the switch SW3
Is opened and the inflow of the constant current Id is stopped. Since the other operations are the same as those in the first embodiment,
Omit description

As shown in the modification of this embodiment,
The present invention can be applied not only to the case of positive unipolarity but also to the input signal of negative polarity or the input signal of both positive and negative polarities. Therefore, the integrating A / D converter of the present invention can be used as a battery. It is also possible to support integrated measurement when the current values such as the charging current and the discharging current are positive and negative.

Further, the integrating A / D converter according to each of the embodiments of the present invention described above can be provided in a battery charger. According to this, the integrated value of the charging current and / or the discharging current of the battery can be measured with high accuracy and economically.

[0107]

According to the integral type A / D converter of the first aspect, since the A / D conversion is started during the integration of the input signal, the clock of the A / D conversion can be set to a low frequency, Moreover, it is possible to shorten the time until the end of A / D conversion.

Further, when the integrated value of the input signal reaches a predetermined value, a constant current flows in or out in the direction of decreasing the integrated value, so that the dynamic range of A / D conversion can be expanded. Therefore, input signals of the same level are
When the D conversion is performed, it is possible to improve the accuracy by adjusting the gain of an amplifier or the like.

According to the integral type A / D converter of the second aspect, the same effect as that of the A / D type converter of the first aspect can be obtained, and the integrator output exceeds the predetermined first voltage. Counting starts at a predetermined second voltage (eg,
Since the count is stopped when the voltage reaches (zero voltage), the input signal can be A / D converted with high accuracy. Further, even when the integrator output oscillates in the vicinity of the predetermined second voltage, the constant current source is not wastefully switched, so that an error caused by noise during switching is small.

According to the integral type A / D converter of the third aspect, the same effect as that of the A / D type converter of the second aspect is obtained, and the comparing means is one comparator having a hysteresis characteristic. , Can be configured simply.

According to the integral type A / D converter of the fourth aspect, the same effect as that of the A / D type converter of the first aspect can be obtained. Further, since the constant current means and the counter are operated in accordance with the monitoring result of the comparison output in every predetermined cycle, the constant current means is not wastefully switched, and the error occurrence due to the noise at the time of switching is avoided, which is simple. It can be configured in various ways.

According to the integral type A / D converter of the fifth aspect, the same effect as that of the A / D type converter of the second aspect can be obtained. Further, since the constant current means and the counter are operated according to the monitoring result of the second comparison output every predetermined cycle, the constant current discharge and the counting operation are started at the earlier of the first comparison output or the timing of the predetermined cycle. Will be done. Therefore, the time required to complete the A / D conversion after the end of the integration period can be minimized.

According to the charger of claim 6, the integrated value of the charging current or the discharging current of the battery can be measured with high accuracy and economically.

[Brief description of drawings]

FIG. 1 is an integration type A / D according to a first embodiment of the present invention.
The figure which shows the structure of a converter.

FIG. 2 is an integration type A / D according to the first embodiment of the present invention.
Timing chart of the converter.

FIG. 3 is an integration type A / D according to a second embodiment of the present invention.
Timing chart of the converter.

FIG. 4 is an integration type A / D according to a third embodiment of the present invention.
The figure which shows the structure of a converter.

FIG. 5 is a timing chart of an integrating A / D converter according to a third embodiment of the present invention.

FIG. 6 is an integration type A / D according to a modified example of the embodiment of the present invention.
The figure which shows the structure of a converter.

FIG. 7 is a diagram showing a configuration of a conventional integral type A / D converter.

FIG. 8 is a timing chart of a conventional integrating A / D converter.

[Explanation of symbols]

10 Integrator 20 Control logic means 30 counter 40 registers 50 clock pulse generator 60 Timing controller Vin input signal Iu, Id constant current Ri input resistance Ai amplifier Ci capacitor Cm first comparator Cz second comparator Cp third comparator

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H03M 1/18 H03M 1/18 F term (reference) 2G016 CA00 CB21 CB22 CB31 CB32 CC01 CC04 CC05 CC08 CC09 CC12 CC16 CC21 CC26 CD10 2G035 AA08 AA13 AA17 AB03 AC15 AD13 AD20 AD23 AD28 AD29 AD30 AD32 AD44 AD51 AD65 5G003 CA05 EA05 5H030 AA03 AS18 BB03 FF42 5J022 AA11 BA01 BA02 BA05 BA06 BA08 CA09 CC04 CE01 CE06 CE08 CF01 CF02 CF04 CF07

Claims (6)

[Claims] 1. An integrator composed of an amplifier, a capacitor connected between an input terminal and an output terminal of the amplifier, and an input resistor connected to the input terminal of the amplifier, and a command signal at the input terminal of the amplifier. Constant current means for inflowing or outflowing a constant current according to the above, a comparing means for generating a comparison output when the output of the integrator exceeds a predetermined voltage, and counting according to a count command signal, and timely A counter that outputs a count value, and the comparison output is input, the constant current means according to the comparison output, a control means for supplying each command signal to the counter, and according to the comparison output, the Command signal to the constant current means,
An integrating A / D converter characterized in that a count command signal is applied to each of the counters. 2. An integrator comprising an amplifier, a capacitor connected between an input terminal and an output terminal of the amplifier, and an input resistor connected to the input terminal of the amplifier, and a command signal at the input terminal of the amplifier. Constant current means for inflowing or outflowing a constant current according to the above, a first comparison output is generated when the output of the integrator exceeds a predetermined first voltage, and the output of the integrator also has a predetermined first voltage. A comparison unit that generates a second comparison output when the voltage reaches two, a counter that counts according to a count command signal, and outputs a count value at an appropriate time, the first comparison output, and the second comparison output are input. The constant current means and the control means for supplying each command signal to the counter according to the comparison output, and the counter signal to the constant current means according to the first comparison output. Giving cement command signals respectively,
An integral type A / D converter characterized in that these command signal and count command signal are stopped according to the second comparison output. 3. The integral type A / D converter according to claim 2, wherein the output of said integrator is a predetermined first as the comparison means.
A comparator having a hysteresis characteristic that rises when the voltage exceeds the voltage and also falls when the output of the integrator reaches a predetermined second voltage, and outputs a command signal to the constant current means according to the output of the comparator. Is provided to each of the counters, and an integration type A / D converter is provided. 4. An integrator comprising an amplifier, a capacitor connected between an input terminal and an output terminal of the amplifier, and an input resistor connected to the input terminal of the amplifier, and a command signal at the input terminal of the amplifier. Constant current means for inflowing or outflowing a constant current according to the above, a comparing means for generating a comparison output when the output of the integrator exceeds a predetermined voltage in the vicinity of zero voltage, and counting according to a count command signal. However, a counter that outputs a count value in a timely manner, the comparison output is input, and the presence or absence of the comparison output is monitored at every predetermined cycle, and the constant current means and the counter are instructed according to the monitoring result. A control means for supplying a signal, and when the comparison output is present in a predetermined cycle, a command signal is given to the constant current means, a count command signal is given to the counter, and the ratio Output stops the command signal and the count command signal by lost, integrating A / D converter, characterized in that. 5. An integrator comprising an amplifier, a capacitor connected between an input terminal and an output terminal of the amplifier, and an input resistor connected to the input terminal of the amplifier, and a command signal at the input terminal of the amplifier. Constant current means for inflowing or outflowing a constant current according to the above, a first comparison output is generated when the output of the integrator exceeds a predetermined first voltage, and the output of the integrator also has a predetermined first voltage. The comparison means for generating the second comparison output when the voltage reaches two, the counter for counting according to the count command signal and outputting the count value at the appropriate time, the first comparison output and the second comparison output are input. The constant current means and the control means for supplying each command signal to the counter according to the comparison output and the predetermined cycle signal, and the command signal to the constant current means according to the first comparison output. Giving a count command signal to each of the counter,
The command signal and the count command signal are stopped according to the second comparison output, and the second comparison output is generated at a predetermined cycle,
Further, when each command signal is not supplied to the constant current means and the counter, a command signal is given to the constant current means and a count command signal is given to the counter, and these command signals are given in accordance with the second comparison output. And an integration type A / D converter characterized by stopping the count command signal. 6. A charger characterized by using the integration type A / D converter according to any one of claims 1 to 5 as a device for monitoring a charging current and / or a discharging current of a battery.