JP2006317425A - Alternating current voltage detection system for power conversion circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correctly detect output voltage within a single PWM carrier cycle. <P>SOLUTION: When voltage Vun occurs on a U-phase output terminal of a PWM-controlled inverter, integration of a detection signal proportional to the output voltage is started, and reference voltage of reverse polarity to that of the detection sinal is integrated when the output voltage becomes zero. Time t1 since the output voltage becomes zero until the integration value of the reference voltage becomes zero is measured. From the time t1, a carrier cycle T, the voltage value of the reference voltage or the like, voltage (average output voltage) in the single PWM carrier cycle is calculated by a predetermined calculation formula. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a detection method for detecting an AC side voltage of a power conversion circuit that converts alternating current into direct current or direct current into alternating current.

  6 to 8 show a conventional method disclosed in Patent Document 1, for example.

  In FIG. 6, 1 is a three-phase commercial power supply, 2 is a three-phase full-wave rectifier circuit, 4 is a PWM (pulse width modulation) inverter, 5 is an induction motor (induction machine), and the induction machine can be an inverter circuit. A general main circuit configuration in the case of variable speed driving is shown. 6 is a speed command value, 7 is a speed detector for detecting the rotational speed of the induction machine, 8 is a vector control circuit, 9 is an adder, 10 is a current command generation circuit, and 11 is current control. A circuit, 12 is an inverter output current detector, 15 is a triangular wave generating circuit, 17 is a non-wrap circuit, and shows a general control circuit configuration for driving the induction machine by vector control.

  Since these operations are not particularly related, description thereof will be omitted.

Reference numeral 18 in FIG. 6 is an inverter output voltage detection circuit. This inverter output voltage detection circuit 18 inputs an inverter input voltage detection value V _DC obtained by insulating the output of the smoothing capacitor 3, a three-phase gate signal Gu, Gv, Gw, and a primary angular frequency command ω1 ^*. As a result, instantaneous phase voltages Vu, Vv, and Vw are output. This detection circuit 18 has been proposed to solve the problems (detection distortion due to magnetic saturation, detection error of the zero cross point) of the voltage detection method using the instrument transformer generally performed so far. FIG. 7 shows the detailed configuration, and FIG. 8 shows an example of the operation waveform of each part.

In FIG. 7, Gu, Gv, and Gw are U-phase, V-phase, and W-phase PWM gate signals. For example, Gu and Gv are shown in FIG. The exclusive OR circuits 21a, 21b, and 21c receive the gate signals and output the inverter line voltage signals Suv, Svw, and Swu. For example, FIG. 8 shows the Suv signal. The high (high) level section of the Suv signal indicates a section where the DC voltage V _DC is applied between the U-phase and V-phase windings of the induction machine.

Then, it outputs a logical product signal Sp AND circuit 22P, Gu signal and Suv signal at 22N, a logical product signal S _N of the Gv signal and Suv signal. The Sp and _SN signals are as shown in FIG. 8, and the high level section of the Sp signal is a section in which the DC voltage V _DC is applied between the U and V phase windings and the U phase winding side becomes a high voltage. In addition, the high level section of the _SN signal indicates a section in which the DC voltage V _DC is applied between the U and V phase windings and the V phase winding side becomes a high voltage.

The signals Sp and _SN are input to the analog switch type primary delay circuits 23P and 23N of FIG. The analog switch type first-order lag circuit 23P turns on the analog switch 26 when the signal Sp is high (high) level, and turns on the analog switch 27 at the high level of the signal obtained from the Sp signal via the inverting circuit 29P. Assuming that the resistance value of the resistor 24 in the circuit 23P is r1, the resistance value of the resistor 25 is r2, and the capacitance of the capacitor 28 is C1, when the Sp signal is at the high level, _VDC is the input voltage and C1 · (r1 + r2) The capacitor 28 is charged by a first-order lag circuit having a time constant. On the other hand, when the Sp signal is at a low level, the capacitor 28 is discharged with a time constant of C1 · r2. The time constant of C1 · r2 is set to a value larger than the PWM switching period. As a result, the output V _UVP of the analog switch type first-order lag circuit has the waveform shown in FIG.

Since the amplitude changes in proportion to the inverter input voltage _VDC , the fluctuation of the inverter input voltage is automatically corrected.

  Analog switch primary delay circuits 23N, 23b, and 23c have the same configuration as circuit 23P and perform the same operation. Reference numerals 29N, 29b, and 29c denote inverting circuits.

Analog switch type first-order delay circuit 23P, 23N of the output V _UVP, V _UVN is subtracted by the subtractor 30, and outputs the U-phase, the line voltage detection value S _UV of the V phase as shown in Figure 8. The primary delay circuits 23b and 23c operate with the V-phase and W-phase line voltage detection values S _VW and the W-phase and U-phase line voltage detection values S _WU , respectively, and their output waveforms are | V in FIG. _VW | The adder 31 adds V _UVP , V _UVN , | V _VW |, | V _VU |, and passes the filter 32 to obtain the amplitude of the line voltage, which is multiplied by 1 / √3 by the amplifier 33. The amplitude of the voltage.

Further, the reset signal RS shown in FIG. 8 is generated from the detection value _VUV signal representing the U-phase and V-phase line voltage via the comparator 35 and the one-shot multicircuit. This reset signal pulse is generated at the zero-crossing point when the rise of V _UV signal, digital integrating circuit 37 is reset by this signal. The integrating circuit 37 digitally integrates the primary angular frequency command ω1 ^* , which is the output of the adder 9 in FIG. 6, and outputs a U-phase and V-phase line voltage phase θ _UV . The function table ROM 38V stores a sin (θ _UV -5π / 6) function. The function table ROM 38U receives the phase θ _UV of the line voltage as an address input, outputs a sine wave signal delayed by 30 ° phase, and passes through a D / A converter 34U having the phase voltage amplitude command as a reference voltage. The U-phase instantaneous phase voltage V _U is output.

Similarly, the function table ROM 38V receives the phase θ _UV of the line voltage as an address input, outputs a sine wave signal delayed by 150 ° phase, and passes through a D / A converter 34V using the phase voltage amplitude command as a reference voltage. Thus, the V-phase instantaneous phase voltage V _V is output. The W phase voltage is obtained from the U phase voltage V _U and the V phase voltage V _V.

As described above, the voltage detection method as shown in FIG. 7 makes it possible to detect the inverter output voltage without using a measurement transformer, detection distortion due to magnetic saturation, detection error near the zero cross point, etc. Can solve the problem. Further, since the phase voltage is detected based on the line voltage, the phase voltage can be accurately detected regardless of what PWM gate signal is given.
JP 62-185594 A (page 2-4, Fig. 1-3)

  The above method has the following advantages, but has the following problems.

  (1) Although the fundamental component of the output voltage can be detected, an accurate output voltage within one PWM carrier cycle cannot be detected. Therefore, it is not suitable for high-speed control that can cope with high-speed response.

  (2) Since the output voltage of the inverter circuit and the PWM gate signal are used without directly detecting the output voltage of the inverter circuit, the voltage drop due to the on-resistance of the semiconductor element and the voltage change during the transient response can be considered. Not.

  Therefore, the object of the present invention is to enable accurate output voltage detection within one PWM carrier cycle, and to perform high-accuracy voltage detection in consideration of the voltage drop due to the ON resistance of the semiconductor element and the voltage change during transient response. It is to do.

In order to solve such a problem, in the invention of claim 1, in the AC voltage detection system of the power conversion circuit controlled based on the comparison result between the control signal and the carrier and converting AC to DC or DC to AC,
An integrating means for integrating the AC side pulse output voltage and the reference voltage of the power conversion circuit; and a measuring means for measuring the time required to integrate the integration amount of the AC side pulse output voltage with the reference voltage. The AC side pulse output voltage within one cycle is detected.

  In the invention of claim 1, during the period in which the AC pulse voltage is output within one cycle of the carrier, the first signal proportional to the AC side pulse output voltage is integrated by the integrating means, and the AC side From the time when the pulse output voltage becomes zero, the integration value by the integration means is further integrated with a reference voltage having a polarity opposite to that of the first signal. From the time when the output voltage becomes zero, the integration value becomes zero. The AC side pulse output within one cycle of the carrier is calculated from the measurement time, the ratio of the AC side pulse output voltage to the first signal, the voltage value of the reference voltage, and the carrier cycle. The voltage can be detected (invention of claim 2).

  In the first aspect of the invention, it is possible to detect the AC side pulse output voltage within one cycle of the carrier using either one of the DC sides of the power conversion circuit as a reference potential (the third aspect of the invention).

  Further, in the first aspect of the invention, when the carrier is a symmetrical triangular wave, the first signal proportional to the AC side pulse output voltage is integrated by the integrating means during the half cycle of the carrier, and the half cycle of the carrier is obtained. Alternatively, from the time when one cycle of the carrier ends, the integration value by the integration means is further integrated with a reference voltage having a polarity opposite to that of the first signal, and the integration value becomes zero after the reference voltage is input. The AC side pulse output within one cycle of the carrier is calculated from the measurement time, the ratio of the AC side pulse output voltage to the first signal, the voltage value of the reference voltage, and the carrier cycle. The voltage can be detected (invention of claim 4).

  Furthermore, in the first aspect of the present invention, when the control signal is equal to or lower than a predetermined value, the first signal proportional to the AC side pulse output voltage is integrated by the integrating means during a plurality of predetermined cycles of the carrier. After the completion of the multiple carrier period, the integration value by the integrating means is further integrated with a reference voltage having a polarity opposite to that of the first signal, and the integration value becomes zero from the time when the integration with the reference voltage is started. AC time pulse output voltage within one cycle of the carrier is measured from the measured time, the ratio of the AC side pulse output voltage to the first signal, the voltage value of the reference voltage, and the carrier cycle. Can be detected (the invention of claim 5).

  According to the present invention, the AC side pulse output voltage within one carrier cycle of the power conversion circuit can be detected with high accuracy including voltage fluctuation, voltage drop due to on-resistance of the semiconductor element, and voltage change during transient response. . As a result, there is an advantage that high-response and high-performance driving can be realized in motor driving.

  According to the invention of claim 3, since common mode noise when detecting the AC side pulse output voltage is suppressed, it is possible to detect the voltage with high accuracy.

  Furthermore, according to the invention of claim 4, since the AC side pulse output voltage can be detected every half cycle of the carrier, the detection can be made a high-speed response.

  Furthermore, according to the fifth aspect of the present invention, it is possible to detect the voltage with higher accuracy when the motor is driven at a low speed.

  FIG. 1 is a diagram illustrating a first principle of the present invention. Vun in FIG. 1 indicates a voltage between the U-phase output terminal of the inverter and the N potential of the DC intermediate voltage, and T indicates a carrier cycle.

  Here, for example, when a voltage is generated at the U-phase output terminal, a detection signal proportional to the output voltage is integrated. Then, when the output voltage becomes zero, the integrated value is further integrated with a reference voltage having a polarity opposite to that of the detection signal. At this time, since the reference voltage has a polarity opposite to that of the detection signal, the integral value decreases. Then, a time t1 from when the output voltage becomes zero until the integral value becomes zero is measured.

  At this time, the value of the integration value arrival point V1 is expressed as in equation (1), where Vun is the value of the detection signal proportional to the instantaneous value of the U-phase output voltage of the inverter and τ is the integration time constant. It is.

From the equation (1), a value proportional to the total sum of the U-phase output voltages within one carrier cycle is expressed as the following equation (2).

  When the value of equation (2) is divided by one carrier period T, a value proportional to the average output voltage within one carrier period is obtained. If a value proportional to the average output voltage within one carrier cycle is Vunave, this is expressed as the following equation (3).

  V1 in the above equation (3) is expressed by the following equation (4) when the reference voltage is Vref and the discharge time is t1 from the operation at the time of discharge.

  Substituting equation (4) into equation (3) yields equation (5) in equation (5).

  From the above equation (5), it can be seen that the average output voltage Vunave within one carrier cycle can be calculated if the reference voltage Vref, the discharge time t1 and the carrier cycle T are known. This voltage Vunave is a value proportional to the average output voltage within one carrier cycle, and the actual voltage value (Vunave (real) is obtained by multiplying Vunave by the ratio (= k) to the actual value as follows (6 ).

Vunave (real) = k × Vunave (6)
Therefore, the actual voltage value is a value represented as the equation (6).

  In FIG. 1, the discharging operation of the integrator is started when the output voltage becomes zero. However, as shown in FIG. 2, after integrating all voltage values for one carrier cycle, the next carrier cycle Even if the discharge is started from the start time, the average output voltage within one carrier cycle can be calculated in the same manner.

  FIG. 3 shows an example in which an average voltage for each carrier cycle of the line voltage is obtained by using an integral AD (analog / digital) converter. In the case of a line voltage, as shown in FIG. 3, it may occur multiple times (generally twice) within one carrier period. Therefore, as shown in FIG. 2, the charging period and the discharging period of the integrator are repeated every other carrier period. During the charging period of the integrator shown in FIG. 3, the detection signal Vuv1 proportional to the line voltage is charged by the integrator. Then, the integrator is discharged with the reference voltage from the time when the next carrier cycle starts (time tA in FIG. 3). Thereafter, as in the case of the phase voltage, the average value of the line voltage within one cycle of the carrier can be calculated by substituting each value of the above equation (5) with the value at the time of the line voltage.

  FIG. 4 is a configuration example of a detection circuit that detects a phase voltage within one carrier cycle.

  In FIG. 4, reference numeral 21 denotes a circuit for outputting a signal necessary for calculating the U-phase output voltage average value, and 31 and 41 are V-phase and W-phase circuits as in the case of 21. Since the basic operations of 21, 21, and 41 are the same, the circuit 21 will be described below.

  First, the voltage dividing circuit 22 generates a signal (corresponding to Vun in FIG. 1) proportional to the voltage between the U-phase output voltage and the direct current n potential. The comparator 26a compares the output value of the voltage dividing circuit 22 with the zero level, and generates a signal indicating whether or not the output voltage of the voltage dividing circuit 22 is generated. Based on the output signal of the comparator 26a, the arithmetic processing unit 50 generates a signal (cont24a) for controlling on / off of the analog switch 24a. Specifically, the cont 24a outputs an on signal when there is an output voltage of the voltage dividing circuit 22, and outputs an off signal when there is no output voltage of the voltage dividing circuit 22.

  On the other hand, the reference voltage generation circuit 23 generates a reference voltage (corresponding to Vref) when discharging the integration value of the integration circuit 25. The analog switch 24b is ON / OFF controlled by a control signal (cont24b). As the cont 24b, an inversion signal of the cont 24a (corresponding to FIG. 1) or a signal generated as a signal synchronized with the carrier cycle based on the output of the triangular wave generation circuit 15 (corresponding to FIG. 2) can be used. . With this configuration, when there is an output voltage of the voltage dividing circuit 22, the analog switch 24a is turned on, and Vun, which is the output of the voltage dividing circuit 22, is integrated by the integrating circuit 25 (FIG. 1 or FIG. 2). Charging period operation).

  Next, when Vun becomes zero, or when the carrier within the charging period ends, the analog switch 24b is turned on, and a reference voltage (Vref) having a polarity opposite to that of Vun is integrated by the integrating circuit 25. Since Vref is opposite in polarity to Vun, the operation is an operation in which the integral value decreases (discharges). The comparator 26b compares the output value of the integration circuit 25 with a zero level, and generates an output signal when the output of the integration circuit becomes zero. Using the signals of the comparators 26a and 26b and the signal of the triangular wave generating circuit 15, the discharge time (corresponding to t1 in FIG. 1) of the integrating circuit is measured by the measuring device 51a in the arithmetic processing unit 50. Thereby, the average value (Vunave) of the phase voltage within one carrier period shown in the above equation (5) can be calculated.

  In the above method, the detection value can be calculated once every two carrier cycles due to the discharge time of the integration circuit, and the voltage value for one carrier cycle within the discharge time is ignored. When the carrier frequency is higher than that, the effect is not so much, and it is considered that the carrier frequency can be sufficiently used.

  As a countermeasure, two identical circuits are prepared as shown in FIG. 5, and one of the integration circuits calculates the detection value alternately by using the other integration circuit as the discharge period during the charging period. The average output voltage for each period can be calculated for each carrier period.

  As described above, by detecting the output voltage of the inverter, the average output voltage per carrier cycle of the inverter using the carrier modulation method is changed in the input voltage, the voltage drop due to the on-resistance of the semiconductor element, and the transient response. It becomes possible to detect with high accuracy including voltage change of time. As a result, high-response and high-performance driving can be realized in motor driving.

  Note that the present invention is not limited to the inverter, and the AC side voltage of the converter can be detected in the same manner.

  FIG. 9 shows a second embodiment of the present invention, which is a configuration example of a detection circuit for detecting a three-phase line voltage.

  This power conversion circuit and detection circuit include a three-phase commercial power source 1, a three-phase full-wave rectifier circuit 2, a smoothing capacitor 3, a PWM inverter 4, an induction motor 5, a gate signal generating means 45, and carrier synchronization. Signal generating means 53, U-V line voltage detecting circuit 70, voltage dividing circuit 61, subtracting means 62, V-W line voltage transmitting circuit 80, W-U line voltage detecting circuit 90, And an arithmetic processing means 54.

  The U-V line voltage detection circuit 70 includes reference voltage generation means 71, switches 72a, 72b, 73a, 73b made of analog switches, integration circuits 74a, 74b, and comparators 75a, 75b. Yes. The reason why two sets of integrating circuits are provided in this way is to detect voltages alternately as in the configuration of FIG. The V-W line voltage detection circuit 80 and the W-U line voltage detection circuit 90 have the same configuration as the U-V line voltage detection circuit 70. Further, the arithmetic processing means 54 is provided with a measuring instrument 55 which is partially formed.

In the above configuration, the point provided with the carrier synchronization signal generation unit 53, the point provided with the subtraction unit 62, and the comparator 26a shown in FIG. 4 directly connected to the voltage dividing circuit 22 are omitted. 4 and 5 except that the reference voltage generation means 71 generates reference voltages of + Vref and -Vref as positive and negative reference voltages. A gate signal generation unit 45 including a triangular wave carrier generation unit 47 and a voltage command value generation unit 48 outputs a gate signal to the PWM inverter 4 and supplies a carrier signal to the carrier synchronization signal generation unit 53. The carrier synchronization signal generating means 53 generates a carrier cycle start signal and a carrier cycle intermediate signal of the pulse signal synchronized with the start time and the intermediate time point of the triangular wave carrier signal, and supplies them to the arithmetic processing means 54.

  The operation of the U-V line voltage detecting means 70 will be described below with reference to FIG.

  The voltage dividing circuit 61 divides the U, V, and W phase output voltages of the PWM inverter 4 based on the negative potential of the capacitor 3. Further, the subtracting means 62a subtracts the voltage of the voltage dividing circuit 61b from the voltage dividing circuit 61a, and outputs the voltage obtained by dividing the line voltage of the U-V phase. Similarly, the subtraction means 62b and 62c output values obtained by dividing the V-W line voltage and the W-U line voltage, respectively.

  Since the triangular wave carrier in the circuit of the second embodiment is a symmetric triangular wave carrier, the output voltage has a symmetrical waveform with respect to the intermediate point of the carrier period as shown in the U phase voltage and V phase voltage waveforms in FIG. ing. The same applies to the W-phase voltage. Therefore, when the duty ratio in PWM control is other than 100% or 0%, any phase of the PWM inverter outputs a high level voltage at the middle point of the carrier. Therefore, the line voltage of each phase is 0 V at the intermediate point of the carrier as shown in the output voltage waveform of the subtracting means 62a in FIG. The carrier synchronization signal generation means 53 generates a pulse voltage signal at timings synchronized with the peaks and valleys of the triangular wave carrier, and is a carrier cycle start signal and a carrier cycle intermediate signal shown in FIG. The arithmetic processing unit 54 recognizes the carrier cycle start time and the carrier cycle intermediate time point when the pulse voltage of each of the signals is at a high level.

  First, the operation of the circuit including the switches 72a and 73a and the integrating circuit 74a when the carrier cycle start signal becomes high level is as follows.

  The arithmetic processing means 54 outputs a signal for controlling the switches 72a and 73a, and connects the output of the subtracting means 62a to the integrating circuit 74a. Specifically, this control signal is continuously ON from the start of the carrier cycle to the middle point of the carrier regardless of the level of the line voltage. On the other hand, the output of the switch 73a has a high impedance. The output voltage waveform of the integrating circuit 72a through the subtracting means 62a and the switches 72a and 73a at this time is shown in the section of the carrier half cycle a in FIG.

  Next, the operation of the circuit including the switches 72a and 73a and the integrating circuit 74a when the carrier cycle intermediate signal becomes high level is as follows.

  If the output of the comparator 74a at this time causes the output of the integrating circuit 74a to be a positive voltage, the arithmetic processing means 54 controls the switch 73a to control the negative reference voltage (− Vref) is connected to the integrating circuit 74a. Conversely, if the output of the integrating circuit 74a is a negative voltage, the positive reference voltage (+ Vref) from the reference voltage generating means 71 is connected to the integrating circuit 74a to integrate The output of the circuit 74a is brought close to 0, the integration of the output voltage of the subtracting means 62a is terminated, and the integration with a voltage having a polarity opposite to that of the output voltage is started.

  The arithmetic processing means 54 starts counting up the measuring instrument 55 and monitors the output of the comparator 75a. On the other hand, the output of the switch 72a is set to high impedance. The output voltage waveform of the integrating circuit 74a through the subtracting means 62a and the switches 72a and 73a at this time is shown in the section of the carrier half cycle b in FIG.

  The operation of the circuit including the switches 72b and 73b and the integrating circuit 74b at this time is as follows.

  The arithmetic processing means 54 outputs a signal for controlling the switch 72b, connects the output of the subtracting means 62a to the integrating circuit 74b, and starts integration in the integrating circuit 74b. The switch 72b is also continuously turned ON for a half cycle from the intermediate point of the carrier to the end time of the carrier.

  On the other hand, the switch 73b has a high impedance during this period. Similarly, the output voltage waveform of the integrating circuit 74b via the switches 72b and 73b is shown in the section of the carrier half cycle b in FIG.

  Next, in the integrating circuit 74a, when the output becomes zero voltage due to the integration of the reference voltage having the opposite polarity, and the sign of the output of the comparator 75a is switched, the arithmetic processing means 54 controls the switch 73a to control the integrating circuit 74a. A ground potential is connected to the input so that the output of this integrating circuit is kept at 0V. At the same time, the count-up of the measuring instrument 55 is stopped, and the voltage between the U and V lines from the start of the carrier cycle to the middle point of the carrier cycle is determined from the counted value in the same manner as in the first embodiment shown in FIGS. Get the average value of.

  Next, when the carrier cycle start signal becomes high level, the operation of the circuit including the switches 72a and 73a and the integration circuit 74a is the same as the operation already described.

  On the other hand, in the switches 72b and 73b and the integration circuit 74b, the integration with the reference voltage having the opposite polarity to the output of the integration circuit is started, and the time until the integration circuit reaches 0 voltage is measured by the measuring device 55. In the same manner as described above, the average value of the line voltage of the carrier half cycle from the middle point to the end of the carrier cycle is obtained.

  In this way, by integrating the line voltage, the voltage input to the integrating circuit can be switched to the reference voltage when the output of the voltage dividing circuit 61a is approximately 0 V. Therefore, switching is performed with the voltage applied to the switch. Noise generated when the

  Since the voltage measured with reference to the negative side of the DC intermediate capacitor 3 that is the input DC voltage to the PWM inverter 4 is adjusted by the voltage dividing circuit 61, the line voltage is generated by the subtracting means 62. In addition, it is possible to reduce common mode noise applied to the detection circuits 70, 80, and 90 rather than measuring the line voltage.

  Accordingly, with regard to the V-W line voltage and the W-U line voltage, the V-W line voltage detection circuit 80 and the W-U line voltage detection configured in the same manner as the U-V line voltage detection circuit 70 are used. The circuit 90 obtains an average voltage of the output voltage of the PWM inverter 4 in a carrier half cycle unit.

  FIG. 11 shows a third embodiment of the present invention, which is a configuration example of a detection circuit for detecting a three-phase line voltage.

  This power conversion circuit and detection circuit include a three-phase commercial power source 1, a three-phase full-wave rectifier circuit 2, a smoothing capacitor 3, a PWM inverter 4, an induction motor 5, a gate signal generating means 45, and carrier synchronization. Signal generating means 53, U-V line voltage detecting circuit 70a, voltage dividing circuit 61, subtracting means 62, V-W line voltage transmitting circuit 80a, W-V line voltage detecting circuit 90a, And an arithmetic processing means 58.

  The gate signal generating unit 45 includes a comparator 46, a triangular wave carrier generating unit 47, and a voltage command value generating unit 48. The arithmetic processing means 58 is provided with a measuring instrument 59 as a part thereof.

  The circuit configuration of FIG. 11 is different from the circuit configuration of FIG. 9 in that information on the primary frequency of the output voltage of the PWM inverter 4 possessed by the voltage command value generation means 48 is input to the arithmetic processing means 58. It is.

  Next, the operation of the U-V line voltage detection circuit 70a will be described with reference to FIG.

  Since the operation of the circuit including the switches 72a and 73a and the integrating circuit 74a when the carrier cycle start signal becomes high level is the same as the circuit of the second embodiment shown in FIG. 9, the description thereof is omitted.

  When the primary frequency is lower than the predetermined frequency, the arithmetic processing means 58 changes the integration period in the integration circuit 74a from the half cycle in the normal operation described above to, for example, two carrier cycles as shown in the figure. Set.

  The output waveform of the integrating circuit 74a of FIG. 12 is shown. The arithmetic processing means 58 stops the integration from the subtracting means 62a after the elapse of two carrier cycles, starts the integration at the reference voltage, and counts up the measuring instrument 59, similarly to the circuit of the second embodiment. Start. At the same time, the switches 72b and 73b are controlled to start integration in the integration circuit 74b. The integration period at this time is also set to two carrier cycles, and the operation thereof is the same as that of the second embodiment, and thus description thereof is omitted.

  On the other hand, the operation of the switches 72a and 73a when the voltage integrated by the integration circuit 74a is integrated with the reference voltage to become zero voltage is the same. The value counted by the measuring instrument 59 is an integrated value of the output voltage in two carrier cycles. Thus, the line voltage for one carrier cycle is obtained in the same manner as the circuit of the first embodiment.

  In general, when a power conversion circuit that performs PWM control drives an electric motor, if the primary frequency to the electric motor is reduced, the output voltage also decreases, and therefore a detection circuit for measuring the line voltage Then, the pulse width in the integration period becomes narrow. Further, since the noise is superimposed on the signal when the switches 72a, 72b, 73a, 73b used in the detection circuit are turned on or off, the S / N ratio is also lowered, but the implementation shown in FIG. In the form circuit, by setting the measurement cycle between two carrier cycles, the average voltage when the output voltage becomes low can be obtained more accurately while avoiding the influence of noise.

First principle explanatory diagram of the present invention Explanatory drawing explaining the modification of FIG. Second principle explanatory diagram of the present invention The block diagram which shows 1st Embodiment of this invention The block diagram which shows the modification of FIG. Configuration diagram showing a conventional example Detailed configuration diagram showing the voltage detection circuit of FIG. Waveform diagram of each part for explaining the operation of FIG. The block diagram which shows 2nd Embodiment of this invention Each part waveform diagram explaining the operation of FIG. The block diagram which shows 3rd Embodiment of this invention Waveform diagram of each part for explaining the operation of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Commercial power supply, 2 ... 3-phase full wave rectifier circuit, 3 ... Smoothing capacitor, 4 ... PWM (pulse width modulation) inverter, 5 ... Induction motor, 15 ... Triangular wave generation circuit, 21, 21a, 21b ... U-phase voltage detection Signal generation circuit, 22 ... Voltage division circuit, 23 ... Reference voltage generation circuit, 24a, 24b ... Analog switch, 25 ... Integration circuit, 26a, 26b ... Comparator, 31, 31a, 31b ... V-phase voltage detection signal generation Circuit, 41, 41a, 41b ... W-phase voltage detection signal generation circuit, 45 ... Gate signal generation means, 46 ... Comparator, 47 ... Triangular wave carrier generation means, 48 ... Voltage command value generation means, 50 ... Arithmetic processing device, 51a to 51c ... measuring instrument, 53 ... carrier synchronization signal generating means, 54, 58 ... arithmetic processing means, 55, 59 ... measuring instrument, 61 ... voltage dividing circuit, 62 ... subtracting means, 70, 70a ... U-V Inter-voltage detection circuit 71... Reference voltage generating means 72 a, 72 b, 73 a, 73 b..., 74 a, 74 b ... integration circuit, 75 a, 75 b ... comparator, 80, 80 a. 90, 90a ... W-U line voltage detection circuit.

Claims (5)

In the AC voltage detection method of the power conversion circuit that is controlled based on the comparison result between the control signal and the carrier and converts AC to DC or DC to AC,
An integrating means for integrating the AC side pulse output voltage and the reference voltage of the power conversion circuit; and a measuring means for measuring the time required to integrate the integration amount of the AC side pulse output voltage with the reference voltage. An AC voltage detection method for a power conversion circuit, wherein an AC side pulse output voltage within one cycle is detected.   During the period in which the AC pulse voltage is output within one cycle of the carrier, the first signal proportional to the AC side pulse output voltage is integrated by the integrating means, and from the time when the AC side pulse output voltage becomes zero. The integration value by the integration means is further integrated with a reference voltage having a polarity opposite to that of the first signal, and the time from when the output voltage becomes zero until the integration value becomes zero is measured. The AC side pulse output voltage within one cycle of the carrier is detected from the ratio of the AC side pulse output voltage to the first signal, the voltage value of the reference voltage, and the carrier cycle. Item 2. An AC voltage detection method for a power conversion circuit according to Item 1.   2. The AC voltage detection system for a power conversion circuit according to claim 1, wherein one end of the DC side of the power conversion circuit is set as a reference potential.   When the carrier is a symmetric triangular wave, a first signal proportional to the AC side pulse output voltage is integrated by an integrating means during the half cycle of the carrier, and when the half cycle of the carrier or one cycle of the carrier is completed The integration value by the integration means is further integrated with a reference voltage having a polarity opposite to that of the first signal, and the time from when the reference voltage is input until the integration value becomes zero is measured. The AC side pulse output voltage within one cycle of the carrier is detected from the ratio of the AC side pulse output voltage to the first signal, the voltage value of the reference voltage, and the carrier cycle. Item 2. An AC voltage detection method for a power conversion circuit according to Item 1. When the control signal is equal to or less than a predetermined value, the first signal proportional to the AC side pulse output voltage is integrated by integrating means during a plurality of predetermined periods of the carrier, and the first signal is integrated after the end of the plurality of carrier periods. And further integrating the integration value by the integration means with a reference voltage having a reverse polarity, and measuring the time from the start of integration with the reference voltage until the integration value becomes zero, the measurement time, 2. The AC-side pulse output voltage within one carrier cycle is detected from the ratio of the AC-side pulse output voltage to the first signal, the voltage value of the reference voltage, and the carrier cycle. AC voltage detection method for the power conversion circuit described in 1.

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