SU1439586A1 - Frequency-type multiplier - Google Patents

Abstract

The invention relates to computing technology and can be used in the construction of automated control systems for various technological processes. The circuit of the invention is an increase in the frequency multiplication accuracy. The device contains multiplying-dividing blocks 1, 6, 11 with the corresponding information inputs and outputs and functional connections. In the device, period T determines the averaging interval, and although an increase in this interval leads to the need to increase the capacity of multipliers-dividers blocks, however, the multiplication accuracy is improved at non-multiple frequencies F ,, F and F, as well as with the instability of frequencies E and F. The output pulse sequence is insensitive to input instability often , -Tokyo device performs the triple averaging them over the time interval T "by accumulating the total number of pulses in the counters reprographic of fission-blocks of 2 yl. (L with

Description

/.

with

CD SP 00

about:

1

The invention relates to computing and can be used in the construction of automated computerized control systems for various technological processes.

The circuit of the invention is the higher accuracy of frequency multiplication.

In FIG. 1, a TK of Ezana is a block diagram of a frequency multiplying device | on ilg 2 the multiplication-division scheme is functional. block

The device contains the first mono-dagger block 1 with the first one, the second and the third information - input and output 5. the second multiply-separating unit 6 with the first, second and third information gates and outputs 10 and the third - case; 5: solid bhgk 11 with the first BglMz second and third information of the s-12-14 and press 15 with the corresponding dim dm link

Each multiplying-delktile block contains a trigger 16, from the first to the fourth elements AND 17-20, from the first 310 fourth formrs 21-24 pulses, from the first to the fourth c-qeT4Hi-: TT 25-28, the first and the second evil the cops / 9 and 30 delays, first and second), hf; sjiei -seHTOB And 31 and 32 and from the first to the next: etny elements SH-33-35 with the corresponding links: many

Frequency monochrome device works as follows

The first information input 2 of the multiplying-dividing block 1 is received and; clock frequency v; At the second information 3 multiplying-dividing block 1 post ™

The frequency pulses F, which are the first one, fall. {multiply On the third information inputs of all three multiply dividing blocks 1, 6 and 11 are received im: pulses of auxiliary (scale) sequence with frequency Ff, o

In accordance with the algorithm of working on the code of the first multiplying-division block 1, during one period of the auxiliary frequency of the FORT mode and the sequence of the pulse number

F.

(one)

 Lg

The impulses with the frequency F, are then sent to the first information input 7 of the second module 7-1 separating block b, to the second information input 8 of which impulses are received with the frequency Fg 5 which is the second multiplier. At the output of the second multiplier: of the experimental unit 6 a pulse sequence is formed by frequency

(ABOUT

Tnf

(2)

or taking into account the expression (1)

F. (3)

10 T2F

I. ,, J., 2

Next, the pulses with frequency F, o arrive at the second information input 13 of the third multiple-division unit 115 to the first 12 information input 12 of which clock frequency F is received. At the third multiplicatively-splitter unit 11, it appears the output of the device5 generates an impulse sequence of the frequency

F,

F

out

o

whether taking into account the expression (3)

F. Fi

F

You v

t.

F, J 2

F

(four)

(five)

The frequency F |., Included in the formula (5) in the form of a proportional coefficient, determines the time scale of the output scroll sequence. When you select the scale c, the unit frequency F the output frequency of the device will be equal to

frequency of input pulse sequences "

F F F

 - (2

(6)

45

50

55

The period T determines the averaging interval and although an increase in this interval necessitates an increase in the capacity of the counters of multiply-dividing blocks, it nevertheless improves the accuracy of multiplication at non-multiple frequencies F, F and F as well as the instability of the frequencies F and Fgo. The output pulse sequence is insensitive to instability of input frequencies, since the device performs their threefold averaging over the time interval T "by accumulating the total number of pulses in the multiplying-dividing counters yy blocks

Claims (1)

Invention Formula The frequency multiplying device contains the first multiplying-divisor unit, which includes a trigger, first, second, third, and fourth elements AND, first, second, third, and fourth pulse shapers, first, second, third, and fourth counters, first and second The second delay elements, the first and second groups of elements are And, the first, second and third elements of the RShI, the first inputs of the first and fourth elements of And are connected to the first information input of the block, the first inputs of the second and third elements And are connected to the second The information input of the block, the sync input Isac1-1I of the trigger is connected to the third information input of the block, the direct output of the trigger is connected to the second input of the first and third elements AND and the input / house of the second sc-shuli, the output of which is connected to the first input of the first element I-fflH and the reset input of the third counter, the inverse output, of the trtsgger is connected to the second inputs of the second and fourth electrons AND AND and the input of the first imager ig-shul-VSE whose output is connected to the first 13IND of the third OR element and the reset input is second About the counter, the code of the first element I is connected to the counting input of the first counter, the overflow output of which is connected to the second input of the first element I, PI, the output of the second element I is connected to the countable input of the second counter, you go, the stroke of the third element I is connected to the counting the input of the third counter, the output of the fourth element I is connected to the counting input of the fourth counter, the overflow output of which is connected to the second input of the third SHS element, the outputs of the first and third OR elements are connected to the inputs of the second OR element, Exit coupled to an output block E1SH first element output coupled to an input of the third pulse shaper 0 0 five five the output of which is connected to the reset input of the first counter and the input of the first delay element, the output of which is connected to the first inputs of elements AND of the first group, whose codes are combined respectively with the installation inputs of the first counter, the output of the third element OR is connected to the input of the fourth pulse form, the output of which is connected to the reset input of the fourth counter and the input of the second delay element, the output of which is connected to the first 5 inputs of the elements-And the second group, the outputs of which are connected respectively to the device The starting inputs of the fourth counter, the inverse bit outputs of the second counter are connected respectively to the second inputs of the elements And the nepBOfi groups, the inverse bit outputs of the third counter are connected respectively to the second inputs of the elements of the second group, characterized by the fact that frequency slice, the second and third multiply-dividing blocks are entered into it, and the first information input of the first multiplier-dividing block is connected to the first information input of the third multiply The flax divider unit and the device's input frequency reference, the second information input of the first multiplier-divider unit is connected to the first information input of the device, the third information inputs of the first, second and third multiplier-separating blocks are connected to the scale input of the device, the code of the first multiplier - an incremental block is connected to the first information input of the second multiplying-dividing block, the second information input of which is connected to the second information input of the device, output The second multiplying-dividing block is connected. with the second information input of the third multiplying-dividing block, the output of which is the output of the device. 0 five 0