SU1718233A1 - Device to determine a random process median - Google Patents

Abstract

This invention relates to specialized computing devices and may be used in the processing of random processes. The purpose of the invention is to improve accuracy. The device for determining the median of the random process contains a block 1 of comparison, a Schmitt trigger 2, two elements AND 3.4, a generator of 5 clock pulses, two counters 6, 7, an element OR 8, two registers 9, 10, a block 11 of subtraction, a element 12 of delay, accumulating adder 13, dividing unit 14 and code converter 15 - voltage interconnected functionally. Accuracy improvement is achieved by eliminating the sign uncertainty of the calculated median value, 3 Il.

Description

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This invention relates to specialized computing devices and may be used in the processing of random processes.

A device for determining the median is known, comprising a comparison unit, a Schmitt trigger, five AND elements, an OR element, an NE element, a trigger, a clock generator, and a code-voltage converter with corresponding connections 1.

A disadvantage of the known device is low accuracy. This is because the sign of the calculated median is determined by the sign of the difference between the instantaneous value of the signal and the current value of the median, which can lead to a change in the sign of the true value of the median.

The closest to the claimed is a device for determining the median of a random process, containing a comparison unit, Schmitt trigger, seven AND elements, two OR elements, two NOT elements. two threshold elements, two reversible counters, an AND block, two triggers, a pulse generator, and a time interval shaping unit with corresponding links 2.

A disadvantage of this device is also low accuracy, since it can change the median sign relative to the true value, since the sign of the calculated median is determined by the sign of the difference between the instantaneous value of the random signal and the current value of the median.

The purpose of the invention is to improve accuracy.

The goal is achieved by the fact that a device for determining the median of a random process contains a Schmitt trigger, two AND elements, two counters, an OR element, a clock generator, a code-voltage converter, a comparison unit. The first information input of the comparison unit is the information input of the device, and the second one is connected to the output of the code converter - voltage. The output of the comparison unit is connected to the Schmitt trigger input, the direct and inverse outputs of which are connected to the first inputs of the first and second I elements, respectively. Two registers are entered in the device, a delay element, a subtractor, an accumulator, and a division block. The output of the clock generator is connected to the second inputs of the first and second elements And, the outputs of which are connected to the counting inputs of the first and second counters, respectively, the overflow outputs of which are connected respectively to the first and second inputs

element OR. The output of the OR element is connected to the clock inputs of the first and second registers and through the delay element with the reset inputs of the first and second counters and

with the clock input of the accumulating adder, the information output of which is connected to the input of the divisible division block. The input of the division unit is the input value 2 of the device, and the output of the division unit

connected to the information input of the converter code - voltage, the sign input of which is connected to the sign output of the accumulating adder, m higher bits (2m + 1 is the number of specified quantization levels) of the first and second counters are connected to the information inputs of the first and second registers, respectively. The outputs of the latter are connected respectively to the inputs of the reduced and

a subtracted subtraction unit, the information and sign outputs of which are connected respectively to the information and sign inputs of the accumulating adder.

. FIG. 1 shows a block diagram of a device for determining the median of a random process; in fig. 2 shows an example of a block diagram of a subtractor; in fig. 3 - an example of the structural scheme

accumulating adder /

A device for determining the median of a random process contains a block 1 of comparison, a Schmitt trigger 2, the first 3 and second 4 elements And, a clock generator 5, the first

6 and second 7 counters, the OR element 8, the first 9 and second 10 registers, the subtraction unit 11, the delay element 12 accumulating the adder 13. the division unit 14, the code converter 15 is a voltage.

The subtraction unit (Fig. 2) contains a reference element 16, the first 17 and second 18 switches, and the subtractor 19.

The accumulating adder (Fig. 3) contains the comparison element 20, the first 21 and second 22 elements EXCLUSIVE OR, the first 23, the second 24 and the third. 25 switches, adder-subtractor 26.0-trigger27. register 28, the element is NOT 29 and the element is And 30. As the subtractor and the adder-compute-.

tatel can be used integrated circuit K 155 IPZ. All other units of the device are standard computing units.

The first input of unit 1 of comparison is the information input of the device, the output of unit 1 of comparison is connected to the input of Schmitt trigger 2, the direct output of which is connected to the first input of the first element 3 and the inverse to the first input

The second element is And 4. The second inputs of the first 3 and second 4 elements And are connected to the k output of the clock generator 5, the output of the first element I is connected to the counting input 6 of the first counter 6, the m most significant bits of which are connected to the information input of the first register 9, the output of which connected to the input of the decremented subtraction unit 11; The output of the second element I 4 is connected to the counting input of the second counter 7, whose higher bits are connected to the information input of the second register 10, the output of which is connected to the input of the subtracted block 11 Itani. The information and character outputs of subtraction unit 11 are connected to the informational and symbolic inputs of accumulating adder 13, respectively. The information output of accumulating adder 13 is connected to the input of divisible division unit 14, the divider output is fed to value 2. Output of divider 14 is connected to the information input of the converter 15, the code is the voltage, the sign input of which is connected to the sign output of the accumulator adder 13. The output of the converter 15, the code is the voltage that is the output of the device a second input unit 1 ..Vyhody overflow comparing the first b and second counters 7 are connected respectively to the first and second inputs of OR element 8; the output of which is connected to the input of the delay element 12 and to the clock inputs of the first 9 and second 10 registers. The output of the delay element 12 is connected to the clock input of the accumulating adder 13 and to the reset inputs of the first and second 7 counters.

In block 11 of the subtraction (Fig. 2), the input of the reduced and the input of the deductible are connected respectively to the first and second inputs of the comparison element 16, the first 17 and the second 18 switches. The outputs of the first 17 and second 18 switches are connected respectively to the inputs of the reduced and subtracted subtractor 19. The output greater than or equal to the reference element is the sign output of the subtractor, the output of the subtractor is the information output of the subtractor. The output is greater than and the output is less than the comparison unit 16 is connected respectively to the control inputs of the first 17 and second 18 switches.

In the accumulating adder 13 (FIG. 3), the output of the register 28 is connected to the first inputs of the comparison element 20, the second 24 and the third 25 switches. The information input of the device is connected to the second inputs of the comparison element 20, the second 24

and the third 25 switches. The outputs of the switches 24 and 25 are connected respectively to the first and second information inputs of the subtractor 26, the output of which is connected to the information input of the register 28 and is the information output of the accumulating adder 13. The sign input of the accumulating adder is connected to the first input of the second element EXCLUSIVE OR 22. with the second input of the first element EXCLUSIVE OR 21 and with the second input of the element AND 30. The output of the D-flip-flop 27 is connected to the second input of the second element EXCLUSIVE OR 22, the output of which is connected to the first input control mode of the summator-reader 26, with the control input of the first switch 23 and with the input of the element NOT 29. The output of the element is NOT connected to the second input of the control of the mode of the adder-subtractor 26 and to the first input of the element 30, whose output is connected to the second the input of the first switch 23. The output is less than the comparison element 20 connected to the control input of the third switch 25, the output is greater than or equal to the comparison element 20 connected to the control input of the second 24 switch and to the first input of the first element EXCLUSIVE OR 21, the output cat The op is connected to the first information input of the first switch 23. The output of the last, which is the sign output of the accumulating adder, is connected to the information input of the D-flip-flop 27, the clock inputs of which and the register 28 are the clock input of the accumulating adder.

The device works as follows.

In the initial state, all blocks are zeroed.

The random signal X (t) is applied to the first input of the comparator unit 1, where it is compared with the reference voltage Don, which is generated by the code-voltage converter 15. Since at the initial moment of time to, the voltage at the output of converter 15 is zero, then X (t0) is directly applied to the input of Schmitt trigger 2. For definiteness, let us assume that X (to) has a positive (negative) value, then at the forward (inverse) output of flip-flop 2 a logical signal 1 appears, which is fed to the first input of the AND 3 (4) element. The second inputs of the And 3 and 4 elements receive a signal from the output of the clock generator 5, the repetition period of which is longer than the correlation time of the random signal. Depending on the sign of X (t), the signal of the clock generator 5 is fed to the counting input of either counter 6 or counter 7, Each of the counters has n + m bits, and n-determines the dead zone of the device, am is the number of data bits of the converter The code is the voltage corresponding to the maximum iop.max value. When one of the counters 6 or 7 is filled at its overflow output, a signal is generated, coming through the OR element 8 to the clock inputs of registers 9 and 10. At the same time, the information with m most significant bits of counters 6 and 7 is written to registers 9 and 10 At the output of the subtraction unit 11, a value is generated that is proportional to the difference in the probabilities of the residence time of the random process above and below the value of Uon. Block output

The subtraction enters the accumulating adder, in which the correction value produced by the subtraction unit 11 is added (subtracted) to the current value. The code of the signal from the output of the accumulating adder is divided into two blocks AND division, the signal from the output of which is fed to the information input of the converter 15 code - voltage, sets the next value Uon. The value of Uon, corresponding to the median value, is set when the codes from the outputs of counters 6 and 7 are the same, i.e. when probably The sign of Xon exceeding the value of Uon coincides with the probability that X (t) is less than Uon. Thus, the device implements a median search algorithm using the half-division method. The delay of the element 12 is chosen sufficient to record the information in registers 9 and 10 and to carry out the process of subtraction in block 11. The signal from the output of the element

The 12 delays clocks the accumulating adder 13 and resets the counters B and 7 to the zero state, preparing the device for processing the next sample.

The subtraction unit (Fig. 2) operates as follows.

The signals of the decreasing A and the subtracted B are supplied respectively to the first and second inputs of the comparison element 16 and the switches 17 and 18 If AB, the values of A and B are input to the inputs of the reduced and subtracted subtractor 19, respectively. In and

A. Consequently, at the output of the subtractor 19, the information value AB is formed, and at the output, more or equal, of the comparison element 16 is the sign of the difference.

Accumulating adder (Fig. 3) works as follows. To the arrival of the next clock pulse at the output of the register 28 and trigger 27

the module is present and the sign of the accumulated number is A. The module of number B arrives at the second inputs of the comparison element 20 and the switches 24 and 25. The sign of the number B is fed to the first input of the AND element 30 and the second input

0 elements EXCLUSIVE OR 22. Accumulator adder implements the operation of algebraic accumulation. Consider the operation of the accumulating adder at different ratios between the modules and

5 values of A and B; Let A and B be of the same sign. 43 in this case, the output of the EXCLUSIVE OR 22 element will be a zero signal and the adder-subtractor 26 is switched to the arithmetic slope mode, and the switch 23 connects its second input to the output, to which the signal from the output of the element 30 arrives And, a single signal is output from the output of the element HE 29, therefore, the output signal of the element 30 repeats the sign signal of the number B.

Let A 0 and B 0, Then, at the output of the EXCLUSIVE OR 22 element, there is a single signal, which is the 0 key to the sign output of the adder, i.e. to the output of the switch 23. and the adder-subtractor 26 is switched to the subtraction mode. When lAl | B | through switches 24 and 25, the values of A and B are connected to the outputs of decreasing and subtracting, respectively. At the output of the EXCLUSIVE OR 21 element, there will be a single signal corresponding to the sign of the number A. At | A | | In the I adder-subtractor, the operator performs the operation | B) .- 1A |, and at the output of the EXCLUSIVE OR element 21 there will be a signal corresponding to the sign of the number B.

Let A 0 and B 0. The adder-calculator also operates in the subtraction mode. If A | 1B |, at the output of the EXCLUSIVE or 21 element, and consequently, at the sign output of the accumulating accumulator, there will be a single signal corresponding to the sign of the number B. At 1A B, at the output of the EXCLUSIVE OR 21 element there is a zero signal.

Comparison of the proposed technical

5 solutions with the prototype showed clear disadvantages of the prototype.

These disadvantages are the following: the sign of the calculated median is determined at a certain point in time by the sign of the difference between the value of the random process in

this point in time and the calculated median value. This leads to the fact that there are such moments when the sign of the median, calculated by the device, does not coincide with the true sign of the median, which leads to failure of the device, which reduces its reliability.

Application of the proposed technical solution allows eliminating malfunctions of the device and, consequently, increasing the reliability of operation, since the sign of the calculated median does not depend on the instantaneous values of the random signal and is determined by the result of statistical processing of the random signal.

The absence of malfunctions improves the accuracy of the device and the accuracy of the information at its output. Increased reliability compared with the base object allows using the device, for example, to control the equipment, to reduce the number of errors, which ultimately leads to a decrease in the cost of the equipment produced.

F o rmu l invention

A device for determining the random process median containing a Schmitt trigger, the first and second elements AND, the first and second counters, the OR element, the clock pulse generator, the converter code — the voltage whose output is the device output, and the comparison unit, the first information input which is the information input of the device, the second information is. The input input is connected to the output of the voltage converter, and the output is connected to the input of a Schmitt trigger, the direct and inverse outputs of which are connected to the first inputs of the first and second elements AND, respectively, characterized in that, in order to improve accuracy, the first and the second registers, the delay element, the subtraction unit, the accumulating adder and the dividing unit, the output of the clock generator connected to the second inputs of the first and second elements And, the output of the first element And connected to the counting input of the first count The outputs of the m most significant bits of which (- the number of specified quantization equations) are connected respectively to the information inputs of the first register, the output of the second element I is connected to the counting input of the second counter, the outputs m of the most significant bits of which are connected respectively to the information inputs of the second register whose clock input is connected to the clock input of the first register, the input of the delay element and the output of the OR element, the first and second inputs of which are connected respectively to the overflow outputs of the first the second counter, the inputs of which are set to zero, is connected to the clock input of the accumulating adder and to the output of the delay element; the sign input of which is connected to the sign output of the subtraction unit, the information output of the accumulating adder is connected to the input of the divisible division block, the input is divided which is a reference value input unit 2, block divider output coupled to an information input of the code converter - voltage sign input of which is connected to the output of the accumulator landmark ..

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Claims (1)

Claim A device for determining the median of a random process containing a Schmitt trigger, first and second AND elements, 30 first and second counters, an OR element, a clock generator, a code-voltage converter, the output of which is the output of the device, and a comparison unit, the first information input of which 35 is the information input of the device, the second information. The input input is connected to the output of the code-voltage converter, and the output is connected to the input of the Schmitt trigger, the direct and 40 inverse outputs of which are connected to the first inputs of the first and second elements And, accordingly, characterized in that, in order to increase the accuracy, ^ first and second registers, delay element, subtraction unit, accumulating adder and division unit, wherein the output of the clock generator is connected to the second inputs of the first and second elements And the output of the first element And is connected to the counting input of the first counter ka, the outputs of the m high bits of which (2 ^{t + 1} is the number of specified quantization equations) are connected respectively to the information inputs of the first register, the output of the second element And is connected to the counting input of the second counter, the outputs of the m high bits of which are connected respectively to the information inputs of the second register, the clock input of which is connected to the clock input of the first register, the input of the delay element and the output of the OR element, the first and second inputs of which are connected respectively to the overflow outputs of the first and of counters, the zero input of which is connected to the clock input of the accumulating adder and with the output of the delay element, the output of the first register is connected to the input of the reduced subtraction block, the input of the subtracted which is connected to the output of the second register, the information output of the subtraction block is connected to the information input of the accumulating adder, the sign input of which is connected to the sign output of the subtraction unit, the information output of the accumulating adder is connected to the input of the dividend division unit, the input of the divider of which is the input of setting the value 2 of the device, the output of the division unit is connected to the information input of the code-voltage converter, the sign input of which is connected to the sign output of the accumulating adder. FIG. Z