SU1552372A1 - Gray code counter - Google Patents

Abstract

The invention relates to automation, pulsed and computing technology and can be used to count pulsed signals. The purpose of the invention is to increase speed. The counter contains one auxiliary counting trigger on AND-OR-NOT elements, two odd counting triggers on AND-OR-NOT elements, and two even-counting trigger on AND-OR-NOT elements. The counting input of the counter in the Gre code is connected to the counting input of the auxiliary counting trigger. There is an entry for initial installation. The auxiliary counting trigger forms a single-shot T-flip-flop circuit with one memory element formed by two elements and one switching trigger formed by two elements. The outputs of the elements of the auxiliary T-flip-flop are connected to the inputs of the first counting flip-flop. The outputs of each counting trigger connected to the inputs of the subsequent counting trigger. The performance gain is achieved by accelerating bitwise transfer. 1 il.

Description

(21) 4342351 / 24-21

(22) 12.12.87

(46) 03/23/90. Bul № 11

(71) Leningrad Electrotechnical Institute named after V.I. Ulnova (Lenin)

(72) V.I.Varshavsky, V.B.Marakhovsky, N.M. Kravchenko and Yu.S.Tatarinov

(53) 621.37.322 (088.8)

(56) Designing microelectronic digital devices. / Ed. S.A.Mayorova. - M .: Sov.radio, 1977, p.170, Fig.5.16, p.172, Fig.5.17, p.168,

Fig.5.15.

USSR Author's Certificate No. 1492474, cl. H 03 K 23/18, 1987.

(54) COUNTER IN GRAY COLLE

(57) The invention relates to automation, pulsing and computing, and can be used to count pulsed signals. The purpose of the invention is to increase speed. The counter contains one auxiliary counting trigger on AND-MLI-elements, two odd-counting triggers on AND-OR-NOT elements, and two even-counting triggers on AND-OR-NOT elements. The counting input of the counter in the Gre code is connected to the counting input of the auxiliary counting trigger. There is an entry for initial installation. The auxiliary counting trigger forms a single-shot T-trigger circuit with one memory element formed by two elements and one switching trigger formed by two elements. The outputs of the elements of the auxiliary T-flip-flop are connected to the inputs of the first counting flip-flop. The outputs of each counting trigger connected to the inputs of the subsequent counting trigger. Performance gains are achieved by accelerating bitwise transfer. 2 Il.

from 9

(/

WITH

The invention relates to binary pulse counters, provides counting in binary code and Gre code, and can be used in computing, in particular in memory management schemes, in matching circuits of computing devices with controllable objects, etc.

 The purpose of the invention is to increase speed.

FIG. 1 shows a flowchart of the counter; in fig. 2 - time diagrams of his work.

The counter contains one auxiliary counting trigger 1, which is formed by elements AND-OR-HB 2-5, two odd counting triggers 6, which are formed by elements AND-OR NOT 7-Yu, and two even counting triggers 11, which are formed by elements AND-OR - NOT 12-15. The counting input 16 of the counter and the GRE code is connected to the counting input of the auxiliary counting trigger. The drawing shows one of the possible schemes for the initial installation of the meter having an input 17 for the initial installation. The auxiliary counting trigger forms the well-known one-cycle counting trigger circuit with a single memory element, which is formed by

Cr

SG

N:

I and 5 and one switching trigger, which is formed by elements 2 and 3. The outputs of elements 2-5 of the auxiliary counting trigger are connected to inputs 18-21 of the first odd estimated trigger 6. Outputs 22-25 of each odd counting trigger

6 are connected respectively to inputs 26-29 of the subsequent, odd counting HOI trigger 11, and outputs 30-33 of the even countable trigger 11 are connected respectively to inputs 18-21 of the subsequent odd counting trigger 6.

I

The odd counting trigger L b is a collection of two triggers formed by the elements

7 and 8, 9 and 10. Element outputs /

and 8 are connected respectively to the outputs 25 and 22 of the odd counting trigger 6, with the first inputs of the second groups of inputs of elements 10 and 9 with the second inputs of all three groups of inputs of elements 8 and 7. The outputs of elements 9 and 10 are connected respectively to the outputs 23 and odd the counting trigger 6, with the first inputs of the first groups of inputs of elements 7 and 8, with the second inputs of all three groups of inputs of elements 10 and 9. Inputs 18-21 are oddly countable about the trigger 6 are connected respectively to the first inputs of the third groups of inputs of elements 7 and 8, c the first inputs of the second input groups in elements 7 and 8, with the first inputs of the first groups of inputs of elements 9 and 10 and with the first inputs of the third groups of inputs of elements 10. The even trigger is a combination of two triggers, which are formed by elements 12 and 13, 1 and 15.

The outputs of elements 12 and 15 are connected respectively to the outputs 33 and 30 of an even counting trigger 11, with the second inputs of the first groups of inputs of the elements and 15, with the first inputs of the second groups of inputs of elements 13 and 12. The outputs of the elements and 15 are connected respectively with the outputs 31 and 32 even-numbered trigger 11, with the first inputs of the first groups of g moves of elements 12 and 13, with the first inputs of the second groups of inputs of elements 15 and 1. The inputs 26-29 of the even-numbered counting trigger 11 are connected respectively to the first inputs of the first groups of input elements and 15, the third inputs of the first groups of inputs of elements and 15, with the third inputs of the first groups of inputs of elements 12 and 13, with the second inputs of the first groups of inputs of elements 12 and 13. The outputs of elements 2 and 3 of the auxiliary counting trigger, the outputs of 22 and 25, 30 and 33 of each even and odd counting trigger connected to the tires binary about the account. Outputs 23 and 2k, 31 and 32 of each even and odd counting trigger, as well as outputs 30 and 33 of the last even estimated trigger are connected to the estimated buses in the Gre code. 3 odd estimated trigger 6 and 35 even on the counting trip 11 is connected to the input 17 of the initial installation of the counter and, respectively, with the third inputs of all three inputs of the element 8 and i, the second input of the first soil of the inputs of the element 15.

The counter works as follows.

Consider the work of a three-bit (by the number of bits in the Gre code) counter formed by auxiliary counting trigger 1, one odd 6 and one even 11 counting triggers. In this case, the binary code will be generated at the outputs of elements and 3, 7 and 8, 12 and 13, and the code re at the outputs of elements 9 and 10, 14 and 15, 12 and 13.

The operation of a three-bit counter in the Gre code is described by a timing diagram (FIG. 2). The counter is set to the initial state after supplying the unit to the counting input 16 and zero to the input of the initial installation 17. In this case, the outputs of elements 2, 4, 8, 9, 13 and O are set, and the outputs of elements 3, 5, 7, 10, 12, and 15 is set to 1. In this state, the binary counter (outputs of elements 2, 8, 13) and the state of the counter in the Gre code (outputs of elements 9, And, 13) are equal to 000.

Installation O at the entrance; 16 causes the switching trigger of the auxiliary counting trigger to be switched. The first counting pulse (setting 1 at input 16) leads to switching the output of element 5 from 1 to 0, which causes switching from the outputs of elements A and 9 from 0 to 1. The last change causes a change in the output state of element 10 from 1 to 0. At the same time binary state

513523

the estimator and counter in ode Gre will be 100 (figure 2). Further installation of O at input 16 leads to switching the switching trigger to the operating state. The second counting pulse at the input 16 causes the switching of the output of the epement k from 1 - O, which causes the switching of the outputs of the element

5 and 8

of

 ABOUT

M. Last of-About

The change leads to switching the outputs of elements 7 and 15 from 1 to O. Changing the state of the output of element 15 causes a change in the state of the output of element 1 from O to 1. In this case

Claims (1)

the state of the binary counter is 010, and the counter in the Gre code is 110 (Fig. 2). Further operation of the circuit can be traced according to the timing diagram of the counter, shown in FIG. 2 Invention Formula A counter in the Gre code for p-bits, consisting of an auxiliary counting trigger, which is made according to the scheme of a single-act counting rigger with one switching trigger on the first and second elements AND-OR-NOT and with one memory element on the third and the fourth AND-OR-NOT elements and the n-1 sequence of counting triggers, of which each odd counting trigger consists of an additional trigger, which is formed by the fifth and sixth AND-OR-NOT elements, whose outputs are connected respectively to the first inputs first groups of inputs of the common and fifth elements AND-OR-NOT, with the first inputs of the first groups of inputs of the seventh and eighth elements AND-OR-riE, which form a trigger, the outputs of which are connected to the counting buses in the Gre code and respectively with the first inputs of the second groups of inputs of the sixth and The fifth AND-OR-NOT elements, with the first inputs of the second groups of inputs of the eighth and seventh AND-OR-NOT elements, each even countable trigger consists of an additional trigger, which is formed by the ninth and tenth elements of the AND-OR-NOT outputs which are connected respectively to the inputs of the first groups of inputs of the tenth and ninth elements AND-OR-NOT, with the first inputs of the first groups of inputs of the eleventh and twelfth elements AND-OR-NOT, which form a trigger, the outputs of which are connected to with, ABOUT five 0 0 about 5 about § 726 we have accounts in the Gre code and respectively with the first inputs of the second input groups of the twelfth and eleventh AND-OR-NOT elements, with the first inputs of the second input groups of the tenth and ninth AND-OR-NOT elements, the outputs of the fifth and sixth AND-OR elements -NOT every odd counting trigger are connected respectively to the second inputs of the second groups of inputs of the ninth, tenth AND-OR-NOT elements and to the second inputs of the first groups of inputs of the eleventh, twelfth elements AND-OR-NOT of the subsequent even counting trigger, outputs an additional three Gera p-1 counting flip-flops are connected to counting buses in the Gre code, characterized in that, in order to improve speed, in each odd-numbered flip-flop, the outputs of the fifth and sixth elements AND-OR-NOT are connected respectively to the second inputs of the second and third groups of inputs the sixth and fifth elements AND-OR-NOT, the outputs of the seventh and eighth elements AND-OR-NOT connected respectively with the second inputs of the first and third groups of inputs of the eighth and seventh elements AND-OR-NOT, the second inputs of the first groups of inputs of the fifth and sixth elements AND-OR-NOT, first e inputs of the third groups of inputs of the fifth and sixth elements AND-OR-NOT, the first inputs of the third groups of inputs of the seventh and eighth elements AND-OR-NOT, the second inputs of the second groups of inputs of the seventh and eighth elements AND-OR-NOT are connected respectively to the outputs of the nine addition, the eleventh, twelfth, tenth elements AND-OR-NOT of the previous even counting trigger, and in the first odd counting trigger are connected respectively to the outputs of the first, third, fourth, SECOND AND-OR-NOT subsidiary counting trigger, in each even count th trigger the third inputs of the second groups of inputs of the ninth and tenth elements AND-OR-NOT, the third inputs of the first groups of inputs of the eleventh and twelfth elements AND-OR-NOT are connected respectively with the outputs of the eighth and sixth elements AND-OR-NOT of the previous odd-counting trigger . 15 2