CN116996073A - Analog-digital converter and low-power-consumption image sensor - Google Patents

Abstract

The invention discloses an analog-digital converter capable of reducing power consumption, which comprises a first comparator (1), a first clock Zhong Jiequ module (2), a second clock intercepting module (7), a high-order counter (3), a low-order counter (8), a frequency divider (4), an interval pulse generator (5), a pulse width amplifier (6) and a bit synthesizing module (9). The analog-digital converter can obviously reduce the power consumption and shorten the counting time while ensuring the counting precision. The invention also discloses an image sensor adopting the analog-digital converter, which has the characteristics of low power consumption and high frame rate.

Description

Analog-digital converter and low-power-consumption image sensor

Technical Field

The invention relates to the technical field of CMOS (complementary metal oxide semiconductor) image sensors, in particular to an analog-digital converter and a low-power-consumption image sensor.

Background

Analog-to-Digital Converter (ADC) is a process of converting a continuously variable Analog signal into a discrete digital signal. In an image sensor, incident photons are photoelectrically converted into analog electrical signals by a photo diode, and the analog signals are converted into digital signals by an ADC and output. With the continuous development of technology, the image processor is widely applied in the fields of military, scientific research, industrial and agricultural production, medical and health and the like, however, due to the defects of the image, the application market is more and more urgent for realizing the low-power-consumption image sensor. While the ADC is a core component of the image sensor chip, the reduction of its own power consumption will affect the power consumption of the sensor to a large extent.

For the conventional image sensor, a high-speed clock is required to count in order to ensure the counting precision, which results in high turnover times of the counter and excessive power consumption. For example, an ADC with a bit width of 10 bits has a built-in counter with a single full-width count of 1024 (2≡10) times, so that the power consumption is high. In addition, the counting time is long, and the frame rate of the image sensor is greatly reduced.

Disclosure of Invention

Technical problem to be solved

The invention aims to solve the problems of high power consumption and low frame rate of an image sensor caused by large power consumption expense of an analog-digital converter, and aims to provide an ADC which can ensure the counting precision and obviously reduce the power consumption, thereby realizing the low power consumption and high frame rate of the image sensor.

Technical proposal

In a second aspect, there is provided an analog-to-digital converter, comprising:

a first comparator 1 for comparing the RAMP signal V (RAMP) with the pixel signal V (PXOUT) to be detected and outputting V (CMOUT);

the clock interception module comprises a first clock interception module 2 and a second clock interception module 7, and is used for intercepting a clock signal of which the enabling signal is a high-level interval;

the high-order counter 3 is used for counting the rising edge number of the low-speed clock intercepted by the first clock interception module;

a low-order counter 8, configured to count the number of rising edges of the low-speed clock passing through the second clock intercept module;

the frequency divider 4 is used for outputting a low-speed clock signal after frequency division processing of an input high-speed clock signal, wherein the frequency division multiple is 2 n, and n is the low-order bit number of the ADC;

an interval pulse generator 5 for taking out a time width less than one clock cycle in the output signal V (CMOUT) of the first comparator 1;

a pulse width amplifier 6 for amplifying the signal output from the interval pulse generator 5 by a times in time, wherein a=2ζ;

and the bit synthesis module 9 is used for converting the m bits of the counting result of the high-order counter 3 and the n bits of the counting result of the low-order counter 8 into m+n bits of binary numbers through an algorithm.

The working principle of the analog-digital converter provided by the invention is as follows: and the V (CMOUT) signal output by the comparator is counted by adopting a high-order counter and a low-order counter at the same time, namely the high-order counter is used for measuring an integer number of low-speed clock cycles, and the low-order counter is used for measuring a less than integer number of low-speed clock cycles. By adopting the pulse width amplifier to amplify the pulse width of the decimal period according to the multiple, when the amplified signal is counted by the low-order counter, the obvious distinguishing degree can be shown, the counting precision is improved, and the brightness level is obvious on the image. Finally, the high-order count value m bit and the low-order count value n bit are converted into binary numbers of the (m+n) bit by utilizing a bit synthesis module.

In a third aspect, the present invention further provides a low power consumption image sensor employing the above-mentioned analog-to-digital converter.

Compared with the prior art, the invention has the following advantages and technical effects:

according to the analog-digital converter, the high-order counter and the low-order counter are combined, and the low-speed clock counting mode is adopted, so that the counter turnover frequency can be reduced while the counting precision is ensured, and the ADC power consumption is further reduced; meanwhile, the counting time is shortened so that the frame rate of the image sensor is increased.

Drawings

The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:

fig. 1 is a schematic structural diagram of an ADC system according to an embodiment;

FIG. 2 is a timing diagram of the ADC system according to the embodiment;

fig. 3 is a schematic diagram of a pulse width amplifier according to an embodiment;

FIG. 4 is a timing diagram of the pulse width amplifier according to the embodiment;

FIG. 5 is a schematic diagram of a pulse selector according to an embodiment;

FIG. 6 is a timing diagram illustrating an operation of the pulse selector according to the embodiment;

FIG. 7 is a schematic diagram illustrating the working principle of the bit synthesis module according to the embodiment;

FIG. 8 is a block diagram illustrating a clock signal and a clock signal according to an embodiment;

FIG. 9 is a diagram showing the structure and operation timing of a counter according to an embodiment;

FIG. 10 is a diagram showing a structure and an operation timing of a frequency divider according to an embodiment;

FIG. 11 is a schematic diagram showing the structure and operation timing of an interval pulse generator according to an embodiment;

identification in the drawings:

1-a first comparator; 2—first time Zhong Jiequ module; 3-high counter; 4-a frequency divider; 5-interval pulse generator; 6-pulse width amplifier; 7, a second clock interception module; 8-low counter; 9-a bit synthesis module;

61—a first current source; 62—a second current source; 63—a first D flip-flop; 64—pulse selector; 65-a second comparator;

description of the embodiments

For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.

Examples

The traditional image sensor has the problems of high power consumption expense, long counting time and limited frame rate caused by the fact that the counter is turned over for a plurality of times. For example, an ADC with a bit width of 10 bits has a built-in counter that counts up to 1024 (2·10) times of flip per full-width, and therefore has high power consumption. In order to provide an image sensor that meets both low power consumption and high frame rate, the present invention provides an improved Analog-to-Digital Converter (ADC).

Fig. 1 shows a low power consumption analog-to-digital converter structure of the present invention, which includes:

a first comparator 1 for comparing the RAMP signal V (RAMP) with the pixel signal V (PXOUT) to be detected and outputting V (CMOUT);

the first clock interception module 2 and the second clock interception module 7 are used for intercepting a clock signal of which the enabling signal is a high-level interval;

the high-order counter 3 is used for counting the rising edge number of the low-speed clock passing through the first clock interception module;

a low-order counter 8 for counting the number of rising edges of the low-speed clock of the second clock interception template;

the frequency divider 4 is used for outputting a low-speed clock signal after frequency division processing of an input high-speed clock signal, wherein the frequency division multiple is 2 n, and n is the low-order bit number of the ADC;

an interval pulse generator 5 for taking out a time width less than one clock cycle in the output signal V (CMOUT) of the comparator 1;

a pulse width amplifier 6 for amplifying the signal output from the interval pulse generator 5 by a times in time, wherein a=2ζ;

the bit synthesis module 9 is configured to convert the m bits of the count result of the high-order counter 3 and the n bits of the count result of the low-order counter 8 into m+n bits through an algorithm.

Fig. 3 shows a possible configuration of a pulse width amplifier, which includes, as shown, a first current source 61, a second current source 62, a first D flip-flop 63, a pulse selector 64, a second comparator 65, a first capacitor CA, a second capacitor CB, a first control switch sw_main_a, a second control switch sw_main_b, a first sample-and-hold switch sw_sha and a second sample-and-hold switch sw_shb;

the D end of the first D trigger 63 is connected with the XQ end of the first D trigger 63, one end of the second control switch SW_MAIN_B is connected with the first current source 61, the other end of the second control switch SW_MAIN_B is connected with the second sample-and-hold switch SW_SHB, the other end of the second sample-and-hold switch SW_SHB is simultaneously connected with the positive input end of the second comparator 65 and the upper polar plate of the second capacitor CB, and the lower polar plate of the second capacitor CB is grounded;

one end of the first control switch SW_MAIN_A is connected with the second current source 62, the other end of the first control switch SW_MAIN_A is connected with the first sample-and-hold switch SW_SHA, the other end of the first sample-and-hold switch SW_SHA is simultaneously connected with the upper polar plate of the first capacitor CA and the negative input end of the second comparator 65, and the lower polar plate of the first capacitor CA is grounded;

the IN signal is connected to the input end of the first D flip-flop 63, the XRST signal is connected to the XRST end of the first D flip-flop 63, and the Q-terminal of the first D flip-flop 63 is connected to the signal line sw_a, which is used for controlling the first control switch sw_main_a; the signal line sw_b is connected with a signal IN for controlling the second control switch sw_main_b; the clock signal CLK is connected to the IN terminal of the pulse selector 64, the XRST signal is connected to the XRST terminal of the pulse selector 64, and the output terminal of the pulse selector 64 is connected to the signal line s_clk, which is used for controlling the first sample-and-hold switch sw_sha; the clock signal CLK is used to control the second sample-and-hold switch SW_SHB at the same time; the reset signal RST is connected to the input end of the second comparator 65, and the output end of the second comparator 65 outputs a signal.

Fig. 4 shows the operation sequence of the pulse width amplifier, and as shown in the drawing, the following description will take the system frequency division ratio of 16 as an example:

the pulse width of the input IN signal is w_in, and is used for controlling the on and off of the first current source 61 and the second control switch sw_main_b; resetting the first D flip-flop when the XRST signal is at a low level, wherein the Q end (V (SW_A)) of the first flip-flop is at a low level after resetting; when the RST signal is at a high level, the second comparator 65, the node vin_a and the node vin_b are all in a reset state, V (vin_a) =v (vin_b) =0, and the comparator outputs V (OUT) =0;

when the output signal V (s_clk) of the pulse selector 64 is at a high level, the first sample-and-hold switch sw_sha is turned on to charge the first capacitor CA, and when V (s_clk) is at a low level, the first sample-and-hold switch sw_sha is turned off, the first capacitor CA is in a discharge state, the node voltage V (vin_a) is continuously increased, and the first capacitor CA is stabilized at a certain voltage level after a period of time;

when the CLK signal is high, the second sampling hold switch SW_SHB is turned on, the second capacitor CB is in a charging state, when the CLK signal is low, the second sampling hold switch SW_SHB is turned off, the second capacitor CB enters a discharging state, the node voltage V (VIN_B) is increased, and the voltage is stabilized at a certain voltage level after a period of time;

the negative input of the comparator is connected with V (VIN_A), the positive input of the comparator is connected with V (VIN_B), the output voltage of the comparator is high only when V (VIN_B) > V (VIN_A), and the pulse width W_OUT=16×W_IN of the high level is high.

It is known in the art that the larger the voltage amplitude of the pixel signal, the larger the pulse width of V (CMOUT) and the larger the count result of the counter.

The pulse selector employs an asynchronous clock, synchronous reset (XRST) D flip-flop cascade architecture. The function is to output a pulse signal every 2 n pulses of the input signal. For convenience of explanation, the pulse selector of 16-select 1 will be described in detail below as an example, and the pulse selector of the present invention is not limited to this configuration, and may be implemented by adjusting the number of D flip-flops as needed.

As a possible embodiment, fig. 5 shows a structure of the pulse selector, and the pulse selector outputs one pulse signal after 16 pulses of the input signal, and the number of D flip-flops is 4 (2^4 =16). As shown in fig. 5, the input terminal of the fifth D flip-flop is input with the clock signal CLK, the D terminal of the fifth D flip-flop is connected to the XQ terminal thereof, and the common terminal of the D terminal and the XQ terminal is connected to the input terminal of the fifth D flip-flop; the D end of the fifth D trigger is connected with the XQ end of the fifth D trigger, and the common end of the D end and the XQ end of the fifth D trigger is connected with the input end of the fifth D trigger; the D end of the fifth third D trigger is connected with the XQ end of the fifth third D trigger, and the common end of the D end and the XQ end of the fifth third D trigger is connected with the input end of the fifth fourth D trigger;

the Q end of the fifth D trigger is connected with one input end of the fifth AND gate through a signal line D0, the Q end of the fifth D trigger is connected with the other input end of the fifth AND gate through a signal line D1, and the output end of the fifth AND gate is connected with one input end of the fifth third AND gate through a signal line NET_A;

the Q end of the fifth third D trigger is connected with one input end of a fifth second AND gate through a signal line D2, the Q end of the fifth fourth D trigger is connected with the other input end of the fifth second AND gate through a signal line D3, the output end of the fifth second AND gate is connected with the other input end of the fifth third AND gate through a signal line NET_B, the output end of the fifth third AND gate is connected with one input end of the fifth fourth AND gate through a signal line NET_AND4, the other input end of the fifth fourth AND gate is connected with a clock signal line, AND the output end of the fifth fourth AND gate outputs signals;

the reset signal XRST is simultaneously connected to the XRST end of the fifth D trigger, the XRST end of the fifth second D trigger, the XRST end of the fifth third D trigger and the XRST end of the fifth fourth D trigger.

Fig. 6 shows the operation timing of the pulse selector, and it can be seen that when the reset signal XRST is low, no signal is output from the signal lines except the clock signal line; after the reset is completed, the signal line D0 outputs a divide-by-two signal (i.e., the frequency is 1/2 of the clock signal frequency), the signal line D1 outputs a divide-by-four signal, the signal line D2 outputs an divide-by-eight signal, and the signal line D3 outputs a divide-by-sixteen signal; only when the level on the signal lines D0, D1, D2, D3 is high, the level on the signal line net_and4 is high, AND the output terminal OUT outputs a signal, AND the pulse amount of the output signal is 1/16 of the clock pulse amount.

Fig. 7 shows the working principle of the bit synthesis module, where the bit synthesis module fuses the upper m bits with the lower n bits to obtain m+n bits. For convenience of explanation, the following description will be given by taking high-order 6-bit and low-order 4-bit data as an example.

S1, a bit synthesis module obtains a count value (binary number) of a high-order counter with 6 bits and a count value (binary number) of a low-order counter with 4 bits;

s2, shifting the count value of the high-order counter with 6 bits in the step S1 to four bits leftwards, and zero filling the last four bits to obtain binary numbers with the bit width of 10 bits;

s3, performing binary subtraction operation on the binary number with the bit width of 10 bits in the step S2 and the count value of the low-order counter with the bit width of 4 bits in the step S1, and finally obtaining the data with the bit of (6+4).

Through the steps, the binary numbers of the high-order m bit and the low-order n bit are converted into the binary numbers of the (m+n) bit.

Fig. 2 shows the operation sequence of the ADC system, and it can be seen that the working principle of the analog-digital converter is: the V (CMOUT) signal output from the comparator is counted by both the high and low counters, i.e. the high counter is used to measure an integer number of low speed clock cycles, and the low counter is used to measure less than an integer number of low speed clock cycles (e.g. the output signal is 50.2 clock cycles, the integer period 50 is counted by the high counter, the fractional period is 0.2, and the low counter is counted). In order to reduce the turnover times of the counter and further reduce the power consumption, the invention adopts a low-speed clock counting mode. When using a low-speed clock, which results in a fractional period measurement, the count accuracy may be reduced. For example, when the decimal period is three cases of 0.1cycle, 0.5cycle and 0.9cycle, if the low-speed clock is directly used for counting, the result of counting is 0LSB. In order to find the balance between low power consumption and high precision, the invention provides the pulse width amplifier which can amplify the pulse width of the decimal period according to the multiple, and when the amplified signal is counted by the low-order counter, the obvious degree of distinction can be shown, the counting precision is improved, and the brightness level is clear on the image. For example, after the pulse width amplifier amplifies the fractional period of the signal by 16 times, the pulse widths of the obtained signals are respectively 1.6cycle, 8cycle and 14.4cycle, so that the count values of the counter are respectively: 1LSB, 8LSB and 14LSB. And finally, converting the high-order count value m bit and the low-order count value n bit into binary numbers of the (m+n) bit through a bit synthesis module.

The analog-to-digital converter structure provided by the invention, wherein the Zhong Jiequ module, the counter, the frequency divider and the interval pulse generator are all conventional devices in the field, and can be selected according to the needs of the person skilled in the art. Possible structures of the above device will be illustrated below, but are not limited to these structures.

Fig. 8 (a) shows a possible implementation of the clock clipping module, which includes an and gate as shown in fig. 8 (b), where the enable signal EN and the clock signal CLK are input signals, and when both signals are at high level, the clock signal at that time is clipped and output (as shown in fig. 8 (b)).

Fig. 9 (a) shows one possible implementation of a counter, a D flip-flop cascade structure employing asynchronous clock, synchronous reset (XRST). Both the high counter and the low counter may have such a structure. Specifically, the ninth D flip-flop is connected to the clock signal CLK, the D terminal of each stage D flip-flop is connected to the XQ terminal thereof, and the common terminal of the ninth D flip-flop and the XQ terminal thereof is connected to the input terminal of the next stage D flip-flop, and each stage D flip-flop is simultaneously connected to the reset signal XRST, and the Q terminal of each stage D flip-flop is used as the output terminal. The number of cascaded D flip-flops is determined by the bit width of the counter, i.e. a T bit counter selects T D flip-flop cascades. After the reset is completed, the signal line D91 outputs the lowest bit of the count value, the signal line D92 outputs the next lowest bit of the count value, and so on, the signal line D9n outputs the highest bit of the count value, and the binary number of the counter count value is formed by arranging the above data from the highest bit to the lowest bit. Starting from 0, when the CLK clock signal rises every one edge, the count is incremented by 1 until the clock signal does not rise, thus effecting the binary-to-decimal conversion of the count value (as shown in fig. 9 (b)).

Fig. 10 (a) shows a possible frequency divider structure, which is the same as the structure of the counter described above, and adopts a structure in which D flip-flops are cascade-connected, except that only the signal line D10n of the frequency divider has a signal output, and the case of outputting a divided signal is shown in fig. 10 (b).

Fig. 11 (a) shows a possible structure of the interval pulse generator, which includes a D flip-flop and an exclusive-or gate, wherein the D flip-flop has a D terminal signal IN and is also connected to a clock signal CLK, the Q terminal of the flip-flop has one terminal of the exclusive-or gate, the IN signal has the other terminal of the exclusive-or gate, and the output terminal of the exclusive-or gate has the input terminal of the next stage module. As shown IN fig. 11 (b), when the output signal IN of the comparator is the same as the Q-phase output of the D flip-flop, the output of the interval pulse generator is at a low level; when the output signal of the comparator is different from the output of the Q end of the D trigger, the output of the interval pulse generator is high level. From this timing it can be seen that the output of the interval pulse generator is a section where the duration of the output signal CMOUT of the comparator is less than an integer number of clock cycles (cycles).

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims (10)

1. An analog-to-digital converter, comprising:

a first comparator (1) for comparing the RAMP signal V (RAMP) with the pixel signal V (PXOUT) to be detected and outputting V (CMOUT);

the clock interception module comprises a first clock Zhong Jiequ module (2) and a second clock interception module (7) and is used for intercepting a clock signal of which the enabling signal is in a high-level interval;

the high-order counter (3) is used for counting the number of rising edges of the low-speed clock intercepted by the first clock interception module;

the low-order counter (8) is used for counting the rising edge number of the low-speed clock passing through the second clock interception module;

the frequency divider (4) is used for outputting a low-speed clock signal after frequency division processing of an input high-speed clock signal, wherein the frequency division multiple is 2 n, and n is the low-order bit number of the ADC;

an interval pulse generator (5) for taking out a time width less than one clock cycle in an output signal V (CMOUT) of the first comparator 1;

a pulse width amplifier (6) for amplifying the signal output by the interval pulse generator (5) a times of time, wherein a=2 ζ;

and the bit synthesis module (9) is used for converting the m bits of the counting result of the high-order counter (3) and the n bits of the counting result of the low-order counter (8) into binary numbers of m+n bits through an algorithm.

2. The analog-to-digital converter according to claim 1, wherein the pulse width amplifier (6) comprises a first current source (61), a second current source (62), a first D flip-flop (63), a pulse selector (64), a second comparator (65), a first capacitor CA, a second capacitor CB, a first control switch sw_main_a, a second control switch sw_main_b, a first sample-and-hold switch sw_sha and a second sample-and-hold switch sw_shb;

the D end of the first D trigger (63) is connected with the XQ end of the first D trigger, one end of the second control switch SW_MAIN_B is connected with the first current source (61), the other end of the second control switch SW_MAIN_B is connected with the second sample hold switch SW_SHB, the other end of the second sample hold switch SW_SHB is simultaneously connected with the positive input end of the second comparator (65) and the upper polar plate of the second capacitor CB, and the lower polar plate of the second capacitor CB is grounded;

one end of the first control switch sw_main_a is connected with the second current source (62), the other end of the first control switch sw_main_a is connected with the first sample-and-hold switch sw_sha, the other end of the first sample-and-hold switch sw_sha is simultaneously connected with the upper polar plate of the first capacitor CA and the negative input end of the second comparator (65), and the lower polar plate of the first capacitor CA is grounded;

an IN signal is connected to the input end of the first D trigger (63), an XRST signal is connected to the XRST end of the first D trigger (63), and the Q end of the first D trigger (63) is connected to a signal line SW_A which is used for controlling the first control switch SW_MAIN_A; the signal line sw_b is connected with a signal IN for controlling the first control switch sw_main_b; a clock signal CLK is connected to the IN end of the pulse selector (64), an XRST signal is connected to the XRST end of the pulse selector (64), and the output end of the pulse selector (64) is connected to a signal line S_CLK which is used for controlling the first sample-and-hold switch SW_SHA; the clock signal CLK is used to control the second sample-and-hold switch SW_SHB at the same time; the reset signal RST is connected to the input end of the second comparator (65), and the output end of the second comparator (65) outputs a signal.

3. An analog-to-digital converter according to claim 2, characterized in that the control of the pulse width amplifier (6)

The method comprises the following steps:

the pulse width of the IN signal is W_IN, and the IN signal is used for controlling the on and off of the first current source (61) and the first control switch SW_MAIN_B; resetting the first D flip-flop (63) when the XRST signal is at a low level, wherein a Q-terminal signal V (SW_A) of the first D flip-flop (63) is at a low level after resetting; when the RST signal is at a high level, the second comparator (65), the node vin_a and the node vin_b are all in a reset state, V (vin_a) =v (vin_b) =0, and the comparator outputs V (OUT) =0;

when the output signal V (s_clk) of the pulse selector (64) is at a high level, the first sample-and-hold switch sw_sha is turned on to charge the first capacitor CA, and when V (s_clk) is at a low level, the first sample-and-hold switch sw_sha is turned off, the first capacitor CA is in a discharge state, the node voltage V (vin_a) is continuously increased, and the voltage is stable after a period of time;

when the CLK signal is high, the second sample-and-hold switch sw_shb is turned on, the second capacitor CB is in a charged state, when the CLK signal is low, the second sample-and-hold switch sw_shb is turned off, the second capacitor CB is in a discharged state, the node voltage V (vin_b) increases, and the voltage is stable after a period of time;

the negative input end of the comparator is connected with V (VIN_A), the positive input end of the comparator is connected with V (VIN_B), the output voltage of the comparator is high only when V (VIN_B) > V (VIN_A), and the pulse width W_OUT of the high level is a multiple of the pulse width W_IN.

4. The analog-to-digital converter of claim 2, wherein the pulse selector (64) comprises n-stage D flip-flops and n-stage and gates, wherein the D flip-flops adopt a D flip-flop cascade structure of asynchronous clock and synchronous reset, so that 1 pulse signal is output every 2 n pulses of the input signal.

5. The analog-to-digital converter of claim 4, wherein the pulse selector (64) has a D terminal of the D flip-flop connected to its XQ terminal, and a common terminal of the D terminal and its XQ terminal connected to an input terminal of a next-stage D flip-flop, Q terminals of two adjacent D flip-flops connected to input terminals of corresponding and gates, output terminals of two adjacent and gates connected to an input terminal of a next-stage and gate, and an output terminal of an (n-1) -th and gate connected to an n-th and gate of the clock signal CLK; the clock signal CLK is coupled to the input of the first stage D flip-flop and the reset signal XRST is coupled to the XRST of the n stage D flip-flop.

6. The analog-to-digital converter of claim 4, wherein the pulse selector (64) is structured to include, when n = 4: a fifth D trigger, a fifth two D trigger, a fifth three D trigger, a fifth four D trigger, a fifth first AND gate, a fifth two AND gate, a fifth three AND gate and a fifth four AND gate;

the input end of the fifth D trigger inputs a clock signal CLK, the D end of the fifth D trigger is connected with the XQ end of the fifth D trigger, and the common end of the D end and the XQ end of the fifth D trigger is connected with the input end of the fifth D trigger; the D end of the fifth D trigger is connected with the XQ end of the fifth D trigger, and the common end of the D end and the XQ end of the fifth D trigger is connected with the input end of the fifth D trigger; the D end of the fifth third D trigger is connected with the XQ end of the fifth D trigger, and the common end of the D end and the XQ end of the fifth D trigger is connected with the input end of the fifth fourth D trigger;

the Q end of the fifth D trigger is connected with one input end of the fifth AND gate through a signal line D0, the Q end of the fifth D trigger is connected with the other input end of the fifth AND gate through a signal line D1, and the output end of the fifth AND gate is connected with one input end of the fifth third AND gate through a signal line NET_A;

the Q end of the fifth third D trigger is connected with one input end of the fifth second AND gate through a signal line D2, the Q end of the fifth fourth D trigger is connected with the other input end of the fifth second AND gate through a signal line D3, the output end of the fifth second AND gate is connected with the other input end of the fifth third AND gate through a signal line NET_B, the output end of the fifth third AND gate is connected with one input end of the fifth fourth AND gate through a signal line NET_AND4, the other input end of the fifth fourth AND gate is connected with a clock signal line, AND the output end of the fifth fourth AND gate outputs signals;

and the reset signal XRST is simultaneously accessed to the XRST end of the fifth D trigger, the XRST end of the fifth second D trigger, the XRST end of the fifth third D trigger and the XRST end of the fifth fourth D trigger.

7. An analog-to-digital converter according to claim 1, characterized in that the data conversion step of the bit synthesis module (9) is:

s1, a high-order counter count value X bit and a low-order counter count value Y bit are obtained by a bit synthesis module;

s2, shifting the count value of the high-order counter of the X bit in the step S1 by Y bits to the left, and zero filling the last Y bits to obtain binary numbers with the high-order bit width of (X+Y) bit;

s3, performing binary subtraction operation on the binary number with the high bit width of (X+Y) bit in the step S2 and the count value Y bit of the low counter in the step S1, and finally obtaining the binary number with the (X+Y) bit after the combination of the high bit and the low bit.

8. An analog-to-digital converter according to claim 1, characterized IN that the structure of the interval pulse generator (5) comprises a D flip-flop and an exclusive-or gate, wherein the D of the D flip-flop is terminated by a signal IN, while the clock signal CLK is also connected, the Q of the D flip-flop is connected to one end of the exclusive-or gate, the IN signal is connected to the other end of the exclusive-or gate, and the output of the exclusive-or gate is connected to the input of the next stage module.

9. The analog-to-digital converter according to claim 1, wherein the low-order counter (8) and the high-order counter (3) are in a D flip-flop cascade structure with asynchronous clock and synchronous reset, and the number of the D flip-flops is determined by the bit widths of the low-order counter (8) and the high-order counter (3).

10. A low power consumption image sensor employing an analog to digital converter as claimed in any one of claims 1 to 9.