SU615496A1 - Pulse-frequency signal integrator - Google Patents

Description

connected to the first inputs of the third, fourth and fifth triggers and through the second and third delay elements connected respectively to the zeroing input of the main counter and to the second inputs of the AND elements of the main group, output; which through the register are connected to the first inputs of the elements AND of the additional group, the second inputs of which are connected to the third input of the multiplying-dividing block and to the input of the additional counter, the bit inputs of which are connected to the outputs of the elements I of the additional group, and the counting input is connected to the output of the fifth element And connected by the first input to the output of the third trigger, and the second input to the device start input and to the first inputs of the sixth and seventh elements AND, the second inputs of which are connected to the device input va and with the second input of the third element And connected by the output to the second inputs of the fourth and fifth triggers, the first outputs of which are connected respectively to the second input of the first and third inputs of the sixth element And, with the output of the sixth element And through the fourth delay element connected to the input of the second trigger and the second output of the fifth trigger is connected to the third input of the first AND element, and the output of the seventh AND element connected by the third input to the output of the sixth trigger is connected to the first input of the main OR element, the second whose input is connected to the output of the multiplying-dividing block and the input of the sixth trigger.

The drawing shows a functional diagram of the device for integrating pulse frequency signals.

The device contains miozhitelnoe blocking unit 1, the main counter 2, the additional counter 3, register 4, the frequency-pulse memory unit 5 ,. triggers 6jl 1, elements AND 12-g18, groups of elements AND 19 20 elements OR 21.22, elements of delay 23t-26, terminal 27 for supplying input signals to terminal 28. applying a trigger signal, terminals 29.30 for applying reference frequency signals, output terminal 31.

The device works as follows. Input signals with a frequency of R are fed to the terminal 1. The signals of the reference frequencies of the op and Rod2Support signals to the terminals 29 and 30, respectively. In the initial state, the counters, registers and triggers of the device are reset. At time t, 28 is given a start signal. In this case, the first pulse after the moment t, applied to the terminal 27, passes through the element I1 and through the delay element 23 to the counting input of the trigger 6, transferring it to the zero state in the unit state,. Obviously, in this case, the signal does not pass to the output of the AND element 13, since the unlocking signal from the trigger 6 is applied to its input with a delay due to the delay element 23. With the transfer of the trigger b to one, the unlocking signal from its output is fed to the input And 13 and through the element OR 21 - to the input of the element And 16. At the same time, through the element 16 and to the input of the counter 2, the signals of the reference frequency P ,, begin to be provided with the function of filling the frequency period. At the same time, the input frequency period is filled until the next signal arrives at 27. When the next signal arrives at terminal 27, this signal passes to the output of the And 13 element, the trigger 7 is switched to and the time determined by the delay element 23 translates the trigger 6 into zero state As a result of the interruption of the supply of the unlocking voltage to the input of the element And 16, the supply of the signals of the reference frequency | to the input of counter 2, and it records information corresponding to the period of the frequency counter. At the same time, as a result of the translation of the 7 trigger. a single state opens element AND 14 for signals from the output of the integrator, specifically from the output of element OR 22, and locks element AND 12 for input signals c. frequency Pjj. The first signals to the integrator output pass from terminal 27 through element 18 and element 22. The first signal from the output sequence after unlocking the element 14 passes through element 14 and element 14; delay 24 to the counting input of the trigger 8 , transfer it from zero to single state.

 As a result, the unlocking signal from the output of the trigger 8 is fed to the input of the element 15 and through the element ID 19 to the input of the element 16. At the same time through the element 16 to the input of the counter 2

the signals of the reference frequency rdd begin to be fed, which are su ftruyut with the information about the period of the input signal accumulated on the accumulated counter

sequences are carried out. until the next signal from the output, the device to the input; element E14 .: When this signal arrives, it passes to the output of element I 15, translation triggers 9 and 10

in one state, and trigger 7 - in zero. After a time determined by the delay element 24, the trigger 8 is turned into a zero state, and as a result,

Claims (1)

the elements 12 and 17 and the elements 14 and 16 are locked. Thus, counter 2 records information on the sum of two periods sV 4T B) f g the period of the input sequence signals from the hour ToaV j the period of the signals of the output sequence. The number of pulses recorded by counter 2 is defined as T + T. whereT, is the period of the reference signals. The information accumulated in the counter is accumulated in ke 2, is rewritten into memory register 4 and in counter 3 by the signals from the output elements 15, and counter 2 is zeroed. Next, the process described by BiAiie for obtaining information on the sum of the two periods in the score. Rule 2 is repeated. The signals of the Gon2 reference frequency begin to be fed to the input of counter 3 after unlocking the element I 17. When signals are applied to the input of counter 3, they are recalculated in it and from its output are fed to the third input of the multiplying-divider block and to the control inputs of the group of elements And 20. As a result of signals from the counter output. 3 to the inputs of the elements AND 20 information stored in the register 4, periodically transmitted through the elements AND 2 to the counter 3, to form its initial setting. Thus, depending on the value of the initial setpoint, the output of the counter 3 is set to the frequency EXIT The obtaining of the final result is carried out with the help of the multiplier-division unit 1. At the same time, the first input (multiplication input) is given to the second input the input (also the multiplication input) is provided by the output signals of the device, the frequency of which is pre-memorized with the help of the frequency-pulse memory unit 5, in which the multiplication operation is also performed by n the memorized frequency. . And finally, on the third entrance is many. the divider unit (division input) signals are output from the counter 3. In multiplier-divider unit 1, the multiplier operation is performed — the input frequencyRd and the frequency of the M-Pgy are multiplied and the result is divided by the frequency of impulses following the output of the counter 3. .. . The multiplier-dividing block is implemented similarly to the described device on counters 2.3 and memory register 4. Therefore, at its output, the resulting signals have a uniform distribution. The signals from the output of the multiplying-splitter unit 1 are fed to the input of the trigger 11 and, via the OR element 22, to the output terminal 31, forming a sequence of pulses characterizing the final result. As a result of the signal input to the trigger input 11, the first of the signals mentioned translates the indicated trigger into a single state, which causes the element to be locked and 18. for signals of the input sequence that passed to the output of the device until the appearance of the signals at the output of the multiplying-dividing block. In the general case, the period of the pulse sequence at the output of the multiplying-dividing block 1 is determined by the expression chi,: c) from the output loop. - & x output-flow V 1 a definable period hyk.opr. output frequency (at the output of block 1), the current value of the period of the output frequency at the moment in the frequency representation of the input) 7 BbOf.ORp f. - detectable output frequency BF. frequency; - the current value of the output current frequency at a given time .. Thus, c. The proposed device performs an integration of the input quantity, presented in the form of a pulse frequency, since: there is a continuous summation of the current increase in the output pulse frequency with the input frequency. Improving the accuracy of the device is due to the fact that the output sequence is uniform, and the increase in speed is a significant reduction in the number of conversions of input signals. The invention The device for integrating frequency-pulse signals contains a multiplying-durable unit connected to the first input with: device input, counter , the outputs of which are connected to the first inputs of the elements AND of the main group, and the element OR,