SU375783A1 - DISCRETE MULTIPLE OF FREQUENCY - Google Patents

Description

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The invention relates to radio engineering and digital measurement technology and can be applied to improve the speed in measuring low and low frequency signals.

Known discrete frequency multipliers made on a push-pull circuit and containing an input driver connected to a control trigger, a binary multiplier consisting of a counter, a group of matching circuits and an OR circuit, and two quantization devices consisting of a control counter, an input which is connected to the output of the key, and the output - to the input of the device for automatically changing the quantization frequency, whose inputs through the frequency divider are connected to the output of the clock frequency generator, have a narrow frequency range and narrow range of variation of the frequency multiplier.

The purpose of the invention is to expand the frequency range and range of the multiplication factor of the discrete frequency multiplier.

To do this, two additional groups of matching schemes are introduced into it - with OR or output circuits, keys, OR circuits or subtraction device consisting of a trigger and a key, one input of which is connected to the output of said trigger, and the potential inputs of two groups coincidence circuits are connected to the outputs of the bits of the control counters, and pulsed circuits are connected to the outputs of the bits of the binary multiplication counter, the input connected to the output of the key of the subtractor, the second input of which and one input of the trigger of the subtracting device through one The OR circuit and additional keys are connected to the outputs of the automatic quantization frequency change device, and the other trigger input of the subtraction device is connected to the OR outputs of two groups of coincidence circuits via the second OR circuit and the second additional keys, which control inputs also the control inputs of the first additional switches are connected to the outputs of the control trigger.

Ia the drawing is represented functional

0 scheme of the proposed discrete frequency multiplier.

The device consists of an input device (former) 1 with a control trigger 2 and a reset device 3 at the output, keys 4, 5, 6, 7, 8, 9 VI 10, devices 11, 12,

5 13, 14 and 15 logical addition, made in the form of OR circuits, binary counters 16, 17 and 18, groups 19, 20 and 2.1 of impulse-potential coincidence circuits, devices 22 and 23 of changing the quantization frequency and tact

frequency, binary quantizer and clock divider 24 and generator 25 and trigger 26 with separate inputs.

The key 10 and the trigger 26 constitute a circuit for reading the frequencies of two pulse sequences that are fed to the inputs of the trigger 26. The subtraction circuit together with the binary counter 18 constitutes a frequency divider with digital negative feedback. The input device /, trigger 2 and counter 16, key 6 and device 23 for changing the quantization frequency and clock frequency, as well as counter / 7, key 9 and device 22 for changing the quantization frequency and clock frequency comprise two alternating devices for quantizing and multiplying frequency coding. . The sequence is determined by trigger 2. Periodic cleaning of the counters 16, 17 and devices 22, 23 before the start of quantization and the coding of the beginning of the period is performed by the device 3 reset.

The counters 16 tl 18 and the group 20 of the schemes of coincidence with the logical addition device 12 and the key 4, as well as the counters 17 and 18 and the group 19 of the schemes of coincidence with the logic addition device 13 and the key 5 constitute two alternate sources of a pulse feedback sequence, which one input to the subtraction circuit. The key 7 and the device 23, as well as the key 8 and the device 22, form two alternately operating sources of a clock pulse sequence, which is fed to the second input of the subtraction circuit. The sequence is set by trigger 2.

The binary counter 18 and the group 21 of the matching circuit with the logical addition circuit 15 comprise a binary frequency multiplier with a multiplication factor, which is determined by the code of the input number.

The multiplier works as follows.

The voltage of the multiplied frequency is fed to the input device /. The square-shaped multiply-frequency pulses formed with his break are fed to the counting input of flip-flop 2. Assume that before supplying the multiplied frequency, he occupied a position in which the keys 5, 5 and S controlled by him were closed, and the keys 4, 7 and 5 were open. The first pulse of the multiplied frequency flip-flop 2 switches and starts the reset device 5, which sets the counter 16 to the zero state, and the device 23 to change the quantization frequency to the position in which the clock pulses of the generator 25 pass without dividing by the output. After switching the trigger 2, the keys 4, 7 and 9 are closed, and the keys 5, 6 and 8 are opened. Due to this, through the public key 6 during the period Tx of the frequency to be multiplied, the clock frequency pulses from the output of the device 23 enter the input of the counter 16. leads to overflow of the counter 16. If the value of the frequency to be multiplied lies in the first sub-band, then

the end of the period Tx in the counter 16 will re-enter the number of pulses less than Nm. If the duration of Tx exceeds the value

7 9.

Jin

where, t is the conversion factor of the counters 16, 17, 18;

fm is the frequency of the clock generator,

then at time t-T a second overflow of counter 16 occurs. An overflow pulse, a dimple to the input of the device 23, changes the frequency value at its output. Therefore, at the output of the device 23, imulses are passed, following with a clock frequency previously divided into two. In the long run, if the value of the frequency to be multiplied is

the second sub-band, then the number of pulses less than Nm arrives at the input of counter 16. At the moment of time, the next overflow of the counter 16 occurs, the device 23 moves to the next position, and the frequency of the pulses at the output of the device 23 is again halved. Thus, during the period Tx, there are V switchings of counter 16, where V is the subband in which the multiplied

the frequency, and after the last overflow, even before the end of the period Tx, a certain number of pulses is less, the frequency of which is equal. The last overflow, counter 16 occurs at time t, equal to

nV-l

t - t

N, nThis is equivalent to the arrival at the input, a counter of 16 Nm pulses with a frequency fm / 2.

At the end of the period Tx, trigger 2 switches back again by opening the keys 7 and 9 and closing the keys 5, 6 to 8. The reset device 3 starts up again, but to its initial state

This time the triggers of the counter / 7 and the device 22 for changing the quantization frequency are set. The frequency at the output of the device 23 remains unchanged and will be equal to fm / 2. The pulses from the output of the device 23 through the keys 7 and the device 14 are fed to the input of the trigger 26, which is connected to the input of the key 10. The sampling of the feedback pulses from the counter / 5 is carried out by means of a group 20 of the coincidence circuit, which controls the code of the number written in the quantization time of the period Tx to counter 16, proportional to the discrete value Tx. In the next period of the frequency to be multiplied, the feedback pulses will be collected using a group of 1/5 coincidence circuit, which controls the number code in counter 17. The feedback pulses from the outputs of group 20 of the coincidence circuit through devices // and 12 logical addition and key 4 are given

to the second separate input of the trigger 26, which compares the pulse repetition frequency, which comes from the output of the device // logical addition and the clock pulses from the output of the device 15 logical addition. If the feedback pulses do not arrive, then the key 10 is open, and all the clock pulses fmJ2 pass to the counting input of the trigger of the least significant bit of the counter 18. If they arrive, each of them switches the trigger 26, which leads to closing the key 10. For this reason, the next clock frequency pulse / m / -2 -i does not pass through the input of counter 18, but causes switching of the trigger 26 and opening of the key 10. As a result, only the next pulse of this frequency passes through key 10 to the input of counter 18 Consequently, the frequency / pulse in on the output of the subtraction circuit, i.e., at the input of the counter 18, is equal to the frequency difference

input - / / OS fm

where / f is the pulse frequency on

the output of the device 23 or 22; foe is the frequency of the feedback pulse.

Mathematically, it can be proved that Bx is Nm-lx, where f is the frequency to be multiplied, or, where x is the number, numbers; / ЕЫХ -frequency of the pulses at the output of the device 15.

Simultaneously with the described process of pulse generation of the multiplied frequency over the previous period Tx, quantization and coding of the next period is carried out, which is carried out using the counter 17, the device 22 for changing the quantization frequency and the clock frequency and the key 9 in the same way as described above.

Subject invention

Discrete frequency multiplier. made under the push-pull scheme and containing

an input driver connected to a control trigger, a binary multiplier consisting of a counter, a group of coincidence circuits and an OR circuit, and two quantizing devices consisting of a control counter whose input is connected to the output of the key and the output to the input of the device automatic change of the quantization frequency, the inputs of which are connected via the frequency divider to the output of the clock frequency generator, characterized in that, in order to expand the frequency range and the range of variation of the multiplication factor, additional inputs are introduced into it There are two groups of circuits that match with the "OR output, keys, circuits

"OR and a subtraction device consisting of a trigger and a key, one input of which is connected to the output of said trigger, the potential inputs of two groups of coincidence circuits being connected to the outputs of the packs

equal counters, and pulsed - to the bit outputs of the binary multiplier counter, the input connected to the output of the key of the subtractor, the second input of which and one input of the trigger of the subtracting device

through one additional circuit "OR and additional keys connected to the outputs of devices for automatic change of the quantization frequency, and the other trigger input of the subtractor is connected to the outputs

the "OR" of two groups of schemes of coincidence through the second additional scheme "OR and the second additional keys, the control inputs of which, as well as the control inputs of the first additional keys, are connected to

control trigger output.