SU1257837A1 - Frequency divider with variable countdown - Google Patents

Abstract

The invention can be used in automation devices, measuring equipment and frequency synthesizers. The purpose of the invention is to increase speed. The divider contains blocks 1, 2, and 3 task codes, decades of 4, 5, and 6 units, tens and hundreds, and tires 7 and 8. To achieve this goal, D-triggers 9 and 10, the element OR-NOT 11, the element are entered into the device. NOT 12, the element OR 13 with the formation of new connections between the elements of the device. 1 il. Is: cd 00 00

Description

The invention relates to a pulse technique and can be used in automation devices, measurement techniques, and frequency synthesizers.

The purpose of the invention is to increase the speed.

The drawing shows an electrical functional diagram of a frequency divider with a variable division factor.

The device contains the first, second, third blocks 1, 2 and 3 of the task codes, the outputs of each of which are bitwise connected to the information inputs of decades of 4-6 units, tens and hundreds, the output bus

7 and input bus 8, the first D-trigger

9, the second D-flip-flop 10 with four inverse outputs, element 11 OR-NOT, element 12 NOT, element 13 OR, the first input of element 11 OR is NOT connected to the input bus 8 and the input of element 12 NOT, the second input element 11 OR is NOT connected to the inverse output of the first D-flip-flop 9, and the output is connected to the sync input of the decade 4 units and to the first inverse output of the second D-flip-flop 10, the output of element 12 is NOT connected to the sync inputs of the first and second D-flip-flop 9 and 10, the information input of the first D-flip-flop 9 is connected to the output of the second binary bit decade 4 units, the output of element 13 OR, and the second inverse output of the second D-flip-flop 10, and the direct output of the first D-flip-flop 9 is connected to the information input of the second D-flip-flop 10 and inputs for setting the operating mode of all decades 4-6, d my output of the second D-flip-flop 10 forms the output bus 7 of the device; the first input of the element 13. OR is connected to the outputs of the third and fourth bits of the decade 4 units, the second input of the element 1-3 OR is connected to the outputs of all bits of the decade 5 tens, and the third input is connected to the outputs of all bits of the decade 6 hundreds; the third inverse output of the second D-flip-flop 10 is connected to the transfer output of the decade 4 units and the sync input, decade 5 dozen, and the fourth inverse output of the second D-flip-flop 10 is connected to the transfer output decade 5 dozen and the sync input of the decade 6 hundreds.

The device must be performed on elements of emitter-coupled logic, for example, series of QSOs, K500, which allow the organization of assembly logic operations.

8 As a D-flip-flop 10, a D-flip-flop can be used to invert with the help of NOT elements signals from its direct output (for their "multiplication). An increase in the number of decades leads only to the need to increase the number of inputs of the element, 13 OR, and the number of inverse outputs of the D-flip-flop 10.

The device works as follows.

At the end of the previous account cycle

from blocks 1-3 is entered in the decades 4-6

0

binary-decimal number that corresponds to the initial state of the decade of the Kies., for example, 000 0001 0001 ie Kns I- At the inverse output of the D-flip-flop 9 and the first inverse output of the D-flip-flop 10, zero potentials are set to allow the input pulses to pass from the bus

8 through element 11. At the direct output of D-flip-flop 9, a single potential is established, allowing all decades in subtraction mode.

The input pulses from the bus 8 are fed to the input element 12 and the first input element 11; with a delay due to the propagation time in elements 11 and 12, the inverted input frequency pulses arrive at the sync input of the decade 4 and the sync inputs of the D-flip-flops

9 and 10.

Let the division factor of the N-14 device be given. Then, before receiving the (N-4) th pulse of the input signal, there is a unit potential at the information input of D-flip-flop 9, due to the code set in decades 5 and 6 and in the three most significant bits of decade 4, and exceeding the code of the identifiable state in binary is the basic number system equal to Kos. 0000 0000 0000, The Kos Code is defined by the OR circuit formed by the mounting OR outputs of all the bits of decade 6, the mounting OR of all bits of the decade 5, the "mounting OR outputs of the third and fourth bits of the decade 4, element 13 and the mounting OR outputs of element 13 and the second bit of decade 4. Immediately before the arrival of the (N-4) th pulse of the input signal in decade 4-b, the code K 0000 0000 0010 is set, which exceeds the Kos. As the decade 5 code is 0000, then the transfer output of this decade set to zero potential. Simultaneously with the arrival of a single potential (N-4) th pulse to the synchronization input of decade 4, the information input of D-flip-flop 9 with a delay to trigger one trigger of decade 4 establishes a zero potential, since in the decades 4-6 the code K 0000 00001 is set that in eleven most significant bits corresponds to the code of the identifiable state of Kos. Thus, for the process of counting the last counting pulse, the entire period of the frequency of the input signal is retracted.

With the arrival of a single potential (N-3) th pulse of the input signal to the sync input of decade 4 in decade 4-6 with a delay to trigger one trigger, the code K 0000 0000 0000 is set, which also corresponds to the identifiable code state of Kos. i.e. at the information input of the D-flip-flop 9, a zero potential is maintained; at the output of decade 4, a zero potential is set. Simultaneously with the arrival of a single potential (N-3) th pulse of the input signal to the synchronization input of the D-flip-flop 9, a zero potential is set at its direct output with a trigger triggering delay, which switches the settings of the decade 4-6 the recording mode, and on the inverse output of the D-flip-flop 9 a single potential is set, blocking the second input element 11, the output of which sets the potential. Thus, to trigger the identification device, which is the D-flip-flop 9, the whole period of the input signal frequency is retracted.

With the arrival of a single potential (N-2) -th pulse of the input signal to the synchronization input of the D-flip-flop 10 at its direct output, which is also the output bus 7 of the device, a zero potential, i.e. an output pulse is formed, and a single potential is established at the first, second, third, and fourth inverse outputs. The first inverse output of D-flip-flop 10 forms a mounting OR with the output of element 11, therefore, a single potential is set at the sync input of unit 4, and element 11 is blocked at the output. The second inverse output of D-flip-flop 10 forms an assembly OR with the output of the second binary bit of decade 4 and the output of element 13. The unit potential of the second output output blocks the specified OR circuit, the third and fourth inverse inputs of D-flip-flop 10 form assembly OR respectively with outputs transferring the decades 4 and 5. Therefore, at the synchronization inputs of the decades 5 and 6, single potentials are also set to block the transfer outputs of the decades 4 and 5. The process of setting the decades 4-6 to the initial state, which ends Each time is also equal to the delay in triggering one trigger. Thus, to prepare the command for setting the mode of decade 4-6 to the initial state with respect to the synchronization pulse, the time interval is set equal to the period of the pulse frequency of the input signal.

With the arrival of the (N-1) th pulse of the input signal to the synchronization input of the D-flip-flop 9, a single potential is set at the direct output with a trigger trigger delay, which switches the inputs of the decade 4-6 mode to the subtraction mode, and the inverse of the D-flip-flop 9 is set to zero by A. Sokolov

Editor N. Gorvattehred I. VeresKorrektor M. Sharoshi

Order 5040/57 Circulation 816 Subscription

..- VNIIPI USSR State Committee

for inventions and discoveries

113035, Moscow, Zh-35, Raushsk nab. 4/5

Branch PPP "Patent, Uzhgorod, st. Project, 4

Howling potential, unblocking on the input element 11.

With the arrival of the N-ro pulse, the input signal to the synchronization input of the D-flip-flop 10, a single potential, i.e., is established at its direct output with a delay to trigger the flip-flop. the formation of the output pulse is completed. The signal from the first inverse output of D-flip-flop 10 unblocks the element 11 from the output, from the second inverse output - mounting OR formed by the second binary bit of decade 4 and the output of element 13, and from the third and fourth inverse outputs unblocks the transfer outputs of the corresponding decades 4 and five.

Claims (1)

Invention Formula A variable divider frequency divider containing the first, second, and third blocks of setting codes, the outputs of each of which are bit-wise connected to the information inputs of successively connected decades of units, tens, hundreds, output and input widths, characterized in that increase the speed, it introduced the first D-trigger, the second D-trigger with four inverse outputs, the element OR NOT, the element NOT and the element OR, the first input of the element OR NOT connected to the input bus and the input of the element H E, the second input - with the inverse output of the first D-flip-flop, and the output - with the synchronization input of the decade of units and with the first inverse output of the second D-flip-flop, the output of the element is NOT connected to the synchronization inputs of the first and second D-flip-flops, information input of the first D- the trigger is connected to the output of the second binary bit of the decade of units, the output of the OR element and the second inverse output of the second D-flip-flop, and the direct output of the first D-flip-flop is connected to the information input of the second D-flip-flop and direct outputs The second D-flip-flop is connected to the output width, the first input of the OR element is connected to the output of the third and fourth digits of the decade of units, the second input of the OR element is connected to the outputs of all digits of the ten-decade, and the third input is connected to the outputs of all hundreds of decade of hundreds, the third inverse output of the second D-flip-flop is connected to the transfer output of the decade of units, and the fourth inverse output of the second D-flip-flop is connected to the transfer output of the decade of tens.