SU1501045A1 - Multiplication device - Google Patents

Abstract

The invention relates to digital computing and is intended for use in specialized and universal computing devices. The purpose of the invention is to reduce hardware costs. The multiplying device contains a matrix of single-digit adders and a matrix of elements And, and operates in a conveyor mode. The number of device stages M is determined from the inequality MΤ _max ≥ _max + T _BSmin + T _BKmax where Τ _max is the maximum signal transit time in a one-bit adder, T _BSmin is the minimum time required for correct reading of the result of C, T _BKmax - the maximum switching period of the bits of the multiplier B. Technically, this condition is realized when M = 3, which eliminates the possibility of the appearance of races. 4 il.

Description

The reference relates to digital computing and is intended for use in universal and specialized digital computing devices.

The aim of the invention is to reduce hardware costs.

Figure 1 shows the functional diagram of the proposed multiplication device (dl); Fig. 2 is a functional diagram of the one-bit adder of all rows of the matrix, except the last; FIG. 3 is a functional diagram of a one-bit adder of the last row of the matrix; Fig 44 is a temporary diagram of the device operation.

The device (Fig. 1) contains a matrix of single-digit adders 1.1-1, p, 2.1-1.n., 3.1t3, p, a matrix of elements

And 4, inputs 5.1-5. The bits of the first operand A, the inputs 6.1-6.3. The bits of the second operand B, clock inputs 7.1-7.3, input 8.1 reset, outputs 9.1-9.3 times C, additional inputs 10.1-10.3 .

Each one-bit adder 1.1-1.11 (2.1-2.P) (figure 2) contains a delay element 11, elements NOT 12, elements AND 13, elements OR 14, the first information input 15, the second information input 16, the third information input 17 , control input 18, output 19 of the sum, output 20 of the transfer, control output 21.

Single-digit adders 3.1-3, n (FIG. 3) contain elements NOT 22, elements AND 23, elements OR 24, delay element 25, first information input 26, second information

sd

four

SP

31501045

input 27, third information input 28, first control input 29, second control input 30, sum output 31, transfer output 32, second control output video 33, first control output 34.

The multiplier operates in a pipeline mode, the essence of which is as follows.

In the initial state, the inputs 1 (see Fig. 4) are set at inputs 7.1, 7.2, 7.3, 8.1. Before starting work . The multiplier is fed to input 8.1. During the time it takes to calculate the second stage of the device, output 9.1 occurs; reading the low-order bit C, the product C, and on single-bit adders 3.1-Z.p, preparation is being made for the calculation, by the time 2 Tdldts, the bit B is being fed, the multiplier to the input 6.3.

By the time point, 4-2 G "ats (, - 1, the signal O is applied to the input 7.3, which permits summation on one-bit adders 3.1-3, p. At the moment

dative pulse A reset that resets the one-digit adders 3.1-З.п to the zero state, and the O signal is set at the outputs of the sum and transfer of the one-digit adders 3.1-З.п.

The calculation process begins with the filing of the inputs 5.1-5. An n-1-bit binary double multiplier A and a low bit of the K-bit multiplier B at input 6.1 (the feed moment coincides with the falling edge of the Reset pulse). One time ((.cvi input 7.1

signal O is enabled, resolving sum

mirovanie on one-digit adders 1..p (. - the maximum time of 30 transition process in the logical

25

element And, t 4 + t

maxnb

where L is the value of the time delay of the signal in the delay element,., - the signal O is maximally applied, allowing the first stage to work, and by the time c. 3 lax the signal 1 is supplied to input 7.3, which provides for storing information at the outputs one-time transient time

in the logical element NOT). Through temporary adders 3.1-З.п and prohibiting

m calculation in the first processing of the signals appearing on

line ends at input 7.1 of the information inputs.

Signal 1 is applied, ensuring that all K bits of a factor B

storing the information that has established Q will be supplied, at inputs 6.1-6.3 there is a signal at the outputs of one-bit adders 1.1-1. P and forbidding the processing of signals that will appear at their information inputs (the maximum time of the signal-passing in one-bit adder from inputs to outputs). .

During the time it passes

signal O is applied, and the calculation continues until all n + K bits of product C are received from outputs 9.1-9.3.

Claims (2)

Invention Formula A device for multiplying, containing a matrix of (t p) elements And calculating the matrix of () one-bit sums 1.1-1.P on one-bit totalizers, on one-bit summators (n is the size of the first operand, m is an arbitrary integer), and the first inputs of the elements And i- ro tori 2.1- 2.P is undergoing preparation for computing purposes; by the time of entry 6.2, the bit B of the multiplier B is provided, and by the moment of time, (,,, + t-t, the signal O is sent to the input 7.2, the resolutions are summed over one-bit adders 2.1-2.p. 55 the matrix column (, ..., p) is connected to the input of the corresponding bit of the first operand of the device, the input of the corresponding bit of the second operand of which is connected to the second inputs of the elements And the j-th row of mat20 15. + 2T, a.e. At input 7.2, signal 1 is applied, providing storing information at the second stage of the device and prohibiting the processing of single-digit adders 2.1-2.p signals that will appear at their information inputs. The calculation process proceeds cyclically. While the calculation is in progress at the third stage of the device, the output C of product C is read out at output 9.2, and at the first stage of the device preparation for the calculation is going on, after a time of 3 hours, input 7.1 is fed to the database multiplier B. At the time point trt d +3 s: ; c kt-t, to input 7.1 The signal O is given, which permits the operation of the first stage, and by the time. C 3 llac C a signal 1 is applied to the input 7.3, which ensures the storage of information at the outputs of one bit signal O is applied, and the calculation continues until all n + K bits of product C are received from outputs 9.1-9.3. Invention Formula A device for multiplying, containing a matrix of (t p) elements And the matrix column (, ..., p) is connected to the input of the corresponding bit of the first operand of the device, the input of the corresponding bit of the second operand of which is connected to the second inputs of the elements And the j-th row of the matrix 10 20 25  TZOSHA; The entries (..., m), whose outputs are connected to the first information passes of single-digit adders of the j-th row of the matrix, the transfer output of (k, i) -th single-digit matrix adder (,., t-1) is connected respectively, with the second information input (k + - “1, i) -ro of the one-bit matrix adder, the transfer output (m, i) -ro of the one-bit matrix adder is connected respectively to the second informational input of the (1,1) -th single-digit matrix adder , the output of the sum (k, l) -ro of the one-digit adder of the matrix (, .., n-1) is connected correspondingly with the third information input (k + 1, 1 + 1) -th single-digit matrix adder, output of the sum (t, p) -th single-digit matrix adder (,.,., p) is connected to the third information input (1, p-1) respectively th one-bit matrix adder, outputs of the sum of one-digit adders of the first column of the matrix are connected to the outputs of the corresponding bits of the result of the device, the additional inputs of which are connected to the third information inputs of the single-column adders of the n-th matrix column, the first and second control inputs of each ( m, i) -ro one-bit adder matrix These are connected respectively to the clock input and the device reset input, each one-digit matrix adder, except one-dimensional 35 adders of the last row of the matrix, contains seven AND elements, two OR elements and three NOT elements, with the outputs of the first, second, third and fourth AND elements are connected respectively to the first, second, third and fourth inputs of the first OR element, the output of which is connected to the output of the sum of a one-bit adder; the outputs of the fifth, sixth and seventh AND elements are connected respectively to the first Vym, second and third inputs of the second element OR, the output of which is connected to the transfer output of a one-digit adder, 50 input of the first element is NOT connected to the first information input of the one-bit adder and the first inputs of the first, fourth, sixth and seventh elements AND, the output of the first evil - 55 ment is NOT connected to the first inputs of the second and third elements AND, the input of the second element is NOT connected to the second information input of one-bit thirty 0 five 5 5 0 5 0 the adder, the second inputs of the first, third and seventh elements And and the first input of the fifth element And, the output of the second element is NOT connected to the second inputs of the second and even-grated elements And, the input of the third element is NOT connected to the third information input of the one-bit adder, the second inputs of the fifth and sixth elements And the third D inputs of the first and second elements And, the output of the third element is NOT connected to the third inputs of the third and fourth elements And, each one-digit adder of the last row of the matrix contains nine tons There are AND elements, two OR elements, four NOT elements and a delay element, the outputs of the first, second, third, fourth and fifth AND elements are connected to the inputs of the first OR element, the output of which is connected to the output of a one-digit totalizer and the first input of the fifth And, the outputs of the sixth, seventh, eighth and ninth elements And connected to the inputs of the second element OR, the output of which is connected to the transfer output of a one-bit adder and the first input of the ninth element And, the input of the first element is NOT connected to the first information a single-bit adder input and the first inputs of the first, fourth, seventh and eighth elements AND, the output of the first element are NOT connected to the first inputs of the second and third elements AND, the input of the second element is NOT connected to the second information input of the single-digit adder, second inputs of the first, third and the eighth And elements and the first input of the Sixth element And, the output of the second element is NOT connected to the second inputs of the second and fourth elements And, the input of the third element is NOT connected to the third information input about the bottom accumulator and the second inputs of the sixth and seventh And elements, the third inputs of the first and second And elements, the output of the third element are NOT connected to the third, the third and fourth elements of the inputs to And, the input of the delay element is connected to the first control input of the one-bit adder and the second inputs of the fifth and ninth elements And, the output of the delay element is connected to the input of the fourth element NOT, the output of which is connected to the fourth inputs of the first, second, third and fourth elements And, rub - with their inputs sixth first, seventh and eighth elements And, the third inputs of the fifth and ninth elements And are connected to the second control input of a one-bit adder, characterized in that, in order to reduce hardware costs, in each one-digit matrix adder, except the last row of the matrix, In addition, two AND elements are introduced, an NOT element and a delay element, whose input is connected to the device’s clock input and the first inputs of the eighth and ninth AND elements, fO.3 20 the delay element is connected to the input of the fourth element NOT, the output of which is connected to the fourth inputs of the first, second, third and fourth elements AND and the third inputs of the fifth, sixth and seventh elements AND, the second input of the eighth element AND is connected to the output of the first element OR, the second input the ninth element AND is connected to the output of the second element OR, the outputs of the eighth and ninth elements And are connected respectively to the fifth input of the first and fourth input of the second element OR. 7.} S1 L chg ljfc Pp  /five Lig. 2