SU1698887A1 - Adder-subtracter unit - Google Patents

Description

one

(21) 4813305/24 (22) 04/10/90 (46) 12/15/91. Bul No. 46

(71) Odessa Polytechnic Institute

(72) A.V. Drozd, E.L.Polin, - V.N.Oginsky and Yu.V.Drozd (53) 681.325 (088.8)

(56) USSR Author's Certificate No. 959069, cl. G 06 F 7/50, 1980.

Presnukhin L.N., Nesterov P.V. Digital computers. M .: Higher School, 1974, p.138, ris.3.33.

- (54) DEVICE FOR ADDITION AND READING NUMBERS

(57) The invention relates to computing and can be used in the construction of computer arithmetic units. The aim of the invention is to enhance the functionality of the device by adding positive and negative numbers. The device for adding and subtracting numbers contains register 1, adders 2 and triggers 3 interconnected functionally. 2 Il.

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The invention relates to computing and can be used in computer arithmetic units.

A one-bit accumulating adder is known, containing AND elements, a delay circuit, OR elements and a T-flip-flop.

The disadvantages of such a device are limited functionality due to the accumulation of the sum of only two positive numbers.

Known combinational serial adder containing the first group adder (adder), the first group trigger (circuit P), the register (register of the 1st addend), the register of the 2nd addend and the result register, the output of the register connected to the first input of the adder of the group, the second the input of which is connected to the output of the register of the 2nd term, the transfer output is connected to the output of the first trigger of the group, the information input of which is connected to the transfer output of the first adder of the group, the output of the sum of which is connected to the input of the register the one whose output is the output device.

The disadvantages of the known device are limited functionality due to the sum of only two positive numbers.

The purpose of the invention is to expand the functionality of the device by adding t numbers: m positive and n negative (m + n).

This goal is achieved in that the device containing the register, the first group adder and the first group trigger, the register output being connected to the first input of the first group adder, the transfer output of which is connected to the information input of the first group trigger, the output of which is connected to the first transfer terminal group accumulator, entered from the second to {-and group adders and from the second to & group triggers, the register mode input combined with the group trigger reset inputs and the device initial setup input register sync is combined with group trigger sync inputs and is a device clock input, register information inputs are device n code inputs, the sum outputs of all previous group accumulators are connected to the first inputs of subsequent group adders, the second group adders inputs are the inputs of the corresponding addends of the device, and outputs transferring the adders of the group from the second to the t-th are connected to the information inputs of the corresponding group triggers, the outputs of which are connected to the transfer inputs respectively The group's adders, the output of the sum of the E-th group adder, is the output of the device.

The proposed invention meets the criterion of significant differences because, as compared with the known solutions, it additionally contains group adders and group triggers, which together with the entered links provide the addition of m positive and n negative numbers, which expands the functionality of the device.

FIG. 1 shows a block diagram of the device; in fig. 2 - time diagrams 5 of us, which explain the operation of the device.

The device contains a register 1, adders 2.1, 2.22.Ј groups and triggers 3.1,

3.2, ..., Z. Egroups, and the input of register mode 1 is combined with the reset inputs of triggers 3.1,

0 3.23.1 group and is the input of the initial installation of the device, the synchronous input of register 1 is combined with the synchronous input

triggers 3.1, 3.2З.Ј groups and is

the clock input of the device, the information inputs of register 1 are the inputs of the device code n, and the output is connected to the first input of the first adder 2.1 of the group, the output of the sum of each previous sum of the torus of group 2 is connected to the first input

0 of the subsequent adder of group 2, the second inputs of the adders of group 2 are connected to the inputs of the corresponding addends of the device, and the outputs of the transfer are connected to the information inputs of the corresponding

5 triggers of group 3, the outputs of which are connected to the transfer inputs of the corresponding adders of group 2, the output of the sum of the adder 2.Ј is the output of the device.

The device performs addition in the successive code of m positive and n negative numbers and works as follows.

TI clock pulses of the type of a meander are applied to the clock input of the device, which synchronize the operation of the device. For this, the clock pulses TI are fed to the clock input register 1 and the clock inputs of the trigger group 3.

The input pulse of the device comes to the input of the initial setup of the device, triggers 3.1, 3.2, ..., Z. Group on the reset inputs, as well as the input of register mode 1. In this case, the register 1 switches to the Information reception mode and the TI synchro-pulse is performed writing in the register 1 binary code of the number n, entering the device. Subsequent TI clock pulses are fed to the synchronous input of register 1 after the termination of the NU pulse, when register 1 enters the information Shift mode. Wherein

the binary code of the number n is advanced, starting with the lower bits, from the output of register 1 to the first input of the first adder 2.1 of the group.

The inputs of the addends of the device are received in a sequential code, starting with the least significant bits, m positive numbers and n negative numbers represented in the reverse code — the total of I numbers. These numbers are received (synchronously with the number n advanced from register 1) to the second inputs of the corresponding adders of group 2. The first inputs of all subsequent adders of group 2 receive the sum signals from the sum outputs of the previous adders of group 2. The carry inputs of the adders of group 2 calculated by these adders in the previous cycle, for which the transfer signal from the transfer output of each adder of group 2 is recorded from the information input to the corresponding trigger of group 3, and from its output in the next cycle stupid to the input of the transfer of the adder of group 2. In each

tact of adders 2.1, 2.22.

The next bits of the summed numbers are given taking into account the carry signals received at the previous clock cycle. In addition, the resulting amount is corrected (increased) by the value of the binary code n being moved out of register 1 to be added during one cycle. Such a correction, equal in magnitude to the number of negative terms of numbers, provides the addition of Ј numbers in the additional code. The bits of the result of the addition (in the additional code) are formed at the output of the sum of the adder 2.1, the groups and arrive at the output of the device. The magnitude of the g terms is set sufficiently to obtain a result of the same magnitude (g + 1) -th bit at the output of the device is ignored.

The device is executed on commercially available microcircuits: register 1 - on mic

Roskhema IR13; adders of group 2 - on IM5 microcircuits; triggers 3 - on TM9 microcircuits.

Compared with the prototype, the proposed device allows to calculate the sum of m positive and n negative numbers, which expands the functionality of devices of this type.

Claims (1)

Invention Formula A device for adding and subtracting numbers containing the register, the first group adder, the first group trigger, the register output being connected to the first input of the first group adder, the transfer output of which is connected to the information input of the first group trigger, the output of which is connected to the transfer input of the first group adder, characterized in that, in order to expand the functionality of the device by adding m positive and n negative numbers (m + n 0, the second to the сум adders of the group and the second to the group triggers, the register mode input combined with the reset inputs of the group triggers and the device initial setup input, the register synchronization input combined with the group trigger triggers and the device clock input, the register information inputs are device n code outputs, the sum outputs of all the previous adders of the group are connected to the first inputs of the subsequent adders of the group, the second inputs of the adders of the group are the inputs of the corresponding addends of the device, the transfer outputs of the group adders from the second to the t-th are connected to the information inputs of the corresponding group triggers, the outputs of which are connected to the transfer inputs of the corresponding adders of the group, the output of the sum {- that adder is the output of the device. FIG. one