JP2558735B2 - Digital frequency synthesizer - Google Patents

Description

The present invention relates to an improvement of a general-purpose digital frequency synthesizer used for a network analyzer or the like.

[Conventional technology]

Conventionally, this kind of digital frequency synthesizer has
As shown in the figure, the frequency setting data stored in each register 1 ₁ , 1 ₂ , ..., 1 _m is added by accumulator 2 ₁ , 2 ₂ , ..., 2 _m for each clock CLK input, and the added value Is introduced into the read-only memory circuit 3 as an address. The memory circuit 3 stores the digital value eta corresponding to the sine wave values of the respective angles of one cycle of the maximum value example sinusoidal advance from zero, the accumulator 2 _1, 2 _2, ..., a 2 _m Upon reception of the designation of the address as the added value, specific digital value data having a sine wave value is output. The digital value data from the storage circuit 3 is converted into analog data by the D / A conversion circuit 4 and output as a set frequency signal through the reduction filter 5. The accumulator 2 (2 ₁ , 2 ₂ , ...,
2 _m ) is composed of an adder 2a and a register 2b as shown in FIG. 6. The content of the register 2b and the frequency setting data are added by the adder 2a, and the added value is stored in the register 2b for each clock CLK. To be done. Note that, in FIG. 5, the D / A conversion circuit 4 has a master-slave register built therein.

Here, m-number of accumulators 2 ₁ to 2 _m are continuous connection as FIG. 5, and, if the individual accumulator is configured as FIG. 6, the propagation time is defined as follows be able to. That, t _0: the propagation time of the adders 2a, ... from the lower bits c ₀ to the bit c _4, t _1: adder 2a from the carrier input to the lower bits C ₀ of the accumulator 2 ₁
Propagation time to output Σi, t ₂ : Propagation time from data input Ai (or Bi) of only accumulator 2 _m to upper bit c ₄ , t ₃ : Propagation time from register 2b to output Qi after clock input, t _4: When the register 2b of the setup time (margin time), the following conditions are satisfied for the digital frequency synthesizer to obtain a maximum frequency.

t ₁ + (m-2) t ₀ + t ₂ + t ₃ + t ₄ <(1 / fc) (1) where fc is the clock frequency and (m-2)
Is all accumulators m to both side accumulators 2 ₁ , 2
Means the number excluding _m . Where, in general, t ₀ t
_{If 1} t ₂ and t ₃ + t ₄ = t reg (t reg << 1 / fc), then m <{(1 / fc) −t reg} / t ₀ (2) Therefore, the number of digits that can be set is (m · n) bits with m determined by the equation (2). Reference numeral n denotes the bit line shown in FIGS. 5 and 6, and an address is given to the read-only memory circuit 3 (ROM) by using an L (= m · n) bit line.

[Problems to be solved by the invention]

Therefore, in the digital frequency synthesizer as described above, the number of digits to be set is determined based on the equation (2), and therefore the settlement cannot be increased further. The only way to increase the number of digits is to lower the clock frequency. However, if the clock frequency is lowered, the address setting time to the memory circuit 3 is delayed by the amount of the lowered frequency, and the memory circuit 3 concerned is delayed.
Since the output of digital value data from is delayed, the maximum frequency that can be set becomes low.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a digital frequency synthesizer capable of appropriately increasing the number of digits while keeping a maximum settable frequency constant.

[Means for solving problems]

A digital frequency synthesizer according to the present invention adds frequency setting data for each clock using an accumulator, reads digital value data from a digital value storage circuit (3) based on an address of the added value, converts the digital value data into analog data, and sets the analog data. A digital frequency synthesizer for outputting as a frequency signal, receiving the first clock, and outputting one of the first clocks.
The second clock (CLK
2) Outputting clock generator circuit and multiple accumulators that add lower digit frequency setting data and output the addition result of each accumulator within the given time after receiving the first clock (CLK2) A lower digit accumulator group connected to the lower digit accumulator group, a carry output of the lower digit accumulator group, and a lower digit addition value storage circuit for accumulating the carry output for each second clock; and a second digit after receiving the second clock. By the clock of, the carry output of the lower digit accumulator radar group stored in the lower digit addition value storage circuit and the upper digit frequency setting data are added, and a plurality of accumulators that output the calculation result of each accumulator are continuously connected. Upper digit accumulator group, and each accumulator provided corresponding to each lower digit accumulator group A lower digit storage circuit group for storing a calculation result for each second clock, and a calculation result of each accumulator of the lower digit accumulator group stored in each lower digit storage circuit for each second clock, And a calculation result of each accumulator of the upper digit accumulator group are given to the digital value storage circuit as an address.

[Action]

Therefore, according to the present invention, by adopting the above means, the first clock is input to the lower digit accumulator group, the frequency setting data of the lower digit is added, and the first clock of the first clock is added from the first clock. The output of the lower digit accumulator is stored in the lower digit addition value storage circuit using the second clock delayed by a predetermined time of less than one cycle. Subsequently, the lower digit added value of the lower digit added value storage circuit and the upper digit added value of the upper digit accumulator are added, and the added value is set by the second clock of the next cycle in the frequency setting data of the upper digit and the lower digit. Is added to the address of the read-only storage circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. N is 10 in the drawing a low order accumulator group formed by continuous connection of the accumulator 10 ₁ to 10 _k, to these input for storing the frequency setting data of the lower digit
Registers 11 _{1 to} 11 _k having bit input / output lines are provided, and similarly, registers as a lower digit storage circuit group 12 that stores added value data of accumulators 10 ₁ to 10 _k on the output side as well.
12 _{1 to} 12 _k are provided.

Reference numeral 13 is an upper digit accumulator group formed by continuously connecting accumulators 13 _{1 to} 13 _m . These inputs have n-bit input / output line registers 14 _{1 to} 14 _k for storing the upper digit frequency setting data. Is provided. Reference numeral 15 is a register provided between the lower digit accumulator group 10 and the upper digit accumulator group 13 as a lower digit additional value storage circuit for accumulating the additional value of the lower digit accumulator group 10. 16 the clock CLK1 by a delay circuit for a predetermined time Td (Td <1 / fc) delayed clock CLK2 delayed here the register 12 ₁ to 12 _k, the register 14 ₁ to 14 _k, the accumulator 13 ₁ - 13
_m , the register 15 and the D / A conversion circuit 4. 1
7 is a timing circuit, and this circuit 17 gives a clock enable signal to the lower digit side registers 11 _{1 to} 11 _k and the upper digit side registers 14 _{1 to} 14 _m to send the frequency variable setting data to the lower digit side registers 11 ₁ to 11. it has the function of sequentially stored in the 11 _k and upper digit side register 14 ₁ to 14 _m. In the figure, 3, 4, and 5 are a read-only memory circuit, a D / A conversion circuit, and a low-pass filter, which have the same structure as the conventional one. The D / A conversion circuit 4 has a master-slave register built in here, but the register may be external.

FIG. 2 is a block diagram showing a specific example of the timing circuit 17. That is, in the timing circuit 17, when the data switching signal is input to the first D-type flip-flop 17a as shown in FIG. 3, the Q terminal of the flip-flop 17a becomes high level, and in this state, the second When the clock CLK1 enters the D-type flip-flop 17b, the clock enable signal NCE1 becomes low level and the registers 11 _{1 to} 11 _k are enabled after a delay of the propagation delay time from the rise of the clock CLK1. Next, the second clock CLK2 is third is input to D-type flip-flop 17c, the register 14 ₁ to 14 _m will by its rise propagation delay time delay NCE2 is a low level
Is enabled. In this state, when the first clock CLK1 rises as shown by e, the registers 11 _{1 to} 11 _k rewrite the data. On the other hand, when the second clock CLK2 is climb as elevation of f, register 14 ₁ to 14 _m perform the rewriting of data. Also,
At the rising edge of f, the Q terminal of the fourth D-type flip-flop 17d becomes low level, and this enters the CL terminal of the first D-type flip-flop and makes the Q terminal of the flip-flop 17a low level. As a result, the Q of flip-flop 17b
The pin, that is, the clock enable pin NCE1 goes high. Further, the Q terminal of the flip-flop 17c, that is, the clock enable terminal NCE2 becomes high level because the Q terminal of the flip-flop 17b becomes low level. Further, since the terminal of the flip-flop 17c becomes low level, the Q terminal of the flip-flop 17d, that is, the CL terminal of the flip-flop 17a becomes high level and returns to the original state.

Next, the operation of the synthesizer configured as described above will be described with reference to FIG. When the first clock CLK1 is input to the accumulator 10 ₁ to 10 _k of the lower digits, as shown in 4 (a), the accumulators 10 ₁ to 1
0 _k is a register at the rising edge a of the clock as shown in FIG.
11 Add the frequency setting data from _{1 to} 11 _k and add it. This addition operation uses the first clock CLK1 for delay circuit 16
It is completed by delaying a predetermined time Td until the second clock CLK2 is obtained. Then, the lower digit addition result of the addition in the accumulator group 10 carry out from the accumulator 10 ₁ as shown in FIG. (C) (shown shaded part b)
It is stored in the register 15 at the rising edge b of the second clock CLK2.

Next, when the second clock CLK2 is input as shown in (b) of the figure with a delay of a predetermined time Td after the generation of the first clock CLK1, the lower level stored in the register 15 at the rising edge b of the clock CLK2. Digit addition value output and upper digit accumulator 13 ₁
The upper digit is added by ~ 13 _m (the added value is the shaded area (d) in the figure). This addition operation is performed by the rising edge d of the next clock CLK2.
By the time of 1 / fc. Subsequently, when the first clock CLK1 is input, the added value of the lower digit accumulators 10 ₁ to 10 _k is output at the rising edge c of the clock CLK1 (the hatched portion B in the figure) and stored at the rising edge d of the second clock CLK2. It is stored in the circuit group 12 _{1 to} 12 _k .

Subsequently, the second clock CLK2 is input, the lower digit addition result (shown hatched portion stored in the register 12 ₁ to 12 _k is a low-order memory circuits at the rising edge d of the clock CLK2 (c) is It is output, and each accumulator in the upper digit 13
Result of addition of low-order digit and high-order digit from _{1 to} 13 _m (shaded area in the figure)
Is output.

Therefore, according to the configuration of the above embodiment, since the frequency setting data is added and calculated by the accumulator groups 10 and 13 separately for the lower digit and the upper digit, the number of digits can be easily increased. You can The delay time of the lower digit accumulator group 10 and the upper digit accumulator group 13 is Tdb. In this case, k <{(Td-t reg) / t as in the equations (1) and (2). _{Since the} relationship of ₀ } (3) is established, it is possible to increase the number of (k · n) bit digits with k that satisfies the above expression (3). Moreover, since it is not necessary to lower the clock frequency as in the conventional case, the number of digits can be increased without lowering the maximum set frequency signal that can be output. When changing the set frequency, that is, when changing the frequency setting data, first switch the lower digit setting data, add the lower digit using this data, and then switch the upper digit setting data. It is necessary to add a timing to add the lower digit addition value. The circuit that creates this timing is the timing circuit 17. This operation will be described below. When switching the set frequency data, a data switching signal is input to the timing circuit 17. By the operation of the timing circuit 17 described above, first, the lower digit clock enable signal NCE1 is set to the low level, and the rising of the first clock CLK1 is waited for. next,
Set the upper digit clock enable signal NCE2 to low level,
Wait for the rising of the second clock CLK2. As shown in FIG. 3, at the rising edge (e) of the first clock CLK1, the registers 11 ₁ to ₁ 1
1 _k of the output data, i.e. the lower digit data Setsu換Ri, this data is added in the low-order accumulator 10 ₁ to 10 _k. This added value is registered at the rising edge (f) of the second clock CLK _2.
The output data of 14 _{1 to} 14 _m , that is, the upper digit data is switched, and the upper digit accumulator 13 _{1 to} 13 _m performs the upper digit addition on the lower digit addition value output accumulated in the register 15 of this data. In this way, the set frequency is set by the timing circuit.
With 17, it becomes possible to switch continuously. When the switching of the set frequency is completed, the timing circuit returns to the original state and waits for the data switching signal as described above.

The present invention is not limited to the above embodiment. For example, ask provided with the function of the low-order accumulator 10 ₁ to 10 _k itself registers 12 ₁ to 12 _k, it is not necessary to provide the register 12 ₁ to 12 _k independent illustrated. At this time, the memory circuit group is included in the lower digit accumulator group 10. In addition, the present invention can be modified in various ways without departing from the scope of the invention.

〔The invention's effect〕

As described in detail above, according to the present invention, since the lower digit accumulator group and the upper digit accumulator group are configured to output the additional digit data of the lower digit and the upper digit while independently adding the frequency setting data, It is possible to provide a digital frequency synthesizer capable of increasing the number of digits without lowering the maximum frequency that can be set.

[Brief description of drawings]

1 to 4 are shown for explaining one embodiment of the digital frequency synthesizer according to the present invention.
1 is an overall configuration diagram of the present invention, FIG. 2 is a specific configuration diagram of the timing circuit of FIG. 1, FIG. 3 is a timing chart of the timing circuit of FIG. 2, and FIG. 4 is a digital diagram of FIG. 5 is a timing chart for explaining the operation of the frequency synthesizer, FIG. 5 is a block diagram of a conventional digital frequency synthesizer, and FIG. 6 is a block diagram of the accumulator of FIG. 3 ... Memory circuit (read-only memory circuit), 4 ... D / A conversion circuit, 10 ... Lower digit accumulator group, 10 ₁ to 10 _k ......
Accumulator, 12 ... Lower digit memory circuit group, 12 _{1 to} 12 _k ...
… Register, 13 …… Higher digit accumulator group, 13 _{1 to} 13 _m
...... Accumulator, 15 ...... Lower digit added value storage circuit, 16
... delay circuit, 17 ... timing circuit.

Claims (1)

(57) [Claims] 1. An accumulator is used to add frequency setting data for each clock, and digital value data is read from a digital value storage circuit (3) based on the address of the added value and converted into analog data to obtain a set frequency signal. In the digital frequency synthesizer for outputting, the second clock (CL) delayed by a predetermined time less than one cycle of the first clock after receiving the first clock (CLK1).
A clock generation circuit (16) that outputs K2) and a plurality of accumulators that add the lower digit frequency setting data and output the calculation result of each accumulator within the predetermined time after receiving the first clock A lower digit accumulator group (10) connected to the lower digit accumulator group and a lower digit added value storage circuit (1) for accumulating the carry output of the lower digit accumulator group for each second clock.
5), and from the reception of the second clock until the next second clock, the carry output of the lower digit accumulator group stored in the lower digit addition value storage circuit and the upper digit frequency setting data are added. , A high-order digit accumulator group (13) that continuously connects a plurality of accumulators that output a calculation result of each accumulator, and a calculation result of each accumulator provided corresponding to each accumulator of the low-order digit accumulator group, Lower digit memory circuit group for storing every second clock (12)
For each second clock, the calculation result of each accumulator of the lower digit accumulator group and the calculation result of each accumulator of the upper digit accumulator group stored in each lower digit storage circuit are stored as the digital value. A digital frequency synthesizer characterized by being given as an address to a circuit.