RU2119238C1 - Frequency synthesizer - Google Patents

Abstract

FIELD: radio engineering; radio receivers and transmitters. SUBSTANCE: frequency synthesizer that has series-connected multiplexor, accumulator, storage unit, digital-to-analog converter, and low-frequency filter is provided, in addition, with OR gate whose output is connected to clock input of accumulator; first and second information inputs of multiplexor function, respectively, as frequency-setting input and synthesizer complementary code setting input; multiplexor control input and first input of OR gate are connected to carry output of accumulator; second input of OR gate functions as reference-signal input of frequency synthesizer. EFFECT: simplified design and improved accuracy of output-signal frequency.

Description

 The invention relates to radio engineering and can be used in radio transmitting and receiving devices.

 A known frequency synthesizer containing a reference generator, a storage adder, a delay element, a multiplexer, two code adders, three frequency registers, a code multiplier, a code converter, a digital-to-analog converter, a low-pass filter [1].

 This synthesizer is too complicated and does not provide sufficient accuracy of the output signal frequency.

 Frequency synthesizers are known in which various circuit solutions are used to increase accuracy [2].

 The circuit solutions used to improve accuracy are either complex, for example, a decimal adder circuit, where the circuit speed decreases due to the serial connection of binary adders, or they cannot provide accuracy no worse than the accuracy of the reference generator.

 The objective of the invention is to simplify the device and improve the accuracy of the frequency of the output signal.

 For this purpose, an OR element is inserted into the frequency synthesizer containing a series-connected multiplexer, an accumulating adder, a memory unit, a digital-to-analog converter, and a low-pass filter, the output of which is connected to the clock input of the accumulating adder, while the first and second information inputs of the multiplexer are respectively the frequency setting input and the installation input of the additional code of the frequency synthesizer, the control input of the multiplexer and the first input of the OR element are connected to the transfer output ummatora, the second input of the OR gate is the input reference signal frequency synthesizer.

 The proposed solution meets the criteria of the invention of "novelty", because differs from the prototype in the presence of new functional elements and new relationships between the elements.

 The drawing shows a structural electrical diagram of the proposed device.

 The frequency synthesizer contains a series-connected multiplexer 1 (MX), an accumulating adder 2 (HC), a memory unit 3 (PSU), a digital-to-analog converter 4 (DAC), and a low-pass filter (LPF) 5. Additionally, an OR 6 element has been introduced, the output of which is connected to the clock input of the accumulating adder, while the first and second information inputs of the multiplexer are respectively the input of the frequency setting A and the installation input of the additional code of the frequency synthesizer D, the control input of the multiplexer and the first input of the OR element are connected to the transfer output the accumulating adder, the second input of the OR element is the input of the reference signal Fo of the frequency synthesizer.

 The device operates as follows.

 As is known, in direct digital frequency synthesizers, the formation of a signal of a given frequency is carried out by calculating a linearly increasing phase code at clock times, converting a phase code into a code for the amplitude of a sinusoidal oscillation, digital-to-analog conversion, and low-pass filtering.

The output frequency of the direct digital synthesizer is
_O F = F _o • A / N,
where F _{about the} frequency of the reference signal;
A is the frequency code;
N is the capacity of the accumulating adder.

 The output frequency of standard highly stable oscillators, as a rule, is a multiple of 1 MHz, the capacity of the accumulating adder is equal to the power of 2.

 If the numbers in the numerator and denominator of the fraction are multiple, the real value of the frequency at the output of the device obtained by dividing these numbers does not exactly correspond to the required frequency value, because the result of division is the number is not an integer.

Let us represent the capacity of the accumulating adder as the sum of two numbers - one of them is a multiple of the code of the required frequency A, and the other complements this number to a value that is a power of 2
N = K • A + D,
where K is an integer;
D is the extension code.

 To obtain the value of the output frequency with the accuracy of the reference generator, it is proposed to adjust its capacity in each cycle of the accumulating adder. For this, an OR 6 element is additionally introduced into the known device.

 If there is no transfer signal at the output of accumulating adder 2, the frequency code A is connected to the information input of accumulating adder 2. When a reference signal pulses through the element 6 of the reference signal to the clock input of accumulating adder 2, code A is sequentially added, and the code increments at the output of accumulating adder 2 each pulse of the reference frequency.

 When the accumulating adder 2 overflows, which occurs after the arrival of the next pulse of the reference frequency, a signal appears at the transfer output of the accumulating adder 2, which, controlling the multiplexer 1, connects an additional code D to the information input of the accumulating adder 2 and, simultaneously, arriving through the OR element 6 to the clock the input of the accumulating adder 2 as an additional clock, sums the additional code D with the code of the remainder of the accumulating adder 2.

 At the end of the process of additional summation, the transfer signal at the output of accumulating adder 2 disappears and multiplexer 1 reconnects the frequency code A to the information input of accumulating adder 2, each subsequent pulse of the reference signal continues the summation of code A, a new operation cycle of accumulating adder 2 begins.

 The summation in each new cycle begins with a code equal to the sum of the remainder of the previous cycle and the additional code.

 The generated code values from the output of the accumulating adder 2 are fed directly to the memory unit 3, executed on a programmable read-only memory (ROM), and determine the address of the selection of the amplitude code of the sinusoid from the memory unit 3. A period of a sinusoid with the number of samples equal to the capacity of the accumulating adder (N-D) is recorded in the ROM. The rest of the ROM is not programmed or used. Moreover, each code at the output of the accumulating adder 2 corresponds to the exact value of the envelope of the sinusoid.

 The amplitude code is supplied to the inputs of the digital-to-analog converter 4, at the output of which a multi-level step voltage is obtained, from which a signal of the generated frequency is extracted using a low-pass filter 5.

 The advantage of the proposed device in comparison with the known one is that due to the correction of the capacitance of the accumulating adder in each cycle of its operation, the accuracy of the output frequency of the frequency synthesizer even with multiple values of the capacitance of the accumulating adder and the frequency of the reference signal is determined by the accuracy of the frequency of the reference generator.

 The device proposed by the authors differs from the one known both by the organization of the code converter and by the scheme for converting the generated code values at the output of the accumulating adder into a multi-level step voltage and has the following advantages: the scheme of the claimed device is simpler, the accuracy of the generated frequencies is higher.

Claims (1)

 A frequency synthesizer comprising a series-connected multiplexer, an accumulating adder, a memory unit, a digital-to-analog converter and a low-pass filter, characterized in that an OR element is inserted into it, the output of which is connected to the clock input of the accumulating adder, while the first and second information inputs of the multiplexer are respectively the frequency setting input and the setting input of the frequency synthesizer extension code, the control input of the multiplexer and the first input of the OR element are connected to the transfer output accumulating adder, the second input of the OR element is the input of the reference signal of the frequency synthesizer.