RU2137287C1 - Frequency synthesizer - Google Patents

Abstract

FIELD: radio engineering; radio transmitting and receiving devices. SUBSTANCE: frequency synthesizer has series-connected first register and multiplier, series-connected standard generator and synchronizing unit, first multiplexer, storage unit, series- connected second register, digital-to-analog converter, and low- frequency filter, N input multiplexers, N first adders, N second adders, and N third registers. Accuracy of synthesizer output frequency depends on that of standard generator even at adder capacity and reference signal frequency other than multiples due to correction of adder capacity during each of its operating cycles. EFFECT: simplified design, improved accuracy of output signal frequency. 2 dwg

Description

 The invention relates to radio engineering and can be used in radio transmitting and receiving devices. A known frequency synthesizer containing a reference generator, a storage adder, a delay element, a multiplexer, two code adders, three frequency registers, a code multiplier, a code converter, a digital-to-analog converter, a low-pass filter [1].

 This synthesizer is too complicated and does not provide sufficient accuracy of the output signal frequency.

 Frequency synthesizers are known in which various circuit solutions are used to increase accuracy [2].

 The circuit solutions used to increase accuracy are either complex, for example, a decimal adder circuit, where the circuit speed decreases due to the serial connection of binary adders, or they cannot provide accuracy no worse than the accuracy of the reference generator.

 A well-known digital frequency synthesizer containing a clock generator, a frequency divider, a frequency code generation unit, a control code generator, two phase storage devices, a code multiplier, an accumulation unit, a pulse distributor, three memory registers, a read-only memory unit, a switch, a DAC and a low-pass filter [3].

 This synthesizer does not allow you to get the exact value of the frequency of the output signal.

 A well-known signal synthesizer with a predetermined law of phase change, containing two frequency dividers, a phase and frequency code generation unit, N-1 combination adders, N code converters, N additional memory registers, a delay element, a switch, a memory register, a DAC, a low-pass filter, phase code generation unit, synchronizer, reference generator [4].

 This synthesizer does not provide sufficient accuracy for the output frequency.

 The objective of the invention is to simplify the device and improve the accuracy of the frequency of the output signal.

 For this purpose, N second multiplexers, N first adders, N are introduced into the frequency synthesizer, which contains the first register and the multiplier connected in series, the reference oscillator and the synchronization unit, the first multiplexer, the memory unit, the second register, the digital-analog converter and the low-pass filter, connected in series second adders and N third registers, with the first inputs of the N first adders connected to the respective outputs of the multiplier, the second inputs of the N first adders connected between battle and with the output of the Nth third register, the output of each of the N first adders is connected to the first input of the corresponding second adder, the transfer output of each of the N first adders is connected to the control input of the corresponding second multiplexer, the outputs of the N second multiplexers are connected to the second inputs of the corresponding second adders , the output of each of which is connected to the input of the corresponding third register, the output of each of the N third registers is connected to the corresponding input of the first multiplexer, the output of the first m the lithlexer is connected to the input of the memory block, the output of the memory block is connected to the input of the second register, the outputs of the synchronization block are connected to the clock inputs of the N third registers controlling the inputs of the first multiplexer and the clock input of the second register, while the first inputs of the N second multiplexers are interconnected and are the input signal is "logical 0", the second inputs of the N second multiplexers are interconnected and are the input to which the additional code is supplied.

 The proposed solution meets the criteria of the invention of "novelty", because it differs from the prototype by the presence of new functional elements and new relationships between the elements.

 In FIG. 1 shows a structural electrical diagram of the proposed device, FIG. 2 - time diagrams of the operation of the device.

 The synthesizer contains serially connected first register 3 (RG1) and multiplier 2 (UM), serially connected reference generator 1 (OG), synchronization unit 4 (BS), first multiplexer 5 (MX1), memory unit 6 (PSU), second register 7 (РГ2), digital-to-analog converter 8 (DAC) and low-pass filter 9 (low-pass filter), N second multiplexers 10-1, 10-2, ... 10-N (МХ2), N first adders 11-1, 11-2 , ... 11-N (CM1), N of the second adders 12-1, 12-2 ,. . . 12-N (СМ2) and N third registers 13-1, 13-2, ... 13-N (РГ3), the first inputs of the N first adders connected to the corresponding outputs of the multiplier, the second inputs of the N first adders connected to each other and the output of the Nth third register, the output of each of the N first adders is connected to the first input of the corresponding second adder, the transfer output of each of the N first adders is connected to the control input of the corresponding second multiplexer, the outputs of the N second multiplexers are connected to the second inputs of the corresponding second adders, the output each of which is connected to the input of the corresponding third register, the output of each of the N third registers is connected to the corresponding input of the first multiplexer, the output of the first multiplexer is connected to the input of the memory block, the output of the memory block is connected to the input of the second register, the outputs of the synchronization block are connected to the clock inputs of N third registers controlling the inputs of the first multiplexer and with the clock input of the second register, while the first inputs of the N second multiplexers are interconnected and are the signal input "logical 0", the second inputs of the N second multiplexers are interconnected and are the input to which the additional code is supplied.

 The device operates as follows.

 As is known, in direct digital frequency synthesizers, the formation of a signal of a given frequency is carried out by calculating a linearly increasing phase code at clock times, converting a phase code into a code for the amplitude of a sinusoidal oscillation, digital-to-analog conversion, and low-pass filtering.

где F_о - частота опорного сигнала,
A - код частоты,
P - коэффициент деления (определяется емкостью сумматора).The output frequency of the direct digital synthesizer is

where F _{about the} frequency of the reference signal
A is the frequency code,
P - division ratio (determined by the capacity of the adder).

 To explain the operation of the device, we will present a device diagram consisting of parallel summation paths — N sum forming units (BFS), each of which consists of a second multiplexer 10-1, 10-2, ... 10-N and a series-connected first adder 11- 1, 11-2, ... 11-N, the second adder 12-1, 12-2, ... 12-N and the third register 13-1, 13-2, ... 13-N.

 The second inputs of the first adders 11-1, 11-2, ... 11-N of all N BFS receive a code from the output of the third register 13-N of the N-th BFS, and the first inputs of the first adders 11-1, 11-2, ... 11-N of all N BPSs from the multiplier 2, codes are multiples of the code A (A, 2A, 3A, ...). In each of the BFS, the capacity of the first adder 11-1, 11-2, ... 11-N is equal to P - division coefficient. The N-th BFS, the code from the output of the third register 13-N of which goes directly to the second inputs of the first adders 11-1, 11-2, ... 11-N of all N BFS, performs the function of an accumulative adder operating in steps of NA.

 Summation occurs simultaneously on all BFS, they differ only in the code coming from the multiplier 2 to the first inputs of the first adders 11-1, 11-2, ... 11- N. At the end of the summation process, simultaneous recording is made in the third registers 13-1, 13-2, ... 13-N of all N BFS codes that are intermediate between the NA samples of the phase code and add up to a sequential set of the current phases of the output signal of the device, and the code recorded in the third register 13-N of the Nth BFS, in addition, the source code for the next summation cycle.

 Let us return to the formula (1).

 The output frequency of standard highly stable oscillators, as a rule, is a multiple of 1 MHz, the capacity of the adder is equal to the power of 2.

 If the numbers in the numerator and denominator of the fraction are multiple, the real value of the frequency at the output of the device obtained by dividing these numbers does not exactly correspond to the required frequency value, because the result of division is the number is not an integer.

Imagine the capacity of the accumulating adder as the sum of two numbers - one of them is a multiple of the code of the required frequency A, and the other complements this number to a value that is a power of 2:
N = K • A + D, (2)
where K is an integer
D is the extension code.

 To obtain the value of the output frequency with the accuracy of the reference generator, it is proposed to adjust the capacitance of the adders.

 In each of the N BFS in the absence of a transfer signal at the output of the first adder 11-1, 11-2, ... 11-N to the second input of the corresponding second adder 12-1, 12-2, .., 12-N through the corresponding second the multiplexer 10-1, 10-2, ... 10-N receives the signal "logical 0" and the code from the output of the corresponding second adder 12-1, 12-2,. . .12-N goes to the corresponding third register 13-1, 13-2, ... 13-N.

 When any of the first adders 11-1, 11-2, ... 11-N is overflowed, which may occur after the next recording of the code in the third registers 13-1, 13-2, ... 13-N and, as a result , changing the code at the second inputs of the first adders 11-1, 11-2, ... 11-N, at the transfer output of the corresponding first adder 11-1, 11-2, ... 11-N, a signal appears that controls the corresponding second the multiplexer 10-1, 10-2, ... 10-N connects to the second input of the corresponding second adder 12-1, 12-2, ... 12-N the additional code D, and the input of the corresponding third register 13-1, 13-2, ... 13-N for a new post entry a code equal to the sum of the remainder at the output of each of the overflowed first adders 11-1, 11-2, ... 11-N from the next cycle and the additional code D drops. At the end of the summation process, the resulting value of the sum is written into the corresponding third register 13-1, 13-2, ... 13-N, the transfer signal at the transfer output of each of the crowded first adders 11-1, 11-2, ... 11-N disappears and the corresponding second multiplexer 10-1, 10-2, .. .10-N reconnects the logic 0 signal to the second input of the corresponding second adder 12-1, 12-2, ... 12-N. Overflow signals of the first adders 11-1, 11-2, ... 11-N in each of the FCC are formed independently of each other.

 The total required number of parallel-connected FCCs is determined by their own speed of each of them.

 In multiplier 2, codes of multiples of A. are generated. Codes of these numbers are generated on the basis of typical multiplication schemes or using additional adders. So codes 2A, 4A, 8A, ... are obtained by simply shifting the source code A by a 1, 2, 3, ... digit, and codes ZA, 5A, 6A, ... are obtained by summing (2A + A), (4A + A), (4A + 2A), ... on several additional adders (may be part of the multiplier circuit, not shown in the drawing).

 Block 4 synchronization, the input of which is the signal of the reference generator 3, generates clock signals for recording in the second register 7 and N of the third registers 13-1, 13-2, ... 13-N, as well as control signals for the first multiplexer 5, while ensuring high accuracy of the generated signals (no worse than the accuracy of the reference generator). The output signals of the synchronization unit 4 are shown in FIG. 2b - FIG. 2g, in FIG. 2a - input signals coming from the reference generator 3. The signals shown in FIG. 2b are used to write codes to N third registers 13-1, 13-2, ... 13-N of all N FCCs, time-shifted relative to them and distributed by the number of FCC signals are fed to the control input of the first multiplexer 5 (Fig. 2d - Fig. 2g), shifted relative to the control signals of the first multiplexer 5, the signals are fed to the clock input of the second register 7 (Fig. 2B). In FIG. 2h shows the values of the codes of samples of the sinusoidal function for the case N = 4, reduced to analog form.

 The generated code values from the output of the first multiplexer 5 are fed directly to the memory unit 6, executed on a programmable read-only memory (ROM), and determine the address of the selection of the amplitude code of the sinusoid from the memory unit 6. A period of a sinusoid is recorded in the ROM, with the number of samples equal to the capacity of the adder (RD). The rest of the ROM is not programmed or used. In this case, each code at the output of the first multiplexer 5 corresponds to the exact value of the envelope of the sinusoid.

 The amplitude code is supplied to the inputs of the digital-to-analog converter 8, at the output of which a multilevel step voltage is obtained, from which a signal of the generated frequency is extracted using a low-pass filter 9.

 Compare the proposed device with the known.

 In the known device [1], the capacity of the accumulating adder is adjusted by introducing an additional code, but as a result of further transformations an error appears, leading to inaccuracy of the output signal.

 Justify what has been said.

Consider a part of the circuit of the known device [1] (adder 8, register 9, multiplier 10, converter 11 codes, DAC 12 and low-pass filter 13). The conversion of the codes generated at the output of the accumulating adder 2 into multilevel step voltage codes is carried out after additional subtraction (adder 8) and multiplication (multiplier 10) by an additional number L, which is explained by the fact that the code values for each of P are recorded in the code converter 11 = 2 ⁿ values of the sine wave, and at the output of the accumulating adder 2 codes appear, which are a fraction of the period of the sine wave described by the value (PB).

 The value L = P / (P-B) (a typo is made in the description of the known device [1] in this formula) is a scale factor and, in the general case, is not an integer. But the code at the output of accumulating adder 2 is an integer, the sample address of the code converter 11 is also an integer, therefore, in each case, the multiplication result must be rounded to an integer, discarding the fractional part, which will inevitably lead to an error in the choice of instantaneous values of the output signal amplitude, and therefore, to a deterioration in the spectral characteristics of the output signal, to a decrease in its accuracy.

 Let us explain the above with a concrete example.

Suppose you need to develop a frequency synthesizer with a frequency grid spacing of 5 Hz, the frequency of the reference oscillator is 1.25 MHz, the accuracy of the frequency of the output signal should be no worse than the accuracy of the reference oscillator. The maximum required capacity of the accumulating adder is determined at A = 1, f _out . = 5 Hz and will be equal to 1250000/5 = 250000. The next largest number, which is a power of 2, is 262144 = 2 ¹⁸ , i.e. to implement the conditions set, an eighteen-bit accumulating adder is required. Additional code B is 262144-250000 = 12144. Now for the known device [1], we determine the value of the number L = 262144 / (262144-250000) = 1,048576. The proposed calculation confirmed the inaccuracy of the multiplication procedure in the known device [1].

 Consider the known devices [3] and [4]. The circuits of these devices are quite similar - they use two groups of adders - an accumulating adder for generating a frequency code, a combinational adder for generating intermediate samples of the phase code.

 In general, the ratio of the frequency of the reference generator and the capacitance of the adders is not possible to obtain the exact value of the frequency. If, to increase the accuracy of the output signal, a capacity limitation is introduced, then this must be done for both groups of adders, which is not provided for in known devices.

Furthermore, proposed in the known device [3] the multiplication of source frequency n is only possible if the ratio F _O and F _of sufficiently large and the multiplication result is clearly lower than the capacity of the accumulator.

 The advantage of the proposed device in comparison with the known one is that due to the correction of the capacity of the adders in each cycle of its operation, the accuracy of the output frequency of the frequency synthesizer even with multiple values of the capacity of the adder and the frequency of the reference signal is determined by the accuracy of the frequency of the reference generator, and the proposed adder circuit allows to obtain circuit performance in a simpler way.

Claims (1)

 A frequency synthesizer comprising a series-connected first register and a multiplier, series-connected a reference oscillator and a synchronization unit, a first multiplexer, a memory unit, series-connected a second register, a digital-to-analog converter and a low-pass filter, characterized in that N second multiplexers, N first adders, N second adders and N third registers, with the first inputs of the N first adders connected to the corresponding outputs of the multiplier, the second inputs of the N first adders with are interconnected with the output of the N-th third register, the output of each of the N first adders is connected to the first input of the corresponding second adder, the transfer output of each of the N first adders is connected to the control input of the corresponding second multiplexer, the outputs of the N second multiplexers are connected to the second inputs of the corresponding second adders, the output of each of which is connected to the input of the corresponding third register, the output of each of the N third registers is connected to the corresponding input of the first multiplexer , the output of the first multiplexer is connected to the input of the memory block, the output of the memory block is connected to the input of the second register, the corresponding outputs of the synchronization block are connected to the clock inputs of the N third registers controlling the inputs of the first multiplexer and the clock input of the second register, while the first inputs of the N second multiplexers are connected between themselves and are the input of the signal "logical 0", the second inputs of the second multiplexers are interconnected and are the input to which the additional code is supplied.

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