SU1610599A1 - Frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to simplify the device. The frequency synthesizer contains the main accumulating adder (NS) 1, phase detector 2, low-pass filter 3, controlled oscillator 4, K additional NS 5, 6, 7, combinational adder 8, code converter 9, multiplexer 10, M clock elements 11 ... 17, K delay blocks 18-20 cycles, delay elements 21 ... 26. The main NS 1 is clocked by pulses δ _о (T) with the reference frequency F _о , the contents of the main HC 1 increases with each clock step by the value A. The pulses P _о (T) overflow of the main HC 1 follows with the frequency F _e АА _о / B, where B -capacity of the main NS 1, these pulses come to the input of the phase detector 2 in the loop phase-locked loop. The overflow pulses of the additional HC 5, 6, 7 are transmitted through delay blocks 18 ... 20 to the inputs of the combinational adder 8, which forms a total sequence, which with the help of code converter 9 converts into a position code controlling multiplexer 10, which, together with clock elements Delay 11 ... 17 performs the role of a phase manipulator. 3 il.

Description

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m elements of the clock delay 11-17 K delay blocks 18-20 cycles, delay elements 21-26. The main NS 1 is clocked by pulses (t) with the reference frequency fg, the contents of the main NS 1 is increased with each clock step by the value of a. The R. (t) pulses of the main NS 1 overflow follow with a frequency fg afo / b, where b is the capacitance of the main NA 1 these pulses arrive at the Echo of the phase detector 2 in the loop of the phase-locked loop. Overflow pulses of additional HC 5, 6 7 come through, delay blocks 18-20

to the inputs of the combinational adder 8 which forms a summary sequence, which with the help of code converter 9 is converted into a positional code that controls a multi-stentor 10, which, together with the elements of the clock delay P-17, performs the role of a phase nanipulator.

This invention relates to a radio technician and can be used in transmitting; . and measuring equipment. - -

The aim of the invention is to simplify the device.

Fig. 1 shows an electrical structural diagram of the frequency synthesizer in Fig. 2, time diagrams of the operation of the device with two additional accumulators; figure 3 - the nature of the interference with two additional accumulating adders,

The frequency synthesizer contains the accumulator adder (NS) 1, phase detector 2, low pass filter 3, controlled oscillator 4, the first, second and third additional NS 5-7, combinational adder 8, converter 9 code, multiplexer 10, m elements of the clock delay 1 1 17 for delay blocks 18–20 for c1slams, i delay elements 21–26,

The frequency synthesizer works as follows.

The number a, specifying the output frequency - that fg, goes to the first code input HC1, whose capacity is equal to the number b present on the second code input NS 1. The HC1 is clocked by the implII (J (j (t) with the reference frequency f. and generates a step-like sawtooth function a (t) at the code output increasing at each clock step by value a. Impulses) of HC1 overflow follow with a frequency equal to 10 decade frequency synthesizers, on average, in which the frequency grid step is 10 where g - integer positive or negative number, frequency fg and number b are usually chosen constant and multiples of ten.

Through a hectare of clock delay elements II - 17 and multiplexer 10, one of the keys of which is necessarily closed, the overflow pulses arrive at phase detector 2 and are basic to the phase locked loop system, which also contains filter 3 and controlled oscillator The torus 4. The phase-locked loop is designed to filter out the fragmentation contained in the overflow signal p (t) HC1.

The variable code a (t), which is formed at the output of HC1, arrives at the first code input of the first additional HC 5, which enters the circuit of a series-connected additional accumulating adders 5-7, clocked by pulses P (t) delayed by the first k of m elements the clock delay is 11-13 at the time of i T clock cycles, where i is the sequence number of the first second or third additional NS 5-7, or, equivalently, the sequence number of the clock delay 1 i. 13, T 1 / f - the duration of the cycle.

When HCI overflows with a pulse) in the first additional HC5. the remainder is recorded in the function a (t), and then with each filling cycle of the main HC1, the first additional HC 5 accumulates residues in the form, a function of O i iCt). The capacities of the first, second and third additional NS 5-7 are the same and equal to the number a, which enters the second inputs of these adders, whereby the capacity of the first second and third additional NS 5-7 varies with frequency tuning, i.e. when changing the number a.

Each subsequent (second and third) additional HC 6 and 7 accumulates the remnants of the previous one, since the output code (t) i -ro additional 9 HC is an input code for (i + 1) -th HC. Total figure 1 shows additional NA 5 - 7, but if necessary, their number can be increased.

The overflow pulses (t) of optional HC 5 7 enter the corresponding k delay blocks 18 20, the elements of which are clocked by a pulse 10

it transmits an overflow pulse HC1, delayed by elements of a clock-- delay 11 - 17 for the corresponding number of clock cycles T. If, for example, the value of the sum S (t) on one of the cycles filled with HC1 is equal to +3, jumps from the leftmost key of the multiplexer

10 and the multiplexer output 10 pop. gives impulse P (t-T), and if S (t) is 4-1, then the third from the left is closed - CCUCH of the multiplexer 10 (in Fig. 1 it is closed) and the output is pulse P. (t-ЗТ). Multiplexer 10, so

P (t) themselves. Each i-th block of delay 15 rev, az, together with elements 18-18 of the circuit contains i delay elements 21-26 and serves to obtain a series of S (t) numbers, which are coefficients in the Pascal-del triangle (1-1) th degree of difference of two quantities. At the output of the first delay unit 18, consisting of a single delay element 21, the overflow pulse P (t) of the first additional HC5 appears on the next cycle after the overflow of HC1, in this case the series S (t) is the indicated overflow pulses whose value in the combiner 8 is +1. The second delay unit 19, connected to the output of the second additional HC6, contains two delay elements 22 and 23. The overflow pulse P (t) taken from the output of the delay element 22 has a weight value of +1, and the weight of this pulse delayed for one cycle in the delay element 23. is equal to -1. The third delay block 20, consisting of delay elements 24 - 26, forms a series S, (t), which is a sequence of numbers + 1, - 2 and +1, following each other at intervals equal to the duration T .c filling cycle HC1.

Combinational adder 8 forms

the summation sequence S (t), which is transformed with the aid of the code converter 9 into a positional code controlling the multiplexer 10 each. the combination of numbers obtained in the combinational adder B corresponds to the logic level in one of the bits of the 7-bit control bus of the multiplexer 10, which is different from the logic levels in the other bits. Under the action of the specified logical level, the corresponding key of the multiplexer 10 closes, and at the output of post-support 11–17, plays the role of the controller's phase mapper. The phase of the pulses commuted by the keys of the multiplexer 10 equal to 1 1 m (with an accuracy of one 20 key) from the extreme keys of the multiplex 10, is taken as zero, and then the time shift of the pulse O (t) at the output of multiplexer 10, expressed in the number of cycles T is equal to the number 25 S (t) at the output of the combinator driver 8. The keys of the multiplexer 10 and the elements of the clock delay 11-17, located to the left of the zero key, create an advance in phase, and

30 on the right - lag.

If the amount is extra. HC 5 - 7 is reduced to two (the third additional HC7 is eliminated), the number of combinations S (t) of the S, (t) and S2 (t) series sums is reduced to four, namely S (t) can be +2, +1, O and -1. Therefore, the need for clock delay elements 15-17 and the corresponding keys of the type 40 multiplexer 10 will fail. There is also no need for delay elements 24-26. The key becomes zero, the pulses P (t-3T). The number of rows of control multiplexer DCs is reduced to four.

Considered, the principle of modulation of the signal (t) allows to transform the spectrum of fractional noise at the output of the multiplexer 10 in such a way that its power decreases significantly at low frequencies and increases at high frequencies. The interference in the high frequency region is effectively suppressed by the filter and the resulting signal-to-interference ratio at the output of the frequency synthesizer increases.

55

Using Figures 2 and 3, the operation of the frequency synthesizer is shown.

10599

ten

it transmits the overflow pulse HC1, delayed by the elements of the clock - delay 11 - 17 for the corresponding number of clock cycles T. If, for example, the value of the sum S (t) on one of the cycles filled with HC1 is equal to +3, then the multiplexer will jump to;

10 and the output of the multiplexer 10. Gives impulse P (tT), and if S (t) 4-1, then the third from the left is closed - K.THÜCH m of the multiplexer 10 (in Fig. 1 it is closed) and the output passes the impulse R. (t-ЗТ). Multiplexer 10, so

5 obr, azom, together with elements over 50

The holders 11–17 perform the role of a phase puller. The phase of the pulses switched by the keys of the multiplexer 10 is equal to 1 1 m (with an accuracy of one 0 key) from the extreme keys of the multiplexer 10 is taken as zero, and then the time shift of the pulse O (t) at the output of the multiplexer 10, expressed in the number of clock cycles T, the number 5 S (t) at the output of the combinational adder 8. The keys of the multiplexer 10 and the elements of the clock delay 11-17, located to the left of the zero key, create an advance in phase, and

0 right - lag.

If the amount is extra. HC 5 - 7 is reduced to two (the third additional HC7 is excluded), the number of combinations S (t) of the S, (t) and S2 (t) series sums is reduced to four, namely S (t) can be +2, +1 , O and -1. Therefore, the need for the elements of the clock delay 15-17 and the corresponding keys of the multiplexer 10 of the multiplexer 10 will fail. There is also no need for delay elements 24-26. The key, which pulses P (t-3T), becomes zero. The number of bits of the control multiplexer DC is reduced to four.

Considered, the modulation principle of the signal (t) allows to transform the spectrum of fractional noise at the output of multiplexer 10 in such a way that its power decreases significantly at low frequencies and increases at high frequencies. The high frequency interference is effectively suppressed by filter 3, and the resulting signal / interference ratio at the output of the frequency synthesizer increases.

55

Using Fig.2 and 3 demonstrated the operation of the frequency synthesizer with

16105998

torus, combinational adder, k qiu delay blocks, the input of the first and second cycle delay blocks are connected respectively to the overflow outputs of the first, second, k-ro additional accumulating adders, the first, second, cycle delay blocks containing one, two, k series-connected delay elements, the outputs of which are connected to the corresponding inputs of the combinational adder, the first and second code inputs

ten

two additional NA 5.6, In this case No. 1, ,, L 71.

Denoted by the duration of the j-ro filling cycle HC1, expressed by the number of cycles of the reference pulse sequence (j (t) with the frequency TP), Phase detector 2 is assumed to be a sample-memory type pulse-phase detector, Pulses (t) are -. Mutating, and pulses with a frequency of C signal determine the beginning

of the next circuit of switched dial-up.,., n-o, “to the second code inputs

shaped voltage. Then, the magnitude, 5, and the clock input of the accumulating amount of interference at the output of the phase detector are respectively the first

,,, proportional to the difference, .- and the second code inputs and clock

t JJiC and jTj are the moments by the input of the frequency synthesizer, about t l and the pulse of pulses, respectively, in that

the reference and signal | 1 sequential Simplification of the synthesizer, between the output of tei, the corresponding inputs of the phase combination adder and the second detector 2 .. the input of the phase detector is set to

As can be seen from the diagram, a reduced, therefore connected

In Fig. 3, with an increase in the number of code points and a multiplexer, as well as in additional NN 5 - 7, process 25 is introduced in series, the junction becomes more dynamic, the clock of the elements of the clock delay increases. Calculations on the computer whose inputs are combined and connected to the clock input of the accumulating adder, the clock input of each of the 30 delay elements in the first,

second, the kM cycle delay blocks are connected to the overflow output; it shows that the spectral components of the process of the form shown in Fig. 3 in the low-frequency region up to 10% of the signal frequency fg are several orders of magnitude lower than the corresponding components of the process, in the absence of a totalizer, which is also connected to the NS 5–7. Since the wheelbase is connected to the input of the first of the two frequency components, it is effectively 35 elements of the clock delay, the output of each is suppressed by filter 3, and the gain from the m elements of the clock delay is The signal-to-noise ratio is connected to the corresponding input significant. the multiplexer, while the outputs of the first time as the m clock elements k of the m clock delay elements P - 17 and the delay elements 40 ki are connected to the clock input, respectively, 21-26, D-triggers can be used, supplementary accumulation as a combinative sum adder, the second code pa 8 is a combinational adder, you select the input of each of the k additional inputs on the simplest binary sum accumulators connected to the first code input of the accumulating adder, the number of sum iruemyh combinations of Raman summa- k i is a torus, codewords into

-, ..J -., .... itinc: pci - the output of the first, second, and kth blocks: a torus, a phase detector, and a lower filter 50 of the cycle delays form coefficients that accumulate the adder ,, k elements respectively, the first, the second, therefore, the connected additional k-th rows of the Pascal triangle; accumulating adders; the code is equivalent to the sum of the modules of the coefficients; the first input is connected to all the rows of the triangle;

the code output of the accumulated amount is 55 ..

tori.

Claims (1)

Formula of Invention Frequency Synthesizer Containing Ring-Operated Generator JLJLJLJl Jl JLJl JLJL LJl nn P nn n PPP PP PP n ± w L  r Ppppppppp, 4 yes El “U W D 9 W“ W JL TPL PPPPPPP L P ry ppppppppppppp. JI I L I I I +1 t ... j {il  - / f +1 -1 0 -i 0 -fi 0 1 1  -i -ti to l 0 -tl I p p p p p p p p p p p p i p 6 65 7 56 7 647 5 b 12 17 14 gd 354248 51 59 64 5.92 Has 1115 23.61 29.58 35.541.4247, 11,65, Bt and OflS CPU 0.33-ass-0.5 0.580.61 - 1.2S -0, G1-1.08 Fig. g lsch 1.0 0.5 ABOUT 0.5 1.0  r S D 9 TPL JI I L +1 t ... j {il  - / f -1 0 -i 0 1 1  -i -ti to l 0 -tl