SU1501265A1 - Frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase the spectral purity of the output signal. The frequency synthesizer contains a reference rr 1, a phase detector 2, a low-pass filter 3, a tunable rr 4, a 5 code drive, a two-channel distributor of 6 signals, a multiplexer 7, a digital-to-analog converter, an integrating link 9, and an elec- tron of bit 10. The signal of gd 1 arrives at phase detector 2 and synchronizes the operation of rg 4 phase self-tuning ring. Since the inputs of phase detector 2 receive periodic signals, in the synchronization mode of the phase-locked loop, a signal is generated at its output proportional to the phase difference compared signals. The filter 3 then filters out noise equal to or a multiple of the reference frequency. At the same time, the attenuation coefficient does not depend on the influence of such factors as temperature fluctuations, power supply voltage loss, aging of the elements. 2 Il.

Description

H

fig1

3150

The invention relates to radio engineering and can be used to obtain a grid of stable frequencies in transceiver and measurement equipment.

The aim of the invention is to increase the spectral purity of the output signal.

Figure 1 shows a structural electrical circuit of a frequency synthesizer; figure 2 - timing charts of his work.

The frequency synthesizer contains a reference oscillator 1, a phase detector 2, a low-pass filter 3, a tunable oscillator A, a 5 code drive, a two-channel01 signal distributor 6, a multiplexer 7, a digital-to-analog converter (D / A) 8, an integrating link 9, a bit element 10. Fig. 2 shows: pulses from the output of a tunable generator (Fig. 2a), the output signal of the code accumulator (Fig. 26), the signal from the overflow output of the code accumulator (Fig. 2c, the signal from the first output of the two-channel distributor of pulses (Fig. .2g) signal from the second output two-channel signal distributor (2E), a signal output from the multiplexer (2e), the output integrating unit (2g), a reference pulse generator (fig.2z).

The frequency synthesizer works in the following way.

The output signal of the reference oscillator 1 with the frequency RD is fed to the first input of the phase detector 2 and synchronizes the operation of the phase locked loop. In the synchronization mode, the frequency F of the tunable generator 4 is determined by the expression

F UF-P,

where A and P are positive integers

numbers; L Fg / A - frequency grid step.

At the same time, A is a constant value at the selected frequency grid step & F, and P is a variable value, equal to the required value of storage unit 5.

Tunable output

generator 4 with period T - (time diagram a) arrives at

50

five

0

five

five

0

five

The input of storage unit 5 ensures synchronization of operation at 5. Within the capacity (module) of drive 5, change of information at its output occurs with a constant increment of A (time diagram b), while at the output of overflow of drive 5 there is a level O ( temporal diagram c). When the current information values of the QD exceed the value of P, level 1 is generated at the output of accumulator 5, and the remainder value R (KT) is transmitted to the second code input of multiplexer 7. The overflow signal from the output of accumulator 5 enters the single-start input of a two-channel distributor 6 , the synchronization of which is also carried out by the output signal of tunable generator A.

8 two channels of the two-channel distributor 6 forming the leading edges of the output signals synchronously

and determined by the arrival time of level 1.

The duration of the output signals of the two-channel distributor 6 differs by one period T (timing diagram of the guide), the duration of the signal at the output of the first channel is t, IT, at the output of the second channel t (1 + 1) T, where 1 is an integer in the range. The output signal of the second channel of the two-channel distributor 6 is fed to the control input of the multiplexer 7 and switches it. In this case, during the time t, the multiplexer transmits information from the second code input to the output, and in the absence of a pulse, the value of the number A comes from the first code input of the multiplexer 7 (time diagram e). D / A converter 8 converts the output variable code of multiplexer 7 into a step voltage sequence.

The integration of the step voltage by the integrating link 9 causes a linear increase in the signal at its output, and the steepness of this process is proportional to the current code value at the output of the multiplexer 7. The output of the integrating link

9 connected to bit 10,

which for a duration t

a pulse arriving at its control input provides the discharge of the integrated link 9 and its initialization. As a result, the signal at the output of the integrating link 9 has the form shown in the time diagram 17.

in the first time interval Oitfrt, the integrator 9 is fully discharged; in the second time interval during one period T, the voltage at the output of integrator 9 increases in proportion to the current value of the accumulator 5, In the third time interval, the voltage increases in proportion to the constant code value A (here To the whole part of the relation). The change of information at the output of accumulator 5 occurs at discrete points in time of the CT, the period of the pulse sequence at the output

the overflow of accumulator 5 varies discretely and is not equal to the period T of the frequency of the reference oscillator (timing diagram h). However, the average period of the sequence (in the example given for ten counting cycles) corresponds exactly to the period T,

In the second time interval, the linear charge of the integrating link 9 occurs at a rate proportional to the current code value of the residual RL, where L is the transfer coefficient of the DAC 8 and the integrating link 9. In the third time interval between the points 2-0, the time diagram of the charge occurs with constant speed, proportional to the code of the argument, t, e. A-L, and this signal has a clearly pronounced periodic character, and the period of the voltage formers and divider of the clock signal is exactly equal to the period of the dot with a variable coefficient Td of the output signal of the reference generator 1, in the region of the outgoing voltages,

division, Formulas

and 3 o b

limited dotted li50

R e te and

A frequency synthesizer containing a series-connected reference oscillator, a phase detector, a low-pass filter, and a tunable oscillator, as well as a code accumulator and a digital-to-analog converter, the input of the code accumulator argument is the first efficiency factor that differs from ncjihhi lead

and 5. and

mox

where and „„, 1. (A, - 1), and

  - (1 + 1) ..

1K1 since the inputs of the phase detector 2 received periodic signals, then the synchronization of the ring

01265

phase-locked loop at its output, an output signal is formed, the ratio of the 11n {the Laz difference of the compared

from signals. Filter 3 filters (filtering interference equal to or a multiple of the frequency of comparison F

As a phase detector, various types can be used.

10 phase detectors, both of the sample-remembering type and trigger phase detectors. In the latter cases, the composition of the phase detector 2 must include a threshold element providing

15 the formation of pulses necessary for the operation of the trigger (in FIG. 1 is not shown). The tripping threshold voltage must satisfy the above limitation.

20

and and and,

Min

Thus, the whole process of compensating for discrete phase oscillations of the signal of accumulator 5 is carried out by digital methods with subsequent conversion into an analog signal. In this case, the departures of the parameters of the DAC 8 or integrator 9 do not

they are reflected in the deterioration of the compensation effect, since their weight ratios at the second and third time intervals remain constant A / R (KT) and do not depend on the coefficient

L. Consequently, the attenuation factor of the frequency synthesizer noise does not depend on the influence of such factors as temperature fluctuations, voltage loss of the power supply source, and element aging.

In addition, a simplification can be achieved in the synthesizer, since the use of dividers, voltage adders and a frequency divider with a variable coefficient is not necessary to form a grid of frequencies.

division, Formulas

and 3 o b

R e te and

A frequency synthesizer containing a series-connected reference oscillator, a phase detector, a low-pass filter and a tunable oscillator, as well as a code accumulator and a digital-to-analog converter, the input of the code accumulator argument is the first efficiency factor that differs from ncjihhi lead

the spectral frequency of the pyhodio signal, between the ear of the overflow of the code accumulator and the second input of the phase detector, are connected in series a two-channel distributor of signals and a bit element, as well as a multiplexer and an integrating link, the output and input of which are connected respectively to the second input of the phase detector and the output of the figure. whose input is connected to the multiplexer output, the control

a i

FG

30 20

o °

I, I, I, I, I, I, I, I, I, I, I, I

 5G - t-,

input, the first code1, p1 input and the second codone input of which are connected respectively to the second output of the two-channel signal distributor, to the first code input of the frequency synthesizer and to the code output of the code accumulator, the clock input of which is combined with the clock input of the two-channel signal distributor and connected to the output of a tunable oscillator, and the control input by the code storage module is the second code input of the frequency synthesizer.

% -rf / jf //

-% LH / XT

Claims (1)

Claim A frequency synthesizer containing a reference oscillator, a phase detector, a low-pass filter and a tunable oscillator, as well as a code storage device and 55 digital-to-analog converter, the input of the code storage argument is the first code input of the frequency synthesizer, distinguishing ”with the aim of increasing spectral purity of the output signal, between the output of the overflow of the code accumulator and the second input of the phase detector, series-connected two-channel signal distributor and element are connected discharge, as well as a multiplexer and an integrating unit, the output and input of which are connected respectively to the second input of the phase detector and the output of the digital-analog converter, the input of which is connected to the output of the multiplexer, the control input, the first code input and the second code input of which are connected respectively to the second output of the two-channel signal distributor, to the first code input of the frequency synthesizer and to the code output of the code store, the clock input of which is combined with the clock input of the two-channel a signal distributor and is connected to the output of a tunable generator, and the control input module of the code storage unit is the second code input of the frequency synthesizer. FIG. 2