SU446940A1 - Frequency multiplier - Google Patents

Description

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The invention relates to the technical means of the ancillary equipment, in particular to wide-range frequency multipliers, and can be used in computing devices, in automatic control systems, telemechanics and other devices having a frequency output.

A frequency multiplier is known comprising a controlled oscillator, a frequency divider in the feedback circuit, and a trigger.

However, in a well-known multiplier, the operation of the frequency range being multiplied (synchronization and capture bands is insignificant,

In order to expand the synchronization capture bandwidth and protect the multiplier circuit from loss of multiplied frequency pulses, a clock pulse generator, four timing circuits, two trigger counters, a protection circuit and a bank demodulator are inserted into the proposed frequency multiplier, and the clock pulse output is directly connected to one inputs of trigger counters and cut two synchronization circuits - to the 5 second inputs of the same trigger meters, the outputs of which through two other synchronization circuits are connected to the inputs of the protection circuit. the output of the latter through a series-connected trigger and an balanced demodulator is connected to the input of the controlled oscillator

The drawing shows a functional diagram of the proposed frequency multiplier.

 The proposed multiplier contains generator I clock and pulse four timing circuits 2-5, two trigger counters b and 7, protection circuit 8. trigger 9, balanced

0 modulator 10, controlled oscillator II, frequency divider 12,

The principle of operation of the frequency multiplier should be considered in three modes,

In the first mode, in the absence of I pulses of the multiplied frequency f, and pulses of frequency, / ooratnoy communication, the scheme works as follows. The generator of I clock pulses periodically produces unipolar pulses of clock frequencies F, Y (Gg of their oscillations shifted in time by half the period of their oscillations. Pulses of clock frequency / 7 arriving at the counting inputs of the lower bits of trigger meters 6 and U, which act as an integrating device, synchronously they are filled in. Due to the initial recording of the unit in one of the high-order bits of the trigger counters, the output pulses from the high-order bits of the counters are shifted in time by exactly half of their period. 8 on the trigger 9, converting together with the trigger counters 6 and 7, the input frequency and feedback frequency pulses into a pulse width pulse voltage, the average value of which is proportional to the time integral of the frequency difference // and / g, these pulses cause an oscillating trigger mode with a duty cycle of 0.5, while the voltage at the output of the balanced demodulator 10 is absent, since it is made according to a balanced circuit and is an active RC low-pass filter with an amplifier. In the second renim, the operation of the circuit in the presence of multiplied frequency pulses /, is as follows. The frequency pulses / enter the input of the synchronization circuit 2, which memorizes them by changing the state: I have a flip-flop included in this circuit, and introduces frequency pulses / g to the second counting input of the trigger counter 6 synchronously with the clock frequency fi, Similarly, synchronization circuits 3, and 5, as a result of which the multiplier circuit is protected from failures and without loss of information. In addition to the clock pulses of the frequency FI, the trigger counters 6 and 7 are filled with pulses of frequencies / g and D, which leads to a change in the duty cycle of the pulse voltage of the trigger 9, which in turn causes the appearance of the average DC voltage at the output of the balanced demodulator 10 .0 At the output of the controlled oscillator AND, a pulsed voltage appears, whose frequency corresponds to the division factor set on frequency divider 12. Therefore, in the steady state, the equality / f, is strictly maintained. In the third mode of the workflow of the frequency multiplier, an abrupt change in the value of the frequency to be multiplied may occur, and a malfunction occurs, irretrievably lost a certain number of multiplied frequency pulses and a breakdown in synchronism; To avoid this, the cxqMa of protection 8 is provided in the multiplier, which is a reversible controlled shift register that, together with trigger counters 6 and 7, ensures the smooth operation of the multiplier in dynamic modes. With a sharp increase in the frequency ji (however, under the condition of /,) the frequency of the output pulses from the high bit of the trigger counter 6 can exceed the frequency of the output pulses from the high bit of the trigger counter 7 by two or more times. In this case, the reversible shift register of the protection circuit 8 terminates the oscillatory mode of the trigger 9, setting it to a state in which the full voltage is applied to the controlled oscillator, and the latter, producing a higher frequency signal, performs compensation for the error in the circuit. At the same time, the protection circuit remembers the number of mismatch pulses and resolves the normal operation of the output trigger only under the condition of full compensation. With this method of protection of the multiplier circuit, the dynamic indicators somewhat deteriorate, but there is no loss of synchronism and irretrievable loss of multiplied frequency pulses. The capacity of the dynamic memory of the protection circuit is determined by the formula Q-2 (m-2), where n is the number of bits of the trigger 1 counter ; gp is the number of bits of the reverse register. The circuit returns to normal operation automatically as the difference between the number of frequent pulses /, and the number of frequency pulses / g decreases. Due to the frequency-phase principle of the digital-to-analog integrator, the properties of a discrete frequency divider and the construction of a feedback multiplier, the static multiplier accuracy can reach 0.01 and higher. When selecting the appropriate elements, the clock frequencies can be on the order of megahertz, and the time constant of the active RC filter can be on the order of several microseconds, which ensures a relatively high dynamic accuracy of the multiplier. The frequency multiplier is a digital astatic tracking system of a frequency-phase type, and since it has trigger counters 6 and 7 that play the role of integrators and, moreover, there is a dynamic memory on register 8 when multiplying low frequencies in the pauses between pulses The input signal does not open the feedback circuit. Due to this, in the multiplier, the synchronism band coincides with the capture bandwidth, which, in turn, are determined by the properties of the applied frequency tunable generator. For example, when using a device as a controlled oscillator of a wide-range multivibrator type with an overlap factor of 40 °, the frequency is of the order of 10 at an input signal frequency of 0.1 + 1000 Hz (frequency overlap 10), the capture frequency and synchronism range coincide with the frequency range of the signal, therefore The proposed frequency multiplier can be effectively used for multiplying low and infra-low values with significant (on the order of 10 or more) and multipliers. SUGGESTS INVENTIONS; A frequency multiplier containing a controlled oscillator, a frequency divider in the feedback circuit, and a trigger, characterized in that, in order to broaden the synchronization acquisition band and protect the multiplier circuit from loss of the multiplied frequency pulses, four clock circuits two trigger counters, a protection circuit and a balanced demodulator, while the output of the clock generator is connected directly to one of the inputs of the trigger counters and through two synchronization circuits-- to the second inputs quiet same trigger counters, the outputs of which two other synchronization circuits are connected to inputs of the protection circuit, the output of the last flip-flop through the serially connected and balanced demodulator connected to an input of a controlled oscillator.

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