SU428566A1 - DIGITAL DEVICE OF FREQUENCY AUTO CONSTRUCTION - Google Patents

Description

The invention relates to the field of radio communications and can be used as a reference reference generator for receiving phase-mapped signals with an unstable carrier frequency.

A digital frequency-controlled digital device containing a feedback mixer, the output of which is connected through a limiter to the input of a digital frequency discriminator, the outputs of the tip of frequency errors through an NMR addition and exclusion generator, is connected to the counting input of the frequency divider, which is connected to the counting input of which is connected to the output clock. and the output of the frequency divider is connected via a voltage multiplier and a frequency multiplier to the heterodyne input of the feedback mixer.

A disadvantage of the known device is the wide pickup band of the frequency auto-tuning ring and, accordingly, the reduced noise immunity of the auto-tuning due to the occurrence of an astatic frequency detuning.

In order to increase the noise tolerance of frequency auto-tuning in the proposed device, the output of the digital frequency discriminator is connected to the input of the frequency error accumulator via the additionally entered combining node, to the second input of which the output of the frequency error accumulators is connected through the additionally input node of the static offset of the frequency detuning associated with the release of the chronizer.

The drawing shows a functional diagram of the proposed digital frequency locked loop device for a coherent phase demodulator.

The device contains a frequency multiplier of 1 per l, where n is the multiplicity of the phase-shift keyed signal, a mixer 2 feedback loops with filtering cascade 3, a chromatiser 4 with outputs 5-7, a controlled divider 8, a multiplier of pru lions 9, a multiplier of 10 frequencies per g frequency limiter ring limiter 11, digital frequency discriminator 12 with measuring input 13, output 14 pulses c with OUTPUT 15 characters, unification node 16, drive 17 frequency ohibi with driver / 5 addition pulses and exceptions, astatatic komplenatsii node 19 Frequency detuning, narrowband phase-locked loop filter 20 with limiter 21, digital phase discriminator 22, phase error accumulator 23 with 24 driver for addition and exclusion pulses, Peremnon Itel voltage 25 with STRIP1 filter 26 and limiter 27, frequency divider 28 on p, digital phase detector 29, frequency divider 30 and cell

"And 31 that make up the astatic frequency detuning compensation node 19, modulo two adder 32 and OR cell 5, cocTiULLY combining node 16, modulo two adder 34 and sign signal generator 35 that make up the digital frequency discriminator 13.

A phase demodulator with a frequency auto-tuning device operates as follows.

The input signal is a phase manth-sharpened oscillation with a frequency of

whereD / nmaps D / n, D / kmax -

the maximal deviation of the frequency from its nominal value; the great values are sent to frequency multiplier 1 by p. At the output of the multiplier / there is a non-mani-pulsed frequency signal p / n4-A / n, which is fed to the mixer 2 feedback loops, and its other input is received by the local oscillator with the frequency / op- | -A / op. At the output of the mixer, sigpal appears with a difference frequency

/ cm P / n- | -LL / n / onD / op.

The bandwidth of the filtering cascade 3 is set to 2 L / n Mai; c. The system of self-tuning contains two rings - frequency and phase.

The frequency control in the frequency locked loop is as follows.

The measuring input 13 of the digital discriminator 12 receives a signal in B: the ID of pulses with a frequency / cm, which are formed by limiting the oscillations from the output of the filtering stage 3 using a limiter. Pulses from the output 7 of the chroniser 4, which have a frequency / o equal to the average frequency of the setting of the filter 3, arrive at another input of the discriminator of the high J2. Thus, the number of pulses at the output 14 of the discriminator 13 is proportional to the module of the frequency difference:

/ cm / 0 / g / H- | -PA / 1/0 "fo.

The sign of each pulse at output 14 is determined with the help of a driver of 35 sign signals: if; a pulse at output 14 corresponds to a pulse at the output of limiter 11, then a positive sign is assigned to it, i.e., this pulse should increase the number in the frequency error accumulator, if "The pulse at output 14 (corresponds to the pulse at output 7 of chronizatar 4, then it is assigned a negative sign, i.e., this pulse should decrease the number of frequency errors in the accumulator.

If the frequency of the following pulses arriving at the inputs of the frequency discriminator is matched, the number of pulses with a positive and a negative signal at the output is the same. Compensation of the astatic frequency detuning is performed by changing the number of tn in the frequency error accumulator, which characterizes the difference between the measured frequencies. The change is made in such a way that if the number t recorded in the frequency error accumulator 17 is in the form of revertmax

sive counter, more magnitude

2

where / Pmax is the maximum number for which the counter is calculated, then the number t decreases,

/ 7 small with

then t increase.

if m less

is chosen in such a way that when

t

tmais

being in the drive number 17 - the frequency of the signal of the local oscillator at the input of the mixer 2 is. The indicated number measurement is carried out with the help of node 19 for compensating astatic detuning of the frequency, consisting of frequency divider 30, whose input receives pulses from output 5 of chroniser 4 and cell "And 31, to one input of which receives pulses from output of frequency divider 30, and on the other - the potential from the senior discharge of the reverse counter P.

Node 19 as compensation and digital frequency discriminator 12 has two outputs - pulse (output frequency divider 30) and sign (output cells). The IMSO output 1 through the adder 32 and module two, to the second input of which the pulse output 14 of the frequency discriminator 12 is connected, is connected to the counting input of the accumulator 17, and the sign output of the compensation node 19 through the OR cell 33, to the second input of which the sign output 15 of the frequency discriminator is connected 12 is connected to the sign input of the nozzle 17.

Thus, the number m in a reversible counter varies from the cumulative effect of the frequency mismatch signal received in the frequency discriminator and from the local signal recorded by the IB case-file 31.

The frequency of the pulses of the reference naryl: from the output of the controlled divider 5 depends on the number of addition and exclusion pulses that are formed in the former 18 by polling the number m taken from the accumulator 17 in a parallel form by polling pulses from the cells of the controlled divider 8. If there is no useful signal at the input of the phase demodulator, then using the node compensating for the static detuning of the frequency t in the accumulator / 7 takes the value n

reading The frequency of the output from the controlled splitter 8 is increased by converting with the help of multiplier 9, to one input of which a sitnal is fed from the controlling divider 8, and to the other input - to output 6 of the synchronizer 4. The frequency of the signal at the output of frequency multiplier 10 is / turns out to be higher than the frequency of the signal at

the output of the mixer 2 in g times.

In order for the additional correction frequency to be made by the compensation unit; astatic detuning does not increase the error of adjustment, the rate of change of the numbers. The frequency determined by the frequency of the pulses from the output of the frequency divider 30 must be less than the permissible error of the frequency adjustment, which is achieved by an appropriate choice of the division factor of the frequency divider 30.

Subject invention

A digital frequency-locked loop device, for example, for a coherent phase demodulator containing a loop mixer: feedback, the output of which is connected via a limiter to the input of a digital frequency discriminator, the output of the frequency error accumulator through an exclusion pulse driver is connected to the frequency divider control input , to the counting input of which the output of the chroniser is connected, and the output of the frequency divider is connected via a multiplier - voltages and a frequency multiplier to the heterodyne The feedback mixer is characterized in that, in order to improve the noise immunity of the frequency control, the output of the digital frequency d.Scrim, the interim is connected to the input of the frequency error accumulator via the additionally entered combiner node, to the second input of which the output of the high bit of the frequency accumulator is connected errors through the additionally introduced node for the compensation of the static detuning frequency, the polling input of which is associated with the output of the chron.izator.

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