CN111211758B - Feedback frequency sweeping type DDS design method suitable for surface acoustic wave sensor - Google Patents
Feedback frequency sweeping type DDS design method suitable for surface acoustic wave sensor Download PDFInfo
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Abstract
The invention discloses a feedback sweep frequency type DDS design method suitable for a surface acoustic wave sensor, which comprises the following steps: 1. setting frequency; 2. accumulating by a phase accumulator and a frequency register; 3. obtaining amplitude and phase information; 4. acquiring a first refreshing frequency interval; 5. acquiring a second refreshing frequency interval; 6. and acquiring a third refreshing frequency interval. The method has simple steps and reasonable design, adopts the FPGA microcontroller to generate the excitation signal for the SWA surface acoustic wave sensor, can generate a stable and reliable excitation signal through feedback regulation output, is based on the programmable performance of the FPGA, has low cost and avoids the construction of an analog circuit.
Description
Technical Field
The invention belongs to the technical field of excitation application of a surface acoustic wave sensor, and particularly relates to a feedback frequency sweeping type DDS design method suitable for the surface acoustic wave sensor.
Background
With the rapid development of electronic computer technology, the DDS signal generator is widely used in the fields of production, scientific research, electronic measurement and communication as a general electronic instrument capable of generating waveforms of different frequencies and shapes. However, such instruments available in the market have not been able to meet the actual requirements in terms of bandwidth, precision, waveform type, etc.
At present, most of signal generators commonly used in production and scientific research are composed of analog circuits, but the signal generators do not meet the requirements of the power industry on signal sources due to the defects of large volume, difficulty in modulation, high cost and the like. And as a novel high-performance Programmable technology, the FPGA (Field-Programmable Gate Array) microcontroller can reconfigure the internal logic resource module thereof through a hardware description language and a special design tool, thereby fundamentally solving the defects of the analog circuit. The surface acoustic wave sensor has the characteristics of small volume, high reliability and the like, and is suitable for underground monitoring of gas concentration. The sensor based on the surface acoustic wave technology can be suitable for the wireless passive sensing technology, and can be excited to start working and feed back the radio frequency signal containing sensing information by emitting effective radio frequency signals to the sensor. The FPGA transmits excitation signals to the surface acoustic wave sensor, so that the problems of inflexibility of fixed-point frequency sweeping, inaccurate excitation signal application and the like in the existing DDS design are solved, and the practical application significance of the DDS is greatly enhanced.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a feedback sweep frequency type DDS design method suitable for the surface acoustic wave sensor aiming at the defects in the prior art, the method has simple steps and reasonable design, an FPGA microcontroller is adopted to generate an excitation signal for the SWA surface acoustic wave sensor, the stable and reliable excitation signal can be generated through feedback regulation output, and in addition, the method is based on the programmable performance of the FPGA, the cost is low, the establishment of an analog circuit is avoided, and the practicability is high.
In order to solve the technical problems, the invention adopts the technical scheme that: a feedback frequency sweeping type DDS design method suitable for a surface acoustic wave sensor is characterized by comprising the following steps:
step one, frequency setting:
step 101, setting the lower limit of an initial frequency interval to be DFord =5.0MHz by adopting an FPGA microcontroller, and setting the upper limit of the initial frequency interval to be UFord =15.0MHz;
step 102, setting an initial frequency to be 5MHz by adopting an FPGA microcontroller, and obtaining a frequency control word to be stored in a frequency register;
103, connecting the FPGA microcontroller with a surface acoustic wave sensor;
step two, accumulating the phase accumulator and the frequency register:
in the ith clock signal, the accumulated data of the phase accumulator and the frequency register is obtained, and the specific process is as follows:
step 201, an FPGA microcontroller is adopted to carry out first addition on the 0 th to 7 th bits of clock frequency in a phase accumulator and the 0 th to 7 th bits of a frequency control word in a frequency register, and data after the first addition is stored in a register first1; when the data after the first addition has a carry, the carry flag bit CF of the flag register is set to 1, and when the data after the first addition has no carry, the carry flag bit CF of the flag register is set to 0;
step 202, performing second addition on the 8 th to 15 th bits of the clock frequency in the phase accumulator and the 8 th to 15 th bits of the frequency control word in the frequency register by adopting an FPGA microcontroller to obtain data after the second addition; when the data after the second addition has a carry, the carry flag bit CF of the flag register is set to 1, and when the data after the second addition has no carry, the carry flag bit CF of the flag register is set to 0;
performing secondary bit splicing on the data subjected to the secondary addition and the data subjected to the primary addition in the register first1 to obtain data subjected to the primary bit splicing, and storing the data subjected to the primary bit splicing in the register first 2; when the data after the first addition in step 201 has a carry, adding a carry flag bit obtained from the data after the first addition to the last bit of the data after the second addition;
step 203, adding the 16 th to 23 th bits of the clock frequency in the phase accumulator and the 16 th to 23 th bits of the frequency control word in the frequency register for the third time by adopting the FPGA microcontroller to obtain data after the third addition; when the data after the third addition has a carry, the carry flag bit CF of the flag register is set to 1, and when the data after the third addition does not have a carry, the carry flag bit CF of the flag register is set to 0;
performing secondary bit splicing on the data subjected to the third addition and the data subjected to the first bit splicing in the register first2 to obtain data subjected to the second bit splicing, and storing the data subjected to the second bit splicing in the register first 3; when the data after the second addition in step 202 has a carry, adding a carry flag bit obtained from the data after the second addition to the last bit of the data after the third addition;
step 204, performing fourth addition on the 24 th to 31 th bits of the clock frequency in the phase accumulator and the 24 th to 31 th bits of the frequency control word in the frequency register by using the FPGA microcontroller to obtain fourth added data; when the data after the fourth addition has a carry, the carry flag bit CF of the flag register is set to 1, and when the data after the fourth addition does not have a carry, the carry flag bit CF of the flag register is set to 0;
performing secondary bit splicing on the data subjected to the fourth time of addition and the data subjected to the second time of bit splicing in the register first3 to obtain data subjected to the third time of bit splicing; the data after the third time of bit splicing comprises fourth time of added data, third time of added data, second time of added data and first time of added data which are sequentially distributed from high bits to low bits; when the data after the third addition in step 203 has a carry, adding a carry flag bit obtained by the data after the third addition and the last bit of the data after the fourth addition;
step 205, assigning the data subjected to the third time of bit splicing to a phase accumulator by adopting an FPGA microcontroller; the data after the third time of bit splicing is recorded as accumulated data of a phase accumulator and a frequency register in the ith clock frequency, and i is a positive integer;
step three, obtaining amplitude and phase information:
in the ith clock signal, amplitude and phase information is acquired, and the specific process is as follows:
step 301, storing amplitude data and phase data in a ROM by adopting an FPGA microcontroller;
step 302, an FPGA microcontroller is adopted to intercept the data after the third time of bit splicing to obtain high 14-bit data, and the amplitude and the phase of an output excitation signal are obtained according to the high 14-bit data;
step four, obtaining a first refreshing frequency interval:
step 401, repeating the step two and the step three for multiple times until the set excitation time is reached, and finishing the first round of frequency sweeping excitationExciting, performing the next round of sweep frequency excitation until the frequency of the last round of sweep frequency excitation reaches the upper limit of the initial frequency interval; wherein, the frequency of the first j round of frequency sweep excitation is f j And f is j -f j-1 ＝2.5MHz，f j-1 Representing the frequency of the j-1 th round of sweep excitation, wherein j is a positive integer and is more than or equal to 2 and less than or equal to 5;
step 402, in the process of the first round of frequency sweep excitation, the jth round of frequency sweep excitation and the 5 th round of frequency sweep excitation, when a signal fed back by the SAW acoustic surface device is effective, the frequency corresponding to the SAW acoustic surface device when the effective signal is fed back by the FPGA microcontroller is recorded as a lower limit value f of a first refresh frequency c1,d And a first refresh frequency upper limit value f c1,u ；
Step five, acquiring a second refreshing frequency interval:
step 501, setting the lower limit of a secondary frequency interval to be f by adopting an FPGA microcontroller c1,d The upper limit of the secondary frequency interval is f c1,u ；
Step 502, setting a secondary frequency initial value f by adopting an FPGA microcontroller 1 Is' f c1,d And obtaining a frequency control word and storing the frequency control word into a frequency register; wherein, the secondary frequency initial value f 1 ' is the frequency of the second first round sweep excitation;
step 503, according to the method described in the second to fifth steps, when the set excitation time is reached, completing the second first round of frequency sweep excitation, performing the second next round of frequency sweep excitation until the frequency of the second last round of frequency sweep excitation reaches the upper limit of the second frequency interval, and obtaining the second refresh frequency lower limit value f c2,d And a second refresh frequency upper limit value f c2,u (ii) a Wherein the frequency of the secondary j 'th wheel sweep frequency excitation is f' j And f' j -f′ j-1 ＝0.625MHz，f′ j-1 Representing the frequency of the second j ' -1 round of sweep excitation, wherein j ' is a positive integer, and j ' is more than or equal to 2 and less than or equal to 5;
step six, acquiring a third refreshing frequency interval:
601, setting the lower limit of the cubic frequency interval to be f by adopting an FPGA microcontroller c2,d The upper limit of the cubic frequency interval is f c2,u ；
Step 602, setting a triple frequency initial value f by adopting an FPGA microcontroller 1 Is "at c2,d And obtaining a frequency control word and storing the frequency control word into a frequency register; wherein, the initial value f of the cubic frequency 1 "is the frequency of the third first round sweep excitation;
603, according to the method in the second to fifth steps, completing the first frequency sweep excitation for three times when the set excitation time is reached, performing the next frequency sweep excitation for three times until the frequency of the last frequency sweep excitation for three times reaches the upper limit of the frequency interval for three times, and acquiring the lower limit value f of the refresh frequency for the third time c3,d And a third refresh frequency upper limit value f c3,u (ii) a Wherein, the frequency of the third j' round sweep excitation is f j And f ″) j -f″ j-1 ＝0.15625MHz，f″ j-1 Representing the frequency of the j "-1 th frequency sweep excitation, wherein j" is a positive integer and is more than or equal to 2 and less than or equal to 5;
step 604, adopting the FPGA microcontroller to refresh the lower limit value f of the frequency for the third time c3,d And a third refresh frequency upper limit value f c3,u Note that the excitation frequency range of the surface acoustic wave sensor is described.
The feedback frequency sweeping type DDS design method suitable for the surface acoustic wave sensor is characterized by comprising the following steps: the set excitation time is 200ms;
the amplitude data and the phase data stored in the ROM memory in step 301 correspond one-to-one, and the i' th phase data among the plurality of phase data is denoted as θ in the order from 0 ° to 90 ° i′ The amplitude data corresponding to the i' th phase data is denoted as A i′ And is and
θ i′+1 denotes the i' +1 th phase data, θ i′ And theta i′+1 The average value range of (1) is 0-90 degrees, i 'is a positive integer, i' is more than or equal to 1 and less than or equal to m, and m is the total number of phase data or amplitude data.
The feedback frequency sweeping type DDS design method suitable for the surface acoustic wave sensor is characterized by comprising the following steps: when the phase data in the ROM memory is equal to 90 degrees, the amplitude data is the maximum amplitude, and the value range of the maximum amplitude is 100 mA-110 mA.
The feedback frequency sweeping type DDS design method suitable for the surface acoustic wave sensor is characterized by comprising the following steps: in step 302, the amplitude and phase of the output excitation signal are obtained according to the high 14-bit data, and the specific process is as follows:
when the 14 th bit and the 13 th bit in the high 14-bit data are 0 and 0, the 0 th bit to the 12 th bit in the high 14-bit data are used as phase addresses, the amplitude corresponding to the phase addresses is the amplitude of the output excitation signal, and the phase corresponding to the phase addresses is the phase of the output excitation signal;
when the 14 th bit in the high 14-bit data is 0 and the 13 th bit in the high 14-bit data is 1, inverting the 0 th bit to the 12 th bit in the high 14-bit data to be phase addresses, wherein the amplitude corresponding to the phase addresses is the amplitude of the output excitation signal, and the phase corresponding to the phase addresses plus 90 degrees is the phase of the output excitation signal;
when the 14 th bit in the high 14-bit data is 1 and the 13 th bit in the high 14-bit data is 0, the 0 th bit to the 12 th bit in the high 14-bit data are obtained as phase addresses, the amplitude corresponding to the phase addresses takes a negative value as the amplitude of the output excitation signal, and the phase corresponding to the phase addresses plus 180 degrees is the phase of the output excitation signal;
when the 14 th bit in the high 14-bit data is 1 and the 13 th bit in the high 14-bit data is 1, inverting the data from the 0 th bit to the 12 th bit in the high 14-bit data to obtain a phase address, the amplitude corresponding to the phase address takes a negative value as the amplitude of the output excitation signal, and the phase corresponding to the phase address plus 270 ° is the phase of the output excitation signal.
The feedback frequency sweeping type DDS design method suitable for the surface acoustic wave sensor is characterized by comprising the following steps: when the signal fed back by the SAW device is valid in step 402, the specific process is as follows:
step 4021, connecting the FPGA microcontroller with an oscilloscope through an RS232 serial port or an RS485 serial port;
step 4022, the FPGA microcontroller sends the received signals fed back by the SAW surface acoustic device to an oscilloscope;
and step 4023, observing that the maximum amplitude of the signal fed back by the SAW surface acoustic device is between 80 and 100mA through an oscilloscope, and indicating that the signal fed back by the SAW surface acoustic device is an effective signal.
Compared with the prior art, the invention has the following advantages:
1. the invention is realized by FPGA, has low hardware requirement and is convenient for subsequent development and use.
2. The invention is flexible and convenient, can adjust the lower limit of different initial frequency intervals and the upper limit of the initial frequency interval through the FPGA, and adjust the first refreshing frequency interval, the second refreshing frequency interval and the third refreshing frequency interval, and is suitable for different SWA surface acoustic wave sensor applying frequencies.
3. The DDS signal design method is realized through the FPGA, the whole calculation period of the DDS signal design can be shortened, and the consumption of hardware resources is effectively reduced.
4. The data of the phase accumulator and the frequency register are processed by four stages to obtain the data after the third time of bit splicing and are assigned to the phase accumulator, so that the self-adaptive capacity of the FPGA is improved, and the method is closer to engineering application.
5. The adopted feedback frequency sweeping type DDS design method suitable for the surface acoustic wave sensor is simple in steps, convenient to implement and simple and convenient to operate, stable and reliable excitation signals can be generated through feedback regulation output, and the method is also suitable for stable excitation of other surface acoustic wave sensors on the basis of the programmable performance of the FPGA.
6. The adopted feedback frequency sweeping type DDS design method suitable for the surface acoustic wave sensor is simple and convenient to operate and good in using effect, the lower limit and the upper limit of an initial frequency interval are set firstly, then the phase accumulator and the frequency register are accumulated, amplitude and phase information corresponding to accumulated data of the phase accumulator and the frequency register are obtained and serve as the amplitude and the phase of an output excitation signal, a first refreshing frequency interval, a second refreshing frequency interval and a third refreshing frequency interval are obtained through multiple frequency sweeping between the lower limit and the upper limit of the initial frequency interval until the excitation frequency interval of the surface acoustic wave sensor is obtained, and the accuracy of the excitation signal of the surface acoustic wave sensor is improved.
7. According to the invention, the excitation frequency interval is reduced step by step through the first refreshing frequency interval, the second refreshing frequency interval and the third refreshing frequency interval, so that the accuracy of applying an excitation signal to the SAW surface acoustic wave device by the FPGA controller is improved, and the precision required by DDS design is improved.
8. According to the method, in the process of obtaining the first refreshing frequency interval, the second refreshing frequency interval and the third refreshing frequency interval, the frequency difference of the frequency sweeping excitation of two adjacent rounds is gradually reduced, so that the method is effectively suitable for different refreshing frequency intervals on one hand, and the accuracy of the refreshing frequency interval is improved on the other hand.
In conclusion, the method has the advantages of simple steps and reasonable design, the FPGA microcontroller is adopted to generate the excitation signal for the surface acoustic wave sensor, the stable and reliable excitation signal can be generated through feedback regulation output, in addition, the cost is low based on the programmable performance of the FPGA, the building of an analog circuit is avoided, and the practicability is high.
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Drawings
Fig. 1 is a flow chart of a feedback swept frequency DDS design method adapted to a surface acoustic wave sensor in accordance with the present invention.
Fig. 2 is a schematic structural view of the saw sensor of the present invention.
1-a piezoelectric thin film layer; 2-an input interdigital transducer; 3-an output interdigital transducer;
4-a sensitive film layer; and 5, sound absorption glue.
Detailed Description
As shown in fig. 1, a method for designing a feedback swept-frequency DDS suitable for a surface acoustic wave sensor includes the following steps:
step one, frequency setting:
step 101, setting the lower limit of an initial frequency interval to be DFord =5.0MHz by adopting an FPGA microcontroller, and setting the upper limit of the initial frequency interval to be UFord =15.0MHz;
step 102, setting an initial frequency to be 5MHz by adopting an FPGA microcontroller, and obtaining a frequency control word to be stored in a frequency register;
103, connecting the FPGA microcontroller with a surface acoustic wave sensor;
step two, accumulating the phase accumulator and the frequency register:
in the ith clock signal, the accumulated data of the phase accumulator and the frequency register is obtained, and the specific process is as follows:
step 201, an FPGA microcontroller is adopted to carry out first addition on the 0 th to 7 th bits of clock frequency in a phase accumulator and the 0 th to 7 th bits of a frequency control word in a frequency register, and data after the first addition is stored in a register first1; when the data after the first addition has a carry, the carry flag bit CF of the flag register is set to 1, and when the data after the first addition has no carry, the carry flag bit CF of the flag register is set to 0;
step 202, performing second addition on the 8 th to 15 th bits of the clock frequency in the phase accumulator and the 8 th to 15 th bits of the frequency control word in the frequency register by adopting an FPGA microcontroller to obtain data after the second addition; when the data after the second addition has a carry, the carry flag bit CF of the flag register is set to 1, and when the data after the second addition has no carry, the carry flag bit CF of the flag register is set to 0;
performing secondary bit splicing on the data subjected to the secondary addition and the data subjected to the primary addition in the register firs t1 to obtain data subjected to the primary bit splicing, and storing the data subjected to the primary bit splicing in a register firs t 2; when the data after the first addition in step 201 has a carry, adding a carry flag bit obtained from the data after the first addition to the last bit of the data after the second addition;
step 203, adding the 16 th to 23 th bits of the clock frequency in the phase accumulator and the 16 th to 23 th bits of the frequency control word in the frequency register for the third time by adopting the FPGA microcontroller to obtain data after the third addition; when the data after the third addition has a carry, the carry flag bit CF of the flag register is set to 1, and when the data after the third addition does not have a carry, the carry flag bit CF of the flag register is set to 0;
performing secondary bit splicing on the data subjected to the third time of addition and the data subjected to the first time of bit splicing in the register firs t2 to obtain data subjected to the second time of bit splicing, and storing the data subjected to the second time of bit splicing in a register firs t 3; when the data after the second addition in step 202 has a carry, adding a carry flag bit obtained from the data after the second addition to the last bit of the data after the third addition;
step 204, performing fourth addition on the 24 th to 31 th bits of the clock frequency in the phase accumulator and the 24 th to 31 th bits of the frequency control word in the frequency register by using the FPGA microcontroller to obtain fourth added data; when the data after the fourth addition has a carry, the carry flag bit CF of the flag register is set to 1, and when the data after the fourth addition does not have a carry, the carry flag bit CF of the flag register is set to 0;
performing secondary bit splicing on the fourth-time added data and the second-time bit spliced data in the register firs t3 to obtain third-time bit spliced data; the data after the third time of bit splicing comprises fourth time of added data, third time of added data, second time of added data and first time of added data which are sequentially distributed from high bits to low bits; when the data after the third addition in step 203 has a carry, adding a carry flag bit obtained by the data after the third addition and the last bit of the data after the fourth addition;
step 205, assigning the data subjected to the third time of bit splicing to a phase accumulator by adopting an FPGA microcontroller; the data after the third time of bit splicing is recorded as accumulated data of a phase accumulator and a frequency register in the ith clock frequency, wherein i is a positive integer;
step three, obtaining amplitude and phase information:
in the ith clock signal, amplitude and phase information is acquired, and the specific process is as follows:
301, storing amplitude data and phase data in a ROM by adopting an FPGA microcontroller;
step 302, an FPGA microcontroller is adopted to intercept the data after the third time of bit splicing to obtain high 14-bit data, and the amplitude and the phase of an output excitation signal are obtained according to the high 14-bit data;
step four, obtaining a first refreshing frequency interval:
step 401, repeating the step two and the step three for multiple times until the set excitation time is reached, completing a first round of frequency sweep excitation, and performing a next round of frequency sweep excitation until the frequency of the last round of frequency sweep excitation reaches the upper limit of the initial frequency interval; wherein, the frequency of the first j-th round of sweep excitation is f j And f is j -f j-1 ＝2.5MHz，f j-1 Representing the frequency of the j-1 th round of sweep excitation, wherein j is a positive integer and is more than or equal to 2 and less than or equal to 5;
step 402, in the process of the first round of frequency sweep excitation, the jth round of frequency sweep excitation and the 5 th round of frequency sweep excitation, when a signal fed back by the SAW acoustic surface device is effective, the frequency corresponding to the SAW acoustic surface device when the effective signal is fed back by the FPGA microcontroller is recorded as a lower limit value f of a first refresh frequency c1,d And a first refresh frequency upper limit value f c1,u ；
Step five, acquiring a second refreshing frequency interval:
step 501, setting the lower limit of a secondary frequency interval to be f by adopting an FPGA microcontroller c1,d The upper limit of the secondary frequency interval is f c1,u ；
Step 502, setting a secondary frequency initial value f by adopting an FPGA microcontroller 1 Is' f c1,d And obtaining a frequency control word and storing the frequency control word into a frequency register; wherein, the secondary frequency initial value f 1 ' is the frequency of the second first round sweep excitation;
step 503, according to the method described in the second to fifth steps, when the set excitation time is reached, completing the first frequency sweep excitation for two times, performing the next frequency sweep excitation for two times until the frequency of the last frequency sweep excitation for two times reaches the upper limit of the second frequency interval, and obtaining the lower limit f of the second refresh frequency c2,d And a second refresh frequency upper limit value f c2,u (ii) a Wherein the frequency of the secondary j 'th wheel sweep frequency excitation is f' j And f' j -f′ j-1 ＝0.625MHz，f j ′ -1 Representing the frequency of the second j ' -1 round of sweep excitation, wherein j ' is a positive integer, and j ' is more than or equal to 2 and less than or equal to 5;
step six, acquiring a third refreshing frequency interval:
601, setting the lower limit of the cubic frequency interval to be f by adopting an FPGA microcontroller c2,d The upper limit of the cubic frequency interval is f c2,u ；
Step 602, setting a cubic frequency initial value f by using an FPGA microcontroller 1 Is "at c2,d And obtaining a frequency control word and storing the frequency control word into a frequency register; wherein, the third frequency is the initial value f 1 "is the frequency of the third first round sweep excitation;
603, according to the method in the second to fifth steps, completing the first frequency sweep excitation for three times when the set excitation time is reached, performing the next frequency sweep excitation for three times until the frequency of the last frequency sweep excitation for three times reaches the upper limit of the frequency interval for three times, and acquiring the lower limit value f of the refresh frequency for the third time c3,d And a third refresh frequency upper limit value f c3,u (ii) a Wherein, the frequency of the third j' round sweep excitation is f j And f ″) j -f″ j-1 ＝0.15625MHz，f″ j-1 Representing the frequency of the j "-1 th frequency sweep excitation, wherein j" is a positive integer and is more than or equal to 2 and less than or equal to 5;
step 604, adopting the FPGA microcontroller to refresh the lower limit value f of the frequency for the third time c3,d And a third refresh frequency upper limit value f c3,u Note that the excitation frequency range of the surface acoustic wave sensor is described.
In this embodiment, the set excitation time is 200ms;
the amplitude data and the phase data stored in the ROM memory in step 301 correspond one-to-one, and the i' th phase data among the plurality of phase data is recorded as θ in the order from 0 ° to 90 ° i′ The amplitude data corresponding to the i' th phase data is denoted as A i′ And is and
θ i′+1 denotes the i' +1 th phase data, θ i′ And theta i′+1 The average value range of (1) is 0-90 degrees, i 'is a positive integer, i' is more than or equal to 1 and less than or equal to m, and m is the total number of phase data or amplitude data.
In this embodiment, when the phase data in the ROM memory is equal to 90 °, the amplitude data is the maximum amplitude, and the value range of the maximum amplitude is 100mA to 110mA.
In this embodiment, in step 302, the amplitude and the phase of the output excitation signal are obtained according to the high 14-bit data, and the specific process is as follows:
when the 14 th bit in the high 14-bit data is 0 and the 13 th bit is 0, the 0 th bit to the 12 th bit in the high 14-bit data is used as a phase address, the amplitude corresponding to the phase address is the amplitude of the output excitation signal, and the phase corresponding to the phase address is the phase of the output excitation signal;
when the 14 th bit in the high 14-bit data is 0 and the 13 th bit in the high 14-bit data is 1, inverting the 0 th bit to the 12 th bit in the high 14-bit data to be phase addresses, wherein the amplitude corresponding to the phase addresses is the amplitude of the output excitation signal, and the phase corresponding to the phase addresses plus 90 degrees is the phase of the output excitation signal;
when the 14 th bit in the high 14-bit data is 1 and the 13 th bit in the high 14-bit data is 0, the 0 th bit to the 12 th bit in the high 14-bit data are obtained as phase addresses, the amplitude corresponding to the phase addresses takes a negative value as the amplitude of the output excitation signal, and the phase corresponding to the phase addresses plus 180 degrees is the phase of the output excitation signal;
when the 14 th bit in the high 14-bit data is 1 and the 13 th bit in the high 14-bit data is 1, inverting the data from the 0 th bit to the 12 th bit in the high 14-bit data to obtain a phase address, the amplitude corresponding to the phase address takes a negative value as the amplitude of the output excitation signal, and the phase corresponding to the phase address plus 270 ° is the phase of the output excitation signal.
In this embodiment, when the signal fed back by the SAW surface acoustic device is valid in step 402, the specific process is as follows:
step 4021, connecting the FPGA microcontroller with an oscilloscope through an RS232 serial port or an RS485 serial port;
step 4022, the FPGA microcontroller sends the received signals fed back by the SAW surface acoustic device to an oscilloscope;
and step 4023, observing that the maximum amplitude of the signal fed back by the SAW surface acoustic device is between 80 and 100mA through an oscilloscope, and indicating that the signal fed back by the SAW surface acoustic device is an effective signal.
As shown in fig. 2, in this embodiment, the saw sensor is fabricated as follows: selecting a piezoelectric film layer 1, arranging an input interdigital transducer 2 and an output interdigital transducer 3 on the piezoelectric film layer 1, arranging a sensitive film layer 4 between the input interdigital transducer 2 and the output interdigital transducer 3, and attaching the bottom surface of the sensitive film layer 4 to the surface of the piezoelectric film layer 1; the structure of the input interdigital transducer 2 is the same as that of the output interdigital transducer 3, the input interdigital transducer 2 and the output interdigital transducer 3 are symmetrically distributed about the center of the piezoelectric film layer 1, and sound absorption glue 5 is coated at two ends of the piezoelectric film layer 1.
In this embodiment, in the actual connection process, the other pin of the input interdigital transducer 2 is grounded, the other pin of the output interdigital transducer 3 is grounded, and one pin of the input interdigital transducer 2 and one pin of the output interdigital transducer 3 are connected to an I/O pin of the FPGA microcontroller.
In the embodiment, in the step 101, the sound absorption glue 5 is an epoxy resin glue, the thickness of the sound absorption glue 5 is 0.1mm to 0.8mm, and the thickness of the piezoelectric film layer 1 is 0.5 μm to 0.8 μm;
in the step 101, the sensitive thin film layer 4 is a tin dioxide thin film layer, the thickness of the sensitive thin film layer 4 is 100 nm-12 nm, gaps are formed between the distance between the two sides of the sensitive thin film layer 4 and the distance between the input interdigital transducer 2 and the output interdigital transducer 3, and the piezoelectric thin film layer 1 is quartz.
According to the method, in the process of obtaining the first refreshing frequency interval, the second refreshing frequency interval and the third refreshing frequency interval, the frequency difference of the frequency sweeping excitation of two adjacent rounds is gradually reduced, so that the method is effectively suitable for different refreshing frequency intervals on one hand, and the accuracy of the refreshing frequency interval is improved on the other hand.
In conclusion, the method has simple steps and reasonable design, adopts the FPGA microcontroller to generate the excitation signal for the surface acoustic wave sensor, can generate a stable and reliable excitation signal through feedback regulation output, is also suitable for stable excitation of other surface acoustic wave sensors during actual use based on the programmable performance of the FPGA, has low cost, avoids the establishment of an analog circuit, and has strong practicability.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and all simple modifications, changes and equivalent structural changes made to the above embodiment according to the technical spirit of the present invention still fall within the protection scope of the technical solution of the present invention.
Claims (5)
1. A feedback frequency sweeping type DDS design method suitable for a surface acoustic wave sensor is characterized by comprising the following steps:
step one, frequency setting:
step 101, setting the lower limit of an initial frequency interval to be DFord =5.0MHz by adopting an FPGA microcontroller, and setting the upper limit of the initial frequency interval to be UFord =15.0MHz;
step 102, setting an initial frequency to be 5MHz by adopting an FPGA microcontroller, and storing a frequency control word into a frequency register;
103, connecting the FPGA microcontroller with a surface acoustic wave sensor;
step two, accumulating the phase accumulator and the frequency register:
in the ith clock signal, the accumulated data of the phase accumulator and the frequency register is obtained, and the specific process is as follows:
step 201, an FPGA microcontroller is adopted to carry out first addition on the 0 th to 7 th bits of clock frequency in a phase accumulator and the 0 th to 7 th bits of a frequency control word in a frequency register, and data after the first addition is stored in a register first1; when the data after the first addition has a carry, the carry flag bit CF of the flag register is set to 1, and when the data after the first addition has no carry, the carry flag bit CF of the flag register is set to 0;
step 202, performing second addition on the 8 th to 15 th bits of the clock frequency in the phase accumulator and the 8 th to 15 th bits of the frequency control word in the frequency register by adopting an FPGA microcontroller to obtain data after the second addition; when the data after the second addition has a carry, the carry flag bit CF of the flag register is set to 1, and when the data after the second addition has no carry, the carry flag bit CF of the flag register is set to 0;
performing secondary bit splicing on the data subjected to the secondary addition and the data subjected to the primary addition in the register first1 to obtain data subjected to the primary bit splicing, and storing the data subjected to the primary bit splicing in the register first 2; when the data after the first addition in step 201 has a carry, adding a carry flag bit obtained from the data after the first addition to the last bit of the data after the second addition;
step 203, adding the 16 th to 23 th bits of the clock frequency in the phase accumulator and the 16 th to 23 th bits of the frequency control word in the frequency register for the third time by adopting the FPGA microcontroller to obtain data after the third addition; when the data after the third addition has a carry, the carry flag bit CF of the flag register is set to 1, and when the data after the third addition does not have a carry, the carry flag bit CF of the flag register is set to 0;
performing secondary bit splicing on the data subjected to the third addition and the data subjected to the first bit splicing in the register first2 to obtain data subjected to the second bit splicing, and storing the data subjected to the second bit splicing in the register first 3; when the data after the second addition in step 202 has a carry, adding a carry flag bit obtained from the data after the second addition to the last bit of the data after the third addition;
step 204, performing fourth addition on the 24 th to 31 th bits of the clock frequency in the phase accumulator and the 24 th to 31 th bits of the frequency control word in the frequency register by using the FPGA microcontroller to obtain fourth added data; when the data after the fourth addition has a carry, the carry flag bit CF of the flag register is set to 1, and when the data after the fourth addition does not have a carry, the carry flag bit CF of the flag register is set to 0;
performing secondary bit splicing on the data subjected to the fourth addition and the data subjected to the secondary bit splicing in the register first3 to obtain data subjected to the third bit splicing; the data after the third time of bit splicing comprises fourth time of added data, third time of added data, second time of added data and first time of added data which are sequentially distributed from high bits to low bits; when the data after the third addition in step 203 has a carry, adding a carry flag bit obtained by the data after the third addition and the last bit of the data after the fourth addition;
step 205, assigning the data subjected to third time bit splicing to a phase accumulator by adopting an FPGA microcontroller; the data after the third time of bit splicing is recorded as accumulated data of a phase accumulator and a frequency register in the ith clock frequency, wherein i is a positive integer;
step three, obtaining amplitude and phase information:
in the ith clock signal, amplitude and phase information is obtained, and the specific process is as follows:
301, storing amplitude data and phase data in a ROM by adopting an FPGA microcontroller;
step 302, an FPGA microcontroller is adopted to intercept the data after the third time of bit splicing to obtain high 14-bit data, and the amplitude and the phase of an output excitation signal are obtained according to the high 14-bit data;
step four, obtaining a first refreshing frequency interval:
step 401, repeating the step two and the step three for multiple times until the set excitation time is reached, completing a first round of frequency sweep excitation, and performing next round of frequency sweep excitation until the frequency of the last round of frequency sweep excitation reaches the upper limit of the initial frequency interval; wherein, the frequency of the first j-th round of sweep excitation is f j And f is j -f j-1 ＝2.5MHz，f j-1 Representing the frequency of the j-1 th round of sweep excitation, wherein j is a positive integer and is more than or equal to 2 and less than or equal to 5;
step 402, in the first round of frequency sweep excitation, the jth round of frequency sweep excitation, and the 5 th round of frequency sweep excitation, when a signal fed back by the SAW acoustic surface device is effective, the FPGA is micro-scaleThe controller records the frequency corresponding to the effective signal fed back by the SAW acoustic surface device as the lower limit value f of the first refreshing frequency c1,d And a first refresh frequency upper limit value f c1,u ；
Step five, acquiring a second refreshing frequency interval:
step 501, setting the lower limit of a secondary frequency interval to be f by adopting an FPGA microcontroller c1,d The upper limit of the secondary frequency interval is f c1,u ；
Step 502, setting a secondary frequency initial value f by adopting an FPGA microcontroller 1 Is' f c1,d And obtaining a frequency control word and storing the frequency control word into a frequency register; wherein, the secondary frequency initial value f 1 ' is the frequency of the second first round sweep excitation;
step 503, according to the method described in the second to fifth steps, when the set excitation time is reached, completing the first frequency sweep excitation for two times, performing the next frequency sweep excitation for two times until the frequency of the last frequency sweep excitation for two times reaches the upper limit of the second frequency interval, and obtaining the lower limit f of the second refresh frequency c2,d And a second refresh frequency upper limit value f c2,u (ii) a Wherein the frequency of the secondary j 'th wheel sweep frequency excitation is f' j And f' j -f′ j-1 ＝0.625MHz，f′ j-1 Representing the frequency of the second j '-1 th round of sweep excitation, wherein j' is a positive integer and is more than or equal to 2 and less than or equal to 5;
step six, acquiring a third refreshing frequency interval:
601, setting the lower limit of the cubic frequency interval to be f by adopting an FPGA microcontroller c2,d The upper limit of the cubic frequency interval is f c2,u ；
Step 602, setting a cubic frequency initial value f by using an FPGA microcontroller 1 Is "at c2,d And obtaining a frequency control word and storing the frequency control word into a frequency register; wherein, the third frequency is the initial value f 1 "is the frequency of the third first round sweep excitation;
603, according to the method in the second to fifth steps, finishing the first frequency sweep excitation for three times until the set excitation time is reached, and carrying out the next frequency sweep excitation for three times until the set excitation time is reachedThe frequency of the last frequency sweep excitation of the three times reaches the upper limit of the frequency interval of the three times, and the lower limit value f of the third refresh frequency is obtained c3,d And a third refresh frequency upper limit value f c3,u (ii) a Wherein, the frequency of the tertiary j' round sweep excitation is f ″) j And f ″) j -f″ j-1 ＝0.15625MHz，f″ j-1 Representing the frequency of the j "-1 th frequency sweep excitation, wherein j" is a positive integer and is more than or equal to 2 and less than or equal to 5;
step 604, adopting the FPGA microcontroller to refresh the lower limit value f of the frequency for the third time c3,d And a third refresh frequency upper limit value f c3,u Note that the excitation frequency range of the surface acoustic wave sensor is described.
2. The design method of the feedback swept frequency type DDS adapted to a surface acoustic wave sensor according to claim 1, wherein the design method comprises the following steps: the set excitation time is 200ms;
the amplitude data and the phase data stored in the ROM memory in step 301 correspond one-to-one, and the i' th phase data among the plurality of phase data is denoted as θ in the order from 0 ° to 90 ° i′ The amplitude data corresponding to the i' th phase data is denoted as A i′ And is and
θ i′+1 denotes the i' +1 th phase data, θ i′ And theta i′+1 The average value range of (1) is 0-90 degrees, i 'is a positive integer, i' is more than or equal to 1 and less than or equal to m, and m is the total number of phase data or amplitude data.
3. The design method of the feedback swept frequency type DDS adapted to a surface acoustic wave sensor according to claim 1, wherein the design method comprises the following steps: when the phase data in the ROM memory is equal to 90 degrees, the amplitude data is the maximum amplitude, and the value range of the maximum amplitude is 100 mA-110 mA.
4. The design method of the feedback swept frequency type DDS adapted to a surface acoustic wave sensor according to claim 1, wherein the design method comprises the following steps: in step 302, the amplitude and phase of the output excitation signal are obtained according to the high 14-bit data, and the specific process is as follows:
when the 14 th bit in the high 14-bit data is 0 and the 13 th bit is 0, the 0 th bit to the 12 th bit in the high 14-bit data is used as a phase address, the amplitude corresponding to the phase address is the amplitude of the output excitation signal, and the phase corresponding to the phase address is the phase of the output excitation signal;
when the 14 th bit in the high 14-bit data is 0 and the 13 th bit in the high 14-bit data is 1, inverting the 0 th bit to the 12 th bit in the high 14-bit data to be phase addresses, wherein the amplitude corresponding to the phase addresses is the amplitude of the output excitation signal, and the phase corresponding to the phase addresses plus 90 degrees is the phase of the output excitation signal;
when the 14 th bit in the high 14-bit data is 1 and the 13 th bit in the high 14-bit data is 0, the 0 th bit to the 12 th bit in the high 14-bit data are obtained as phase addresses, the amplitude corresponding to the phase addresses takes a negative value as the amplitude of the output excitation signal, and the phase corresponding to the phase addresses plus 180 degrees is the phase of the output excitation signal;
when the 14 th bit of the high 14-bit data is 1 and the 13 th bit is 1, the data from the 0 th bit to the 12 th bit of the high 14-bit data is inverted into a phase address, the amplitude corresponding to the phase address takes a negative value as the amplitude of the output excitation signal, and the phase corresponding to the phase address plus 270 ° is the phase of the output excitation signal.
5. The design method of the feedback swept frequency type DDS adapted to a surface acoustic wave sensor according to claim 1, wherein the design method comprises the following steps: when the signal fed back by the SAW device is valid in step 402, the specific process is as follows:
4021, connecting the FPGA microcontroller with an oscilloscope through an RS232 serial port or an RS485 serial port;
step 4022, the FPGA microcontroller sends the received signals fed back by the SAW surface acoustic device to an oscilloscope;
and step 4023, observing that the maximum amplitude of the signal fed back by the SAW surface acoustic device is between 80 and 100mA through an oscilloscope, and indicating that the signal fed back by the SAW surface acoustic device is an effective signal.
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