CN109358484A - A kind of time-to-digit converter based on thresholding buffer - Google Patents
A kind of time-to-digit converter based on thresholding buffer Download PDFInfo
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- CN109358484A CN109358484A CN201811122886.1A CN201811122886A CN109358484A CN 109358484 A CN109358484 A CN 109358484A CN 201811122886 A CN201811122886 A CN 201811122886A CN 109358484 A CN109358484 A CN 109358484A
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
Abstract
A kind of time-to-digit converter based on thresholding buffer of the invention, including N number of a chain delay unit and b chain delay unit, encoder, first and second phase inverter；The measurement period port signal input part LP is connected with the input terminal of the port IN of the first delay cell of a chain, the port IN of the first delay cell of b chain, the input terminal of the first phase inverter INV1 and the second phase inverter；The measuring signal port input terminal EN is connected with the port enabled control terminal EN of each a chain delay unit and b chain delay unit；The output end of first phase inverter is connected with the port clear terminal rst of each a chain delay unit；The output end of second phase inverter is connected with the port clear terminal rst of each b chain delay unit.The present invention, to can be realized tired and measurement when measuring intermittent, dispersion time quantum, reduces quantization error, while choosing the lesser measured value of quantization error in double-strand to improve resolution ratio by thresholding buffer time of measuring.
Description
Technical field
The present invention relates to a kind of time-to-digit converters based on thresholding buffer, belong to fields of numeric control technique.
Background technique
DCO plays important role in many scientific research fields in collection time-to-digit converter (TDC), is that high-precision swashs
The physical basis of light pulse ranging, ultrasonic distance measurement and radar range finding.It is past between distance mearuring equipment and measured target to measure wave beam
To apart from directly proportional, range accuracy is directly determined by time interval measurement precision the time interval returned.Laser ranging, radar range finding
With ultrasonic distance measurement military affairs, space flight, aviation, in terms of suffer from extensive use.It is accurate to what is struck target in military affairs
Ranging is the basis of precision strike, improves the resolution ratio of time interval measurement, it is meant that effectively improve guidance, ignition it is accurate
Degree；In aerospace field, aircraft carries out navigation and high scale by the round-trip required time interval of precise measurement wave beam
Fixed etc., flight course is more harsh to time interval measurement precision and requirement of real-time, in real time accurately time of measuring interval, can
To ensure the safe flight of aircraft.
In conclusion TDC has a wide range of applications in fields such as Aeronautics and Astronautics, precise guidance and nuclear physics, it is to lead
Boat, space technology, communication, industrial production, electric power etc. answer the indispensable key in field.TDC is to observation and control technology in industry, national defence
And it plays the important and pivotal role in terms of learning the progress of technology.Although the TDC structure of traditional structure is simply easily achieved, point
Resolution is limited to the delay time of single delay cell.Meanwhile the time quantum for needing repeatedly to measure, common TDC more times
Measurement can not less quantization error.
Summary of the invention
Technical problem to be solved by the invention is to provide one kind by thresholding buffer time of measuring, thus between measurement
It can be realized tired and measurement when disconnected, dispersion time quantum, reduce quantization error, while it is lesser to choose quantization error in double-strand
Measured value further increases the time-to-digit converter of resolution ratio.
In order to solve the above-mentioned technical problem the present invention uses following technical scheme:
A kind of time-to-digit converter based on thresholding buffer of the invention, including N number of a chain delay unit, N number of b chain
Delay unit, encoder, the first phase inverter INV1 and the second phase inverter INV2, wherein N is the positive integer more than or equal to 3；Measurement
The periodic signal port input terminal LP and the first delay cell of a chain Ta1The port IN, the first delay cell of b chain Tb1The port IN,
The input terminal of the input terminal of one phase inverter INV1 and the second phase inverter INV2 are connected；The measuring signal port input terminal EN and each
The port enabled control terminal EN of a chain delay unit and b chain delay unit is connected；The output end of the first phase inverter INV1 with
The port clear terminal rst of each a chain delay unit is connected；The output end and each b chain of the second phase inverter INV2 is delayed
The port clear terminal rst of unit is connected；The first delay cell of a chain Ta1OUT terminal mouth and the second delay cell of a chain Ta2
The port IN and encoder Qa1Port is connected ... ..., a chain N-1 delay cell TaN-1OUT terminal mouth and a chain N postpone
Unit TaNThe port IN, encoder QaN-1Port is connected, a chain N delay cell TaNOUT terminal mouth and encoder QaN
Port is connected；The first delay cell of b chain Tb1OUT terminal mouth and the second delay cell of b chain Tb2The port IN and encoder
Qb1Port is connected ... ..., b chain N-1 delay cell TbN-1OUT terminal mouth and b chain N delay cell TbNThe port IN,
The Q of encoderbN-1Port is connected, b chain N delay cell TbNOUT terminal mouth and encoder QbNPort is connected；The volume
The output port D of code deviceFOOutput end as the time-to-digit converter based on thresholding buffer.
Above-mentioned a chain delay unit, b chain delay unit include the first PMOS transistor MP1, the second PMOS transistor MP2、
Third PMOS transistor MP3, the 4th PMOS transistor MP4, the 5th PMOS transistor MP5, the first NMOS transistor MN1, the 2nd NMOS
Transistor MN2, third NMOS transistor MN3, the 4th NMOS transistor MN4With the 5th NMOS transistor MN5；First PMOS is brilliant
Body pipe MP1Drain electrode and the second PMOS transistor MP2Source electrode be connected；The second PMOS transistor MP2Drain electrode and first
NMOS transistor MN1Drain electrode, the 4th PMOS transistor MP4Grid, third NMOS transistor MN3Grid, the 5th PMOS it is brilliant
Body pipe MP5Drain electrode be connected；The first NMOS transistor MN1Source electrode and the second NMOS transistor MN2Drain electrode be connected；
The second NMOS transistor MN2Source electrode ground connection；The third PMOS transistor MP3Drain electrode and the 4th PMOS transistor MP4
Source electrode be connected；The third NMOS transistor MN3Source electrode and the 4th NMOS transistor MN4Drain electrode be connected；Described
Four NMOS transistor MN4Source electrode ground connection.
The enabled port control terminal EN and the second NMOS transistor MN2Grid, the 4th NMOS transistor MN4Grid be connected
It connects；Reverse phase enables the port control terminal EN_n and the first PMOS transistor MP1Grid, third PMOS transistor MP3Grid be connected
It connects；The port signal input part IN and the second PMOS transistor MP2Grid, the first NMOS transistor MN1Grid be connected；Letter
Number output end OUT terminal mouth and the 4th PMOS transistor MP4Drain electrode, third NMOS transistor MN3Drain electrode, the 5th NMOS crystal
Pipe MN5Drain electrode be connected；The port clear terminal rst and the 5th NMOS transistor MN5Grid be connected；Reverse phase clear terminal rst_n
Port and the 5th PMOS transistor MP5Grid be connected.
Above-mentioned first PMOS transistor MP1Source electrode meet power vd D, the third PMOS transistor MP3Source electrode connect power supply
VDD, the 5th PMOS transistor MP5Source electrode meet power vd D；The 5th NMOS transistor MN5Source electrode ground connection.
The number of above-mentioned a chain delay unit and b chain delay unit is 16.
When the input signal of the port measuring signal input terminal EN is the i sections of time quantum Q for needing cumulative measurementiWhen, when total
Area of a room ∑ QiMeasurement result is ∑ Qi=max { aTa,bTb}；
For different size of time quantum, the maximum value in two chains is taken to export due to measuring every time, so that measurement every time
Resolution ratio it is different, average mark resolution is calculated by formula
Wherein, TLSB_FFor average mark resolution, TlcmFor TaWith TbLeast common multiple, T is found out by formulaLSB_F<Ta, relatively
It is improved in single-stranded Measurement Resolution.
The present invention uses thresholding buffer as basic delay cell, using the control terminal EN of thresholding buffer as measurement
The input terminal of signal reduces quantization error to can be realized tired and measurement when measuring intermittent, dispersion time quantum；On
The basic delay units delay time of lower two delay chains is different, chooses measured value biggish one from double-strand by encoder
It is exported as measurement result, to promote the precision of measurement.
Detailed description of the invention
Fig. 1 is the electrical block diagram of the time-to-digit converter of the invention based on thresholding buffer；
Fig. 2 is to postpone the circuit structure of unit in the time-to-digit converter of the invention based on thresholding buffer substantially to show
It is intended to；
Fig. 3 is the Transient figure of a chain in the time-to-digit converter of the invention based on thresholding buffer；
Fig. 4 is the Transient figure of b chain in the time-to-digit converter of the invention based on thresholding buffer.
Specific embodiment
Specific embodiments of the present invention will be described in further detail with reference to the accompanying drawings of the specification.
As shown in Figure 1, a kind of time-to-digit converter based on thresholding buffer designed by the present invention, including a chain
One delay cell Ta1, the second delay cell of a chain Ta2, a chain third delay cell Ta3..., the 16th delay cell T of a chaina16；b
The first delay cell of chain Tb1, the second delay cell of b chain Tb2, b chain third delay cell Tb3..., the 16th delay cell of b chain
Tb16；First phase inverter INV1, the second phase inverter INV2；Encoder, in which:
The measurement period port signal input part LP of time-to-digit converter based on thresholding buffer and a chain first postpone
Unit Ta1The port IN, the first delay cell of b chain Tb1The port IN, the first phase inverter INV1Input terminal, the second phase inverter
INV2Input terminal be connected；
The measuring signal port input terminal EN of time-to-digit converter based on thresholding buffer and all delay cells
The enabled port control terminal EN is connected；
First phase inverter INV1Output end and the first delay cell of a chain Ta1The port clear terminal rst, a chain second postpone
Unit Ta2The port clear terminal rst, a chain third delay cell Ta3The port clear terminal rst ..., the delay of a chain the 16th it is single
First Ta16The port clear terminal rst be connected, the second phase inverter INV2Output end and the first delay cell of b chain Tb1Clear terminal
The port rst, the second delay cell of b chain Tb2The port clear terminal rst, b chain third delay cell Tb3The end clear terminal rst
Mouthful ..., the 16th delay cell T of b chainb16The port clear terminal rst be connected；
The first delay cell of a chain Ta1OUT terminal mouth and the second delay cell of a chain Ta2The port IN, encoder Qa1Port
It is connected, the slow unit T of a chain seconda2OUT terminal mouth and a chain third delay cell Ta3The port IN, encoder Qa2Port phase
Connection ... ..., the 15th delay cell T of a chaina15OUT terminal mouth and the 16th delay cell T of a chaina16The port IN, encoder
Qa15Port is connected, the 16th delay cell T of a chaina16OUT terminal mouth and encoder Qa16Port is connected；
The first delay cell of b chain Tb1OUT terminal mouth and the second delay cell of b chain Tb2The port IN, encoder Qb1Port
It is connected, the slow unit T of b chain secondb2OUT terminal mouth and b chain third delay cell Tb3The port IN, encoder Qb2Port phase
Connection ... ..., the 15th delay cell T of b chainb15OUT terminal mouth and the 16th delay cell T of b chainb16The port IN, encoder
Qb15Port is connected, the 16th delay cell T of b chainb16OUT terminal mouth and encoder Qb16Port is connected；
The output port D of encoderFOOutput end as the time-to-digit converter based on thresholding buffer；
The designed time-to-digit converter based on thresholding buffer of the invention is in actual application process, to basic
Delay cell has carried out specific design, as shown in Figure 2: the basic delay cell includes the first PMOS transistor MP1, second
PMOS transistor MP2, third PMOS transistor MP3, the 4th PMOS transistor MP4, the 5th PMOS transistor MP5, the first NMOS crystal
Pipe MN1, the second NMOS transistor MN2, third NMOS transistor MN3, the 4th NMOS transistor MN4, the 5th NMOS transistor MN5,
In:
The port enabled control terminal EN of basic delay cell and the second NMOS transistor MN2Grid, the 4th NMOS transistor
MN4Grid be connected；The reverse phase of basic delay cell enables the port control terminal EN_n and the first PMOS transistor MP1Grid,
Third PMOS transistor MP3Grid be connected；
The port signal input part IN of basic delay cell and the second PMOS transistor MP2Grid, the first NMOS crystal
Pipe MN1Grid be connected；The signal output end OUT terminal mouth and the 4th PMOS transistor M of basic delay cellP4Drain electrode,
Third NMOS transistor MN3Drain electrode, the 5th NMOS transistor MN5Drain electrode be connected；
The port clear terminal rst of basic delay cell and the 5th NMOS transistor MN5Grid be connected；Basic delay is single
The reverse phase port clear terminal rst_n of member and the 5th PMOS transistor MP5Grid be connected；
First PMOS transistor MP1Source electrode meet power vd D；First PMOS transistor MP1Drain electrode and the 2nd PMOS crystal
Pipe MP2Source electrode be connected；Second PMOS transistor MP2Drain electrode and the first NMOS transistor MN1Drain electrode, the 4th PMOS crystal
Pipe MP4Grid, third NMOS transistor MN3Grid, the 5th PMOS transistor MP5Drain electrode be connected；First NMOS crystal
Pipe MN1Source electrode and the second NMOS transistor MN2Drain electrode be connected；Second NMOS transistor MN2Source electrode ground connection；
Third PMOS transistor MP3Source electrode meet power vd D；Third PMOS transistor MP3Drain electrode and the 4th PMOS crystal
Pipe MP4Source electrode be connected；Third NMOS transistor MN3Source electrode and the 4th NMOS transistor MN4Drain electrode be connected；4th
NMOS transistor MN4Source electrode ground connection；
5th PMOS transistor MP5Source electrode meet power vd D；5th NMOS transistor MN5Source electrode ground connection.
Present invention is alternatively directed to the designed time-to-digit converters based on thresholding buffer to be emulated, such as Fig. 3, Fig. 4
Shown, the end the LP input signal of TDC circuit is signal that the period is 1ns as measurement period, and the end EN input signal is the period
300ps, high level continue the pulse signal of 210ps.It is 210ps's due to measuring high level three times within the one-shot measurement period
Pulse signal, so theoretical value is 630ps.It is followed successively by from top to bottom since third signal waveform as Q in Fig. 3a1、
Qa2……、Qa16The output level at end, and delay time of the basic delay cell of each of a chain is 47ps, as shown in Figure 2 a chain
Measurement result is 13*47ps=611ps.It is followed successively by from top to bottom since third signal waveform as Q in Fig. 4b1、
Qb2……、Qb16The output level at end, and delay time of the basic delay cell of each of b chain is 75ps, as shown in Figure 4 b chain
Measurement result is 8*75=600ps.The biggish value of measurement result in a, b chain is chosen, so actual measured value is 611ps, with list
Chain single measurement reduces compared to error.In conclusion a kind of time figure based on thresholding buffer turn designed by the present invention
Parallel operation, using thresholding buffer as basic delay cell, and based on the new of vernier line style time-to-digit converter structure design
Type time-to-digit converter, using the control terminal EN of thresholding buffer as the input terminal of measuring signal, to be interrupted in measurement
, the time quantum of dispersion when can be realized tired and measurement, reduce quantization error.The basic delay cell of upper and lower two delay chains is prolonged
The slow time is different, chooses measured value biggish one from double-strand by encoder and exports as measurement result, to promote survey
The precision of amount.
Embodiments of the present invention are explained in detail above in conjunction with attached drawing, but the present invention is not limited to above-mentioned implementations
Mode within the knowledge of a person skilled in the art can also be without departing from the purpose of the present invention
It makes a variety of changes.
Claims (6)
1. a kind of time-to-digit converter based on thresholding buffer, it is characterised in that: including N number of a chain delay unit, N number of b chain
Delay unit, encoder, the first phase inverter INV1 and the second phase inverter INV2, wherein N is the positive integer more than or equal to 3；
The measurement period port signal input part LP and the first delay cell of a chain Ta1The port IN, the first delay cell of b chain Tb1IN
The input terminal of port, the input terminal of the first phase inverter INV1 and the second phase inverter INV2 is connected；
The measuring signal port input terminal EN is connected with the port enabled control terminal EN of each a chain delay unit and b chain delay unit
It connects；
The output end of the first phase inverter INV1 is connected with the port clear terminal rst of each a chain delay unit；
The output end of the second phase inverter INV2 is connected with the port clear terminal rst of each b chain delay unit；
The first delay cell of a chain Ta1OUT terminal mouth and the second delay cell of a chain Ta2The port IN and encoder Qa1End
Mouth is connected ... ..., a chain N-1 delay cell TaN-1OUT terminal mouth and a chain N delay cell TaNThe port IN, encoder
QaN-1Port is connected, a chain N delay cell TaNOUT terminal mouth and encoder QaNPort is connected；
The first delay cell of b chain Tb1OUT terminal mouth and the second delay cell of b chain Tb2The port IN and encoder Qb1End
Mouth is connected ... ..., b chain N-1 delay cell TbN-1OUT terminal mouth and b chain N delay cell TbNThe port IN, encoder
QbN-1Port is connected, b chain N delay cell TbNOUT terminal mouth and encoder QbNPort is connected；
The output port D of the encoderFOOutput end as the time-to-digit converter based on thresholding buffer.
2. the time-to-digit converter according to claim 1 based on thresholding buffer, it is characterised in that:
The a chain delay unit, b chain delay unit include the first PMOS transistor MP1, the second PMOS transistor MP2, third
PMOS transistor MP3, the 4th PMOS transistor MP4, the 5th PMOS transistor MP5, the first NMOS transistor MN1, the 2nd NMOS crystal
Pipe MN2, third NMOS transistor MN3, the 4th NMOS transistor MN4With the 5th NMOS transistor MN5；
The first PMOS transistor MP1Drain electrode and the second PMOS transistor MP2Source electrode be connected；The 2nd PMOS crystal
Pipe MP2Drain electrode and the first NMOS transistor MN1Drain electrode, the 4th PMOS transistor MP4Grid, third NMOS transistor MN3's
Grid, the 5th PMOS transistor MP5Drain electrode be connected；The first NMOS transistor MN1Source electrode and the second NMOS transistor
MN2Drain electrode be connected；The second NMOS transistor MN2Source electrode ground connection；
The third PMOS transistor MP3Drain electrode and the 4th PMOS transistor MP4Source electrode be connected；The 3rd NMOS crystal
Pipe MN3Source electrode and the 4th NMOS transistor MN4Drain electrode be connected；The 4th NMOS transistor MN4Source electrode ground connection.
3. the time-to-digit converter according to claim 2 based on thresholding buffer, it is characterised in that: enabled control terminal
The port EN and the second NMOS transistor MN2Grid, the 4th NMOS transistor MN4Grid be connected；Reverse phase enables control terminal
The port EN_n and the first PMOS transistor MP1Grid, third PMOS transistor MP3Grid be connected；The end signal input part IN
Mouth and the second PMOS transistor MP2Grid, the first NMOS transistor MN1Grid be connected；Signal output end OUT terminal mouth with
4th PMOS transistor MP4Drain electrode, third NMOS transistor MN3Drain electrode, the 5th NMOS transistor MN5Drain electrode be connected；
The port clear terminal rst and the 5th NMOS transistor MN5Grid be connected；The reverse phase port clear terminal rst_n and the 5th PMOS crystal
Pipe MP5Grid be connected.
4. the time-to-digit converter according to claim 2 based on thresholding buffer, it is characterised in that: described first
PMOS transistor MP1Source electrode meet power vd D, the third PMOS transistor MP3Source electrode meet power vd D, the 5th PMOS
Transistor MP5Source electrode meet power vd D；The 5th NMOS transistor MN5Source electrode ground connection.
5. the time-to-digit converter according to any one of claims 1 to 4 based on thresholding buffer, feature exist
In: the number of a chain delay unit and b chain delay unit is 16.
6. the time-to-digit converter according to any one of claims 1 to 4 based on thresholding buffer, feature exist
In: when the input signal of the port measuring signal input terminal EN is the i sections of time quantum Q for needing cumulative measurementiWhen, total time quantum ∑
QiMeasurement result is ∑ Qi=max { aTa,bTb, wherein a indicates that the series that signal passes through in a chain, Ta indicate the buffer of a chain
Delay time, b indicate that the series that signal passes through in b chain, Tb indicate the buffer delay time of b chain；
For different size of time quantum, the maximum value in two chains is taken to export due to measuring every time, so that point measured every time
Resolution is different, and average mark resolution is calculated by formula
Wherein, TLSB_FFor average mark resolution, TlcmFor TaWith TbLeast common multiple, T is found out by formulaLSB_F<Ta, relative to single-stranded
Measurement Resolution improves.
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| CN110376872A (en) * | 2019-05-29 | 2019-10-25 | 西安电子科技大学 | A kind of time-to-digit converter applied to TADC based on asynchronous reset |
| CN110401439A (en) * | 2019-07-25 | 2019-11-01 | 上海华力微电子有限公司 | A kind of delay cell of delay locked loop |
| CN112506030A (en) * | 2021-02-04 | 2021-03-16 | 南京邮电大学 | Time-digital converter based on PVT detection circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110376872A (en) * | 2019-05-29 | 2019-10-25 | 西安电子科技大学 | A kind of time-to-digit converter applied to TADC based on asynchronous reset |
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| CN112506030B (en) * | 2021-02-04 | 2021-07-13 | 南京邮电大学 | Time-digital converter based on PVT detection circuit |
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