JP5459089B2 - TDC circuit - Google Patents

Description

  The present invention relates to a TDC (Time to Digital Converter) circuit that quantizes a time difference and converts it into digital data using a pulse signal.

  In a wireless communication apparatus, it has been studied to digitize an RF circuit that has been configured using analog elements. As an example, an ADPLL (All Digital phase Locked Loop) circuit corresponding to a PLL (Phase Locked Loop) circuit has been proposed.

  In the ADPLL circuit, the TDC circuit detects a phase difference between two clocks and generates a digital value corresponding to the phase difference. In realizing the ADPLL circuit, a technique for improving the resolution of the TDC circuit is one of the problems.

  The TDC circuit, for example, is configured to input a clock signal to be detected as a phase difference to a plurality of delay elements connected in series, and latch the outputs of these delay elements in synchronization with a reference clock (Patent Document 1). reference).

  In addition to the first series including a series of delay elements to which a phase detection target clock signal is input, a configuration including a second series including delay elements in which the same number of other delay elements are connected in series is also possible. It has been proposed (see Patent Document 2). In this configuration, the reference clock is input to the second series, and the output of the corresponding delay element included in the first series is latched in synchronization with the output signal of each delay element.

  Furthermore, a TDC circuit having a delay circuit in which an odd number of inverters are connected in a loop so that pulse signal propagation continuously occurs has also been proposed (see Patent Document 3).

Japanese Patent Laid-Open No. 2002-076886 JP 2007-110370 A JP 2005-52059 A

  By the way, the resolution of the TDC circuit having the configuration shown in Patent Document 1 is limited to the delay amount of each delay element connected in series. On the other hand, the resolution of the TDC having the configuration disclosed in Patent Document 2 corresponds to the difference between the delay amount of the delay element included in the first series and the delay amount of the delay element included in the second series. Therefore, the resolution can be improved by reducing the difference in delay amount of the delay elements included in the two sequences.

  However, in any configuration, the maximum value of the phase difference that can be detected by the TDC circuit is limited by the delay amount of the entire delay elements connected in series. Therefore, in order to increase the maximum value of the detectable phase difference, a configuration in which a large number of delay elements are connected in series is required, which increases the circuit scale.

  On the other hand, since the delay circuit is connected in a loop in the TDC circuit disclosed in Patent Document 3, it is possible to increase the maximum detectable phase difference without increasing the circuit scale. It is. However, in the TDC provided with such a loop-like delay circuit, it is possible to expand the range of the detectable phase difference, but it is difficult to improve the resolution.

  An object of the present disclosure is to provide a TDC circuit that can achieve both expansion of a detectable range and improvement of resolution.

  The above-described object can be achieved by the TDC circuit disclosed below.

  A TDC circuit according to one aspect includes a first delay circuit including a loop formed by connecting 2n first inversion delay elements in series, and a second delay time different from that of the first inversion delay element. The output logic value of each of the second delay circuit including a loop formed by connecting 2n inversion delay elements in series and the first inversion delay element included in the first delay circuit is expressed as the first inversion delay. A latch circuit that latches in synchronization with the output signal of the second inversion delay element corresponding to the element, a detection target edge that indicates the timing of logical inversion of the input signal that is the target of time difference detection, and the detection target edge A first pulse signal driving circuit for generating a pulse signal having a first reset edge for resetting the inverted logic and propagating it in a loop of the first delay circuit, and according to an input of a reference signal different from the input signal , Enter A pulse signal having a reference edge indicating a timing serving as a reference for detecting a time difference from the signal and a second reset edge for resetting a logic inverted corresponding to the reference edge is generated and propagated in a loop of the second delay circuit The logic inversion corresponding to the input of the first reset edge to be propagated is selectively cut off with respect to either the second pulse signal driving circuit to be activated or the first inversion delay element included in the first delay circuit. A first cutoff circuit that performs an operation and a first inversion delay element that is to be cut off by the first cutoff circuit are configured to perform an operation of resetting the inverted logic according to the input of the propagated detection target edge. One of the reset circuit and the second inversion delay element included in the second delay circuit selectively blocks logic inversion corresponding to the input of the propagated second reset edge. A second cutoff circuit that performs an operation, and a second reset circuit that performs an operation of resetting the inverted logic in accordance with the input of the propagated reference edge with respect to the second inversion delay element to be cut off by the second cutoff circuit And a reset circuit.

  According to the TDC circuit of the present disclosure, it is possible to achieve both expansion of the detectable range and improvement of resolution.

It is a figure which shows one Embodiment of a TDC circuit. It is a figure which shows the structural example of TDC of a vernier delay type. It is a figure explaining the dispersion | variation in delay amount. It is a timing diagram explaining generation | occurrence | production of a stable state. It is a figure which shows one Embodiment of an inversion delay element. It is a timing diagram explaining operation | movement of a interruption | blocking circuit and a reset circuit. It is a figure which shows another embodiment of a 2nd delay circuit. It is a figure which shows embodiment of an ADPLL circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows an embodiment of a TDC circuit.

  The TDC circuit illustrated in FIG. 1 includes a vernier delay type TDC circuit including a first delay circuit 101 and a second delay circuit 102, and reset circuits 111 and 112 and cutoff circuits 113 and 114, respectively. Is done. Each of the first delay circuit 101 and the second delay circuit 102 includes a configuration in which an even number of inversion delay elements (for example, inverters) are connected in a loop. The reset circuit 111 corresponds to a first reset circuit, and the cutoff circuit 113 corresponds to a first cutoff circuit. Similarly, the reset circuit 112 corresponds to a second reset circuit, and the cutoff circuit 114 corresponds to a second cutoff circuit.

  Prior to the description of the TDC circuit shown in FIG. 1, a vernier delay type TDC circuit will be described.

  FIG. 2 shows a configuration example of a vernier delay type TDC circuit. 2 that are equivalent to the components shown in FIG. 1 are denoted by the same reference numerals.

The first delay circuit 101 and the second delay circuit 102 shown in FIGS. 1 and 2 each include a configuration in which 2n (n is a natural number) inverting delay elements are connected in a loop. In the example shown in FIGS. 1 and 2, the first delay circuit 101 includes eight inverters (INV) _{11 to} INV ₁₈ connected in a loop. The second delay circuit 102 includes a configuration in which the same number of INV ₂₁ to INV ₂₈ are connected in a loop. Further, the delay time _{d 1} of each inverter (INV) ₁₁ ~INV ₁₈ included in the first delay circuit 101 is the delay time _{d 2} of each inverter (INV) ₂₁ ~INV ₂₈ included in the second delay circuit 102 Can be selected to be smaller.

  The latch circuit 105 shown in FIGS. 1 and 2 includes the same number of latches corresponding to the eight inverters provided in the first delay circuit 101 and the second delay circuit 102. These latches hold the logical value of the output of each inverter included in the first delay circuit 102 in synchronization with the inversion of the output of each inverter included in the second delay circuit 102. The outputs of these latches are subjected to a phase difference calculation process by the phase difference calculation control unit 108.

Prior to starting measurement by the TDC circuit, initial values are set by the phase difference calculation control unit 108 for the output logic of INV ₁₁ to INV ₁₈ included in the first delay circuit 101 described above. For example, the phase difference calculation control unit 108 can set the logic “H” as an initial value to these inverters by resetting the even-numbered inverters by the control signal INIT. In response, the output of the odd-numbered inverter is set to logic “L”. Similarly, initial values are set in INV ₂₁ to INV ₂₈ included in the second delay circuit 102.

The first delay circuit 101 shown in FIGS. 1 and 2 includes a pulse signal drive circuit 103 that generates a pulse in response to an input signal. The pulse signal drive circuit 103 corresponds to a first pulse signal drive circuit. In the example shown in FIGS. 1 and 2, the pulse signal drive circuit 103 including a flip-flop, an inverter, and a NAND gate resets the fifth-stage inverter (INV ₁₅ ) in response to the rising edge of the input signal, and this INV ₁₅ Force the output of. The pulse signal driving circuit 103 uses the output signals of the first stage INV ₁₁ and the fourth stage INV ₁₅ to return the above-described INV ₁₅ output to the same logic “L” as the initial value. I do. As a result, a pulse signal having a duty ratio of 0.5 is generated with a total of 8 × d ₁ of delay times d ₁ by eight inverters connected in a loop as one cycle.

The pulse signal generated in this manner circulates in a loop including INV _{11 to} INV ₁₈ . The counter 106 counts the number of times this pulse signal has circulated through the loop including INV ₁₁ to INV ₁₈ .

The second delay circuit 102 also includes a pulse signal drive circuit 104 including the same configuration as the pulse signal drive circuit 103 described above. The pulse signal drive circuit 104 corresponds to a second pulse signal drive circuit. In the example of FIGS. 1 and 2, the pulse signal driving circuit 104 operates the fifth stage INV ₂₅ among the loop-connected inverters included in the second delay circuit 102. Note that a reference signal is input to the pulse signal driving circuit 104 instead of the above-described input signal, and is used for the reset operation of the INV ₂₅ . Then, the pulse signal driving circuit 104 sets a total of 8 × d ₂ of delay times d ₂ by eight inverters connected in a loop as one cycle according to the input of the reference signal, and has a duty ratio of ½. A pulse signal is generated.

The pulse signal generated in this way similarly circulates through a loop including INV ₂₁ to INV ₂₈ . The counter 107 counts the number of times this pulse signal has circulated through the loop including INV ₂₁ to INV ₂₈ .

  The phase difference calculation control unit 108 calculates a value REV indicating the measurement result of the phase difference between the input signal and the reference signal based on the output of the latch circuit 105 and the count values of the counters 106 and 107 described above. Further, the phase difference calculation control unit 108 outputs a control signal EOC indicating the timing at which the measurement result converges.

  For details of the phase difference calculation processing by the vernier delay type TDC circuit, refer to Japanese Patent Application No. 2009-802886 “TDC circuit and ADPLL circuit” by the present applicant.

  In the vernier delay type TDC circuit configured as described above, it is possible to achieve both the expansion of the detectable range of the phase difference between the input signal and the reference signal and the improvement of the resolution while suppressing the circuit scale. In addition, since the number of inverters connected in a loop in the first delay circuit 101 and the second delay circuit 102 is an even number, the metastable state of each latch included in the latch circuit 105 can be avoided. .

  By the way, the delay time until the logical change of the input signal to the inverter is reflected in the logical change of the output of the inverter depends on whether the generated logical change is a rise from the logic “L” to the logic “H” or vice versa. It may differ depending on whether it is falling.

  In the configuration in which the pulse signal generated as described above is circulated in a loop in which an even number of inverters having such delay time variations are connected, the pulse waveform disappears while the pulse signal is circulated. There is a possibility that. That is, in the vernier delay type TDC circuit configured as described above, the loop to which the inverter is connected may be in a stable state.

  Next, the mechanism by which the loop to which the inverter is connected becomes stable in a vernier delay type TDC circuit having a configuration in which a plurality of inverters are connected in a loop will be described. In the following description, in the pulse signals generated by the pulse signal drive circuits 103 and 104, an edge corresponding to the logic inversion at the input timing of the input signal or the reference signal is referred to as a detection target edge. In this pulse signal, an edge corresponding to a logic inversion in a direction in which the logic value inverted at the detection target edge is returned to the initial value is referred to as a reset edge.

  FIG. 3 is a diagram for explaining the variation in the delay amount. FIG. 4 is a timing chart for explaining the occurrence of a stable state. Hereinafter, the operation of the second delay circuit 102 in which the reference signal is input prior to the input signal will be described as an example.

In the example shown in FIG. 3, the rising delay time falls in the even delay stages INV ₂₂ , INV ₂₄ , INV ₂₆ , INV ₂₈ included in the second delay circuit 102 shown in FIGS. _{It is} shorter than ₂ by the difference Δ. In the odd-numbered stages INV ₂₁ , INV ₂₃ , INV ₂₅ , and INV ₂₇ , conversely, the falling delay time is shorter than the rising delay time d ₂ by the difference Δ.

  In the configuration in which an even number of inverters are connected in a loop, the delay time variation as shown in FIG. 3 is accumulated in the propagation times of the two edges of the pulse signal in the process of circulating the pulse signal. To go.

For example, in FIG. 4, the falling edge of INV ₂₁ shown corresponding to time T ₁ is propagated as the rising edge in INV ₂₂ , INV ₂₄ , INV ₂₆ , and INV ₂₈ in even stages. On the other hand, in the odd stages of INV ₂₃ , INV ₂₅ , INV ₂₇ , they are propagated as falling edges.

That is, the falling edge of the INV ₂₁ is propagated by the inverter of each stage with a shorter delay time, and thus the above-described difference Δ is accumulated over the number of inverter stages. Therefore, the time required for the falling edge of this INV ₂₁ to make a round of the loop is 8 (d ₂ −Δ), which is shorter than 8 times the delay time d ₂ .

On the other hand, the rising edge of INV ₂₁ shown in FIG. 4 corresponding to time T ₅ is propagated as a falling edge in the even-numbered stages INV ₂₂ , INV ₂₄ , INV ₂₆ , and INV ₂₈ . Conversely, in the odd-numbered stages INV ₂₃ , INV ₂₅ , and INV ₂₇ , they are propagated as rising edges. For this reason, the time required for the rising edge of INV ₂₁ to go around the loop is 8d _{2 which} is exactly 8 times the delay time d ₂ .

The above-described falling edge and rising edge of INV ₂₁ correspond to the detection target edge or reset edge of the pulse signal generated by the pulse signal driving circuit 104. That is, the delay time variation as shown in FIG. 3 causes a difference between the period in which the detection target edge propagates through the loop and the period in which the reset edge propagates through the loop. For this reason, as shown in FIG. 4, every time the pulse signal circulates in the loop, the duty ratio of the pulse signal gradually changes.

For example, paying attention to one cycle starting from the falling edge of INV ₂₁ shown corresponding to time T ₁ in FIG. 4, the period 4d ₂ -8Δ in which the output of INV ₂₁ is logic “H” is the output of INV ₂₁ There has been shorter than that of the period 4d ₂ is a logic "L". When attention is paid to one period starting from the falling edge of INV ₂₁ shown in FIG. 4 corresponding to time T ₉ , the period during which the output of INV ₂₁ is logic “H” is further shortened to 4d ₂ −16Δ. Become. On the other hand, the period during which the output of INV ₂₁ is logic “L” is 4d ₂ + 8Δ, which indicates that the duty of the pulse signal further changes.

In the example shown in FIGS. 3 and 4, each time the pulse signal goes around the loop, the period during which the output of INV ₂₁ is logic “H” is shortened by 8Δ. This shortening accumulates, and when the period during which the output of INV ₂₁ is logic “H” becomes 0, the loop connected with the 8-stage inverter becomes stable. For example, if the delay time d ₂ and the variation Δ are 100 ps and 0.25 ps, respectively, when the pulse signal makes 1610 loops, the two edges overlap and the pulse signal disappears.

Therefore, the range until the disappearance of the pulse signal as described above becomes a detectable range of the phase difference by the vernier delay type TDC circuit in which the even-numbered inverters are connected in a loop. In the above example, if the delay time d ₁ of each inverter included in the first delay circuit 101 to 90 ps, the phase difference between the reference signal and the input signal, the range can be detected up to 160.1Ns.

  Note that the examples shown in FIGS. 3 and 4 are extreme examples in which the delay time of each inverter varies so as to increase the difference between the period of propagation of the detection target edge and the period of propagation of the reset edge. . Therefore, by selecting the inverter element so that the variation in delay time of each inverter cancels the difference between the period of propagation of the detection target edge and the period of propagation of the reset edge, there is no practical problem in the detectable range. Can be extended to a degree. For example, in the above-mentioned Japanese Patent Application No. 2009-802886 “TDC circuit and ADPLL circuit”, the difference between the cycle in which the detection target edge propagates and the cycle in which the reset edge propagates is obtained by making the inverter connected in a loop form a pseudo differential. The reduction of is planned.

Nonetheless, it is difficult to completely cancel the delay time variations of individual inverters. For this reason, the vernier delay type TDC circuit configured as shown in FIG. 2 has a problem that the detectable range of the phase difference is limited to the range until the stable state occurs.
(Embodiment 1)
Next, a method for avoiding the occurrence of the stable state as described above by the reset circuits 111 and 112 and the cutoff circuits 113 and 114 shown in FIG. 1 will be described.

The reset circuit 111 illustrated in FIG. 1 resets the sixth-stage inverter INV ₁₆ using the output of the first-stage inverter INV ₁₁ included in the first delay circuit 101. Similarly, the reset circuit 112 resets the sixth-stage inverter INV ₂₆ using the output of the first-stage inverter INV ₂₁ included in the second delay circuit 102. In the example shown in FIG. 1, the inverter INV ₁₆ corresponds to a third inverting delay element, and the other inverters correspond to a first inverting delay element.

Further, the cutoff circuit 113 shown in FIG. 1 performs an operation of cutting off the input signal to the sixth-stage inverter INV ₁₆ using the output of the seventh-stage inverter INV ₁₇ included in the first delay circuit 101. Do. Similarly, the cutoff circuit 114 performs an operation of cutting off the input signal to the sixth-stage inverter INV ₂₆ using the output of the seventh-stage inverter INV ₂₇ included in the second delay circuit 102. In the example shown in FIG. 1, the inverter INV ₂₆ corresponds to a fourth inversion delay element, and the other inverters correspond to a second inversion delay element.

  Such a third inversion delay element and a fourth inversion delay element can be realized by modifying the reset function unit of a complementary input / output inverter having a reset function.

  FIG. 5 shows an embodiment of the inverting delay element. FIG. 5A is an example of an embodiment of a third inversion delay element and a fourth inversion delay element. FIG. 5B shows a configuration example of the first inversion delay element and the second inversion delay element. For detailed operation of the inverter shown in FIG. 5B, refer to the above-mentioned Japanese Patent Application No. 2009-802886 “TDC circuit and ADPLL circuit”.

  5A and 5B, in the inverter shown in FIG. 5A, the cutoff signals SHT and SHTx for controlling the operation of the circuit on the input side that receives the complementary inputs IN and INx, and The reset signals RST and RSTx for controlling the operation of the output side circuit are separated.

  Then, by inputting logic “L” as the cutoff signal SHTx and logic “H” as the complementary cutoff signal SHT, the input terminals IN and INx and the output terminals OUT and OUTx are blocked in this inverter. .

  On the other hand, by inputting the logic “L” as the reset signal RSTx and the logic “H” as the complementary reset signal RST, the outputs OUT and OUTx of the inverter are respectively set to the logic “H” and the logic “L”. Reset to.

  As described above, in the inverter shown in FIG. 5A, the output reset unit that resets the output logic and the input blocking unit that separates the input logic and the output logic are complemented in the same manner as the complementary blocking signals SHT and SHTx. It is possible to operate independently according to typical reset signals RST and RSTx. When the inverter shown in FIG. 5A is used as the third inverting delay element, the two transistors to which the reset signals RST and RSTx are input correspond to the first output reset unit. On the other hand, the four transistors to which the cutoff signals SHT and SHTx are input correspond to the first input cutoff unit. Similarly, when the inverter illustrated in FIG. 5A is used as the fourth inversion delay element, the two transistors to which the reset signals RST and RSTx are input correspond to the second output reset unit. On the other hand, the four transistors to which the cutoff signals SHT and SHTx are input correspond to a second input cutoff unit.

  Note that the timing of the reset operation executed in response to the reset signals RST and RSTx is preferably within a period in which the input terminals IN and INx are disconnected from the output terminals OUT and OUTx.

  Further, the outputs of the inverter included in the first delay circuit 101 and the inverter included in the second delay circuit 102 shown in FIG. 1 are complementary. Therefore, the outputs of these inverters can be used as they are as the cutoff signals SHT and SHTx and the reset signals RST and RSTx.

In the first delay circuit 101 configured as described above, the reset edge of the pulse signal circulating in the loop is newly generated for each cycle when the reset circuit 111 resets the sixth-stage inverter INV ₁₆ . At this time, the cutoff circuit 113 shuts off the input of the inverter INV ₁₆ before and after the timing at which the reset edge propagates from the previous stage INV ₁₅ so that the operation by the reset circuit 111 is normally performed.

Similarly, in the second delay circuit 101 including the reset circuit 112 and the cutoff circuit 114, the reset edge of the pulse signal that circulates in the loop is reset every time by performing a reset operation on the sixth-stage inverter INV ₂₆ . Newly generated.

FIG. 6 is a timing chart for explaining the operation of the cutoff circuit and the reset circuit. Hereinafter, the description will be given focusing on the output of the sixth stage INV ₂₆ provided in the second delay circuit 102.

Since INV ₂₆ is an even-numbered stage, the initial value is logic “H”, the falling edge is the detection target edge, and the reset edge is the rising edge. In FIG. 6, the detection target edge is indicated by an arrow with a symbol “S”, and the reset edge is indicated by an arrow with a symbol “R”.

In FIG. 6, the detection target edge S of the output of the INV ₂₆ shown corresponding to the time T ₁ is sequentially propagated by the remarkable inverters connected in a loop as indicated by the thin solid line arrows. Detected edges and around the loop in this way, again reaches the INV ₂₆ at time T _9. Then, when this detection target edge is propagated to INV ₂₇ at time T _{10 and} the output logic of INV ₂₇ is inverted, the interruption circuit 113 shown in FIG. 1 uses the output of INV ₂₇ to change INV ₂₆ . An operation to turn off is performed.

For example, the shut-off circuit 113 can realize an operation of putting the INV ₂₆ in the shut-off state by inputting the output OUTx of the INV _{27 to} the INV ₂₆ as the shut-off signal SHTx. This cutoff signal SHTx corresponds to a cutoff control input. In addition, in FIG. 6, this interruption | blocking operation was shown with the arrow of the thick broken line which attached | subjected the code | symbol (1).

On the other hand, the detection target edge described above can continue to further propagate, when the output logic of the _{INV 21} is inverted at time _{T 12,} the reset circuit 114 shown in FIG. 1, using the output of the _{INV 21, INV 26} An operation to reset is performed.

For example, the reset circuit 114, by inputting the output OUTx of _{INV 21} to _{INV 26} as a reset signal RSTX, it is possible to realize an operation for resetting the _{INV 26.} This reset signal RSTx corresponds to a reset control input. In FIG. 6, this reset operation is indicated by a thick dashed arrow with a reference sign (2).

As described above, the reset operation can be normally performed by inputting the reset signal to the INV ₂₆ by the reset circuit 114 as described above during the period in which the INV ₂₆ is in the cutoff state. The timing at which the output logic of the INV ₂₆ is inverted in response to a reset operation, the output logic of the INV ₂₁ is determined at the timing of inverting the propagation of detected edges shown corresponds to a time T _9. That is, in the second delay circuit 102 shown in FIG. 1, the reset edge is newly generated every round by the reset operation on the INV 26 without circulating through the loop. A state in which the reset edge propagates through the inverters of each stage connected in a loop shape is indicated by a thin broken arrow in FIG.

The timing at which the reset edge generated last time from the previous INV ₂₅ arrives at the timing at which a new reset edge is generated in response to the reset operation described above. Therefore, as shown in FIG. 1, in the second delay circuit 102 configured to include the reset circuit 112 and the cutoff circuit 114, it is possible to avoid the occurrence of a stable state in a loop in which an even number of inverters are connected. .

  Similarly, as shown in FIG. 1, in the first delay circuit 101 configured with the reset circuit 111 and the cutoff circuit 113, generation of a stable state in a loop in which an even number of inverters are connected is avoided. Can do.

Incidentally, as shown in FIG. 6, will propagate the reset edge generated by the reset operation, reaches the INV ₂₇ at time T _13, inverts the output logic. At this logic inversion timing, the logic of the cutoff signal SHTx input to the INV ₂₆ by the cutoff circuit 114 is also inverted. In response to this, the blocking operation for the INV ₂₆ is released, and the blocking period ends. In FIG. 6, the release of the shut-off operation is indicated by a thick broken-line arrow with a symbol (3).

Then, the reset edge continue to further propagate, at time _{T 15,} reaches the _{INV 21,} inverts the output logic. At the logic inversion timing, the logic of the reset signal RSTx input to the INV ₂₆ by the reset circuit 112 is also inverted. In response, the reset operation for INV ₂₆ is released and the reset period ends. In FIG. 6, the cancellation of the reset operation is indicated by a thick dashed arrow with a reference (4).

  In the first delay circuit 101, the third inverting delay element can be disposed at any inverter position other than the INV 15 that is operated by the pulse signal driving circuit 103. The reset circuit 111 can perform a reset operation on the third inversion delay element by using the output of the inverter that is separated from the third inversion delay element by a plurality of stages. Further, the cutoff circuit 113 can perform a cutoff operation on the third inversion delay element by using the output of the inverter located between the inverter used by the reset circuit 111 and the third inversion delay element. .

Further, the inverter whose output is used by the reset circuit 111 is selected so that the reset period as shown in FIG. 6 ends before the detection target edge circulating in the loop reaches the third inversion delay element. can do. For example, by setting the number of inverter stages sandwiched between the inverter that uses the output and the third inverting delay element by the reset circuit 111 to be equal to or less than half of the number 2n of inverters connected to the loop, the above-described condition is satisfied. Can be satisfied.
(Embodiment 2)
FIG. 7 shows another embodiment of the second delay circuit. 7 that are the same as those shown in FIG. 1 are given the same reference numerals, and descriptions thereof are omitted.

In the second delay circuit 102 shown in FIG. 7, the reset circuit 112 includes a circuit that inputs the output OUT of the second stage INV _{22 to} the INV ₂₆ as the reset signal RSTx. The cutoff circuit 114 includes a circuit that inputs the output OUT of the eighth stage INV _{28 to} the INV ₂₆ as the cutoff signal SHTx.

  In the example shown in FIG. 7, in the second delay circuit 102, a four-stage inverter corresponding to half the number of stages of inverters connected in a loop between INV26 and INV22 corresponding to the third inverting delay element is sandwiched. Yes. Therefore, in the loop provided in the second delay circuit 102, the duty ratio of the circulating pulse signal is 0.5.

  In FIG. 7, the outputs OUT and OUTx of the odd-numbered inverters are input to the clock terminals CK and CKx of the corresponding latches provided in the latch circuit 105, respectively. On the other hand, the outputs OUT and OUTx of the even-numbered inverters are respectively input to the clock terminals CKx and CK of the corresponding latches.

  Similarly to the second delay circuit 102 shown in FIG. 7, the reset circuit 111 and the cutoff circuit 113 provided in the first delay circuit 101 can be configured.

  In the first delay circuit 101 and the second delay circuit 102 configured as described above, an even number of inverters are connected in the same manner as the first delay circuit 101 and the second delay circuit 102 shown in FIG. Occurrence of a stable state in the loop can be avoided.

  That is, by providing the delay circuit configured as shown in FIG. 1 and FIG. 7, the problem in the TDC circuit having a loop in which an even number of inverters are connected is solved, and the phase difference detectable range of the TDC circuit is reduced. Both enlargement and improvement in resolution can be achieved.

Thereby, it is possible to provide a TDC circuit having both the accuracy required for the ADPLL circuit and the detectable range.
(Embodiment 3)
FIG. 8 shows an embodiment of the ADPLL circuit.

  In the ADPLL circuit shown in FIG. 8, the integrators 211 and 212 respectively integrate the set frequency data (FCW) and the output clock CLKOUT. The integration result by the integrator 212 is passed to the adder 219 via the latch 213 and is subtracted from the integration result by the integrator 211.

  The reference signal REF input to the ADPLL circuit is input to the second delay circuit 102 via the start terminal provided in the TDC circuit 215. The latch 214 latches the reference signal REF in synchronization with the output clock CLKOUT. The output of the latch 214 is input via a stop terminal provided in the TDC circuit 215 and used as an input signal to the first delay circuit 101. Then, the TDC circuit 215 detects the phase difference between the reference signal input to the start terminal and the input signal input via the stop terminal in a range smaller than the counting unit by the two integrators 211 and 212 described above. To do.

  The phase difference detection result REV generated by the TDC circuit 215 is normalized by a clock generation unit (CLKGEN) 216, a normalization unit 217, and a multiplier 218. Then, the normalized phase difference detection result is passed to the adder 219 described above and added to the difference between the two integrators 211 and 212.

  The output of the adder 219 is passed to the digitally controlled oscillator (DCO) 223 via the loop filter (LPF) 222 and used for controlling the output clock. The lock detector (LOCK) 221 detects the establishment of synchronization between the reference signal and the output clock CLKOUT based on the output of the adder 219.

  In the ADPLL circuit configured as described above, the TDC circuit 215 can reliably detect the phase difference even when there is a phase difference close to one cycle of the output signal CLKOUT between the reference signal and the input signal.

  As described above, in the TDC circuit including the delay circuit configured as shown in FIGS. 1 and 7, the occurrence of the stable state described above can be avoided. Therefore, it is possible to realize a phase difference detectable range larger than that required by the ADPLL circuit.

  Therefore, a TDC circuit having a delay circuit configured as shown in FIGS. 1 and 7 can be applied to an ADPLL circuit, for example, a difference between a light emission time and an incident time of reflected light from an object. Can be obtained using a TDC circuit, and can be applied to a purpose of accurately measuring the distance to an object.

101, 401 First delay circuit 102, 402 Second delay circuit 103, 104 Pulse signal driving circuit 105 Latch circuit 106, 107 Counter 108 Phase difference calculation control unit 111, 112 Reset circuit 113, 114 Cutoff circuit 211, 212 Integration 213, 214 Latch 215 TDC circuit 216 Clock generator (CLKGEN)
217 Normalization unit 218 Multiplier 219 Adder 221 Lock detection unit (LOCK)
222 Loop filter (LPF)
223 Digitally controlled oscillator (DCO)
_{INV 11 ~INV 18, INV 21 ~INV} 28 inverter

Claims (3)

A first delay circuit including a loop formed by connecting 2n first inversion delay elements in series;
A second delay circuit including a loop formed by connecting the 2n second inversion delay elements having a delay time different from that of the first inversion delay element in series;
A latch that latches the output logic value of each of the first inversion delay elements included in the first delay circuit in synchronization with the output signal of the second inversion delay element corresponding to the first inversion delay element. Circuit,
A pulse signal having a detection target edge indicating a logic inversion timing of an input signal to be subjected to time difference detection and a first reset edge for resetting a logic inverted corresponding to the detection target edge is generated, and the first signal is generated. A first pulse signal driving circuit to propagate in the loop of the delay circuit;
In response to an input of a reference signal different from the input signal, a reference edge indicating a timing serving as a reference for detecting a time difference from the input signal, and a second reset edge for resetting a logic inverted corresponding to the reference edge, A second pulse signal driving circuit that generates a pulse signal having the following characteristic and propagates in the loop of the second delay circuit:
A first operation for selectively blocking logic inversion corresponding to the input of the propagated first reset edge with respect to any of the first inversion delay elements included in the first delay circuit. A shut-off circuit of
A first reset circuit that performs an operation of resetting the inverted logic in response to the input of the propagated detection target edge with respect to the first inversion delay element to be blocked by the first cutoff circuit;
A second operation for selectively blocking logic inversion corresponding to the input of the second reset edge to be propagated to any one of the second inverting delay elements included in the second delay circuit; A shut-off circuit of
A second reset circuit that performs an operation of resetting the inverted logic in response to the input of the propagated reference edge with respect to the second inverting delay element to be blocked by the second blocking circuit;
A TDC circuit comprising: The TDC circuit according to claim 1, wherein
The first delay circuit includes a configuration in which any one of the predetermined number of first inversion delay elements is replaced with a third inversion delay element having a delay time equivalent to that of the first inversion delay element,
The second delay circuit includes a configuration in which any one of the predetermined number of second inversion delay elements is replaced with a fourth inversion delay element having a delay time equivalent to that of the second inversion delay element,
The third inversion delay element is
A first input cutoff unit that disconnects an input and an output from the third inverting delay element according to a logical value of the cutoff control input;
A first output reset unit that continues the reset state of the output logic of the third inverting delay element according to the logic value of the reset control input;
The fourth inversion delay element is
A second input cutoff unit that disconnects an input and an output from the fourth inverting delay element according to a logical value of the cutoff control input;
A second output reset unit that continues the reset state of the output logic of the fourth inverting delay element according to the logic value of the reset control input,
In the loop of the first delay circuit, the first reset circuit outputs an output signal of the first inversion delay element located at a plurality of stages away from the third inversion delay element in a signal propagation direction. A circuit for inputting as a reset control input of the first output reset unit provided in the third inverting delay element;
The first cut-off circuit outputs an output signal of another first inversion delay element located between the third inversion delay element and the first inversion delay element used in the first reset circuit. Is input as a cutoff control input of the first input cutoff unit provided in the third inverting delay element,
In the loop of the second delay circuit, the second reset circuit outputs the output signal of the second inversion delay element located at a plurality of stages away from the fourth inversion delay element in the signal propagation direction. A circuit for inputting as a reset control input of the second output reset unit included in the fourth inversion delay element;
The second cutoff circuit outputs an output signal of another second inversion delay element located between the fourth inversion delay element and the second inversion delay element used in the second reset circuit. Is input as a cutoff control input of the second input cutoff unit provided in the fourth inverting delay element,
A TDC circuit characterized by that. The TDC circuit according to claim 2, wherein
In the loop of the first delay circuit, the first reset circuit receives an output signal of the first inversion delay element located apart from the third inversion delay element by k stages, which is a natural number equal to or less than n. Use
In the loop of the second delay circuit, the second reset circuit receives an output signal of the second inversion delay element located apart from the fourth inversion delay element by k stages, which is a natural number equal to or less than n. Use
A TDC circuit characterized by that.

Images