SU1104527A1 - Device for executing orthogonal walsh transform - Google Patents

Abstract

ORTHOGONAL TRANSFORMATION BY WALSHE device containing adders, information signal switch, shift register, Walsh function generating unit and clock switch, the first input of which is the clock input of the device, the clock output of the clock switch is connected to the clock input of the shift register, overflow which is connected to the control input of the clock switch, the second output of which is connected to the clock input of the Walsh function shaping unit, information The inputs of the adders are combined and are the information input of the device, the control inputs of the adders are connected to the outputs of the corresponding bits of the shift register, characterized in that, in order to expand the functional capabilities of the device by performing the reconstruction of the signals represented by the expansion coefficients of the integral Walsh functions, it contains registers, direct binary code converters to inverse, summing unit, first and second adders with accelerated propagation of hyphenation, buf a register and a trigger, the outputs of the adders are connected to the information inputs of the registers, the reception control inputs of which are combined and connected to the overflow output of the shift register, the outputs of the registers are connected to the information inputs of direct binary code converters, the control inputs of which are connected to the corresponding outputs Walsh function generation unit; the outputs of the direct transducers (of the first binary code into the reverse code are connected to the inputs of the summing block, the output of which is connected to the input The first accelerated spreading adder, the output of which is the first output of the device and connected to the information input of the buffer register and the first input of the second adder with accelerated transfer of transfers, the second input of the cSP to which is connected to the output of the buffer register and the second information input of the switch information signals, the first information input of which is connected to the output of the second adder with the accelerated propagation of carries, the control input of the buffer register connected to the second output of the clock switch, the clock and control inputs of which are connected respectively to the first and second inputs of the trigger, the output of which is connected to the control, the input of the information switch

Description

the signals whose output is the second output of the device; controlling 1104527 the input of the shift register is the controlling (device input.

The invention relates to automation and computing and can be used in image processing equipment, data compression during data transfer, for analyzing and processing audio and video signals. For digital filtering. A device is known for calculating the decomposition coefficients of a function in a series containing the main and additional groups of keys, integrators, a Walsh function generating unit, a clock pulse commutator, a shift register. A characteristic feature of the device is the processing of the analog input signal and the formation of the decomposition coefficient, also in analog form Cl3. The drawbacks of the device are the low efficiency in processing the signal sequence and the impossibility of recovering the signal represented by the coefficients of the expansion according to the integral Walsh functions. A Walsh orthogonal transform device is known, comprising shift registers and subtractors. The device provides 1, 2, ...) conversion factors, and also calculates the current values of these coefficients t23. The disadvantage of the device is the impossibility of recovering the signal represented by the Walsh integral function decomposition coefficients. The closest to the invention to the technical essence is a device for converting to Walsh functions, containing adders, information signal commutators, adders-counters, pulse switch, ECU pulses the shift, the Walsh-Rademacher function shaping unit, the outputs of the Rademacher functions of which are connected to the control inputs of the information signal switch The inputs whose inputs are connected to the outputs of the adders, whose information inputs are combined and are the input of the device, the control inputs of the adders are connected to the Outputs of the corresponding shift register bits, the overflow output of which is connected to the control input of the clock switch, the first and second outputs of which are connected to the clock inputs of the shift register and the Walsh-Rademacher function block, respectively. The clock switch input is the device clock input. The output of the information signal switch is connected to the information inputs of totalizer readers, the control inputs of which are connected to the outputs of the corresponding functions of the Walsh-Rademacher function shaping unit, the outputs of totalizer totalizers are outputs of device 3. A disadvantage of the known device is the inability to perform the inverse conversion — the inability to recover the signal from coefficients of its decomposition in Walsh integral functions. The aim of the invention is to enhance the functionality of the device by enhancing the recovery of the signals represented by the expansion coefficients of the Walsh integral functions. The goal is achieved in that a device containing adders, an information signal switch, a shift register, a Walsh function generation unit and a clock switch, the first input of which is a clock input of the device, is a clock output of the clock switch of the pulse switch , the overflow output of which is connected to the control input of the clock switch, the second input of which is connected to the clock input of the Walsh function shaping unit, the information inputs of the sum The matrices are combined and are the information input of the device, the control inputs of the adders are connected to the outputs of the corresponding bits of the shift register, registers, direct binary code converters are added to the reverse, summing unit, the first and second adders with accelerated propagation of transfers, the buffer register and the trigger , moreover, the outputs of the adders are connected to the information inputs of the registers, input; reception control of which is connected and connected to the shift register overflow output, register outputs are connected to information inputs of direct binary code to return transducers, control inputs of which are connected to corresponding outputs of the Walsh function generating unit, outputs of direct binary code to reverse converters are connected with the inputs of the summing unit, the output of which is connected to the input of the first adder with the accelerated propagation of hyphenation, the output of which is the first output of the device and connected to the information input of the buffer register and the first input of the second adder with accelerated propagation of transfers, the second input of which is connected to the output of the buffer register and the second information input of the information signal switchboard, the first information input of which is connected to the output of the second putimator with accelerated propagation of transfers , the control input of the buffer register is connected to the second output of the clock switch, the clock and control inputs of which are connected by corresponding The first and second inputs of the trigger, the output of which is connected to the control input of the information signal switch, the output of which is the second output of the device, the control input of the shift register is the control inputs of the device. FIG. 1 shows a block diagram of the device; in fig. 2 is an electrical functional block diagram of a summing unit for the case of adding two-bit numbers in the additional code. An orthogonal Walsch transform device contains accumulative type adders, registers 2, direct binary code converters 3 inverse, a summing block n, the first 5 and second 9 adders with accelerated propagation of transfers, a switch 6 clock pulses, a shift register 7, a function shaping unit 8 Walls, buffer register 10, information signal switch 11, trigger 12, a control input, which is the control input 13 of shift register 7. The information inputs of the adders 1 are combined and are the information input of the device, the control inputs of the adders 1 are connected to the outputs of the corresponding bits of the shift register 7, the outputs of the adders 1 are connected to the information inputs of the corresponding registers 2, the control inputs of which are combined and connected to the overflow output of the register 7 shift, with the second input of the trigger 12 and with the control input of the switch 6 clock pulses, the clock input of which is the clock input of the device and connected to the first trigger input a 12. The codes of registers 2 are connected to the information inputs of the corresponding converters 3 of the forward binary code to the reverse one, the outputs of which are connected to the inputs of the summing unit 4, BBi, which is connected to the input of the first adder 5 with the accelerated propagation of hyphenation, the output of which is the first output of the device and connected to the input of the buffer register 10 and the first input of the second adder 9 with the accelerated spread of carries. The control inputs of converters 3 of the forward binary code to the reverse are connected to the corresponding outputs of the-8 Walsh function generation unit, the clock input of which is connected to the second output of the switch 6 clock pulses and to the control input of the buffer register 10 whose output is connected to the second input of the second adder 9 and with the second information input of the switch 11 information signals, the first input of which is connected to the output of the second adder 9 with the accelerated propagation of carries. The output of the trigger 12 is connected to the control of the input of the switch 11 of information signals, the output of which is the second output, oti of the device. The summing unit 4 for adding N p-bit numbers consists of one-bit three-input adders 14, each having three inputs and two outputs; amount and transfer. In FIG. 2, an electrical functional diagram of block 4 has been added for the case of the addition of four 5 two ity numbers: A, D, F and N.

The operation of the UN device on the mathematical definition of Walsh integral functions, which can be represented in TwiDe, to

P (i + 1, t) WaKi, Tr) dC, .. CH O. t T, i where i О, 1, 2, ...; P (0, t) - 1; , 5 Wal (i, t) - Walsh functions. For a discrete, data representation form, the transformation (1) can be written in the matrix form P WQ, (2)

where P is the matrix of integral functions, Walsh; W is the Walsh function matrix; (Q - Tepltzevtsev is an upper-angle matrix, the elements of which, including the main di-agonal, are equal to one. The coefficients i

Identical transformation - multiplication by the unit matrix E is introduced in order to more accurately reflect the processes occurring in the proposed device. Denote by B the vector of intermediate results: In WEC, X.

The device operates in two modes: direct and inverse transformation. In the decomposition mode of the input signal, the values of the process under study arrive at the input of the device in binary code in time with the clock pulses. These ordinates arrive at the information inputs of the adders 1, whose operation is controlled by the shift register 7. The control input of each szgmmator 1 is connected to its register bit 7 of the shift. So that the i-th adder is connected to the i-th bit of the register of the 7 shift. The control input 13 of the shift register 7 is fed 1, and its initial value is equal to

C. the decomposition of an arbitrary signal, represented by a set of ordinates X (i 1, ..., N), in a number of Walsh integral functions with regard to expression (2) is equal to С WQX,

Where

(-

- vector of decomposition coefficients;

X

the ordinate vector of the process under study;

N is the number of ordinates of the process under study.

The inverse transform is defined by the expression X, (, Teplicev Q, the inverse Q and the unit matrix E, looks like

10 ... for each clock pulse at the clock input of the shift register 7, its content is shifted by one bit to the right, and the freed bit is entered 1 from the control input 13 of the register 7. After the clock shift register 7 has come to the clock input, N clock pulses at the outputs adders 1 accumulate amounts corresponding to the product of process X by. matrix Q, at which time the shift register 7 generates an overflow pulse, according to which the values of the sums from the adders 1 are written to the registers

2 and which (when processing the first process) gives permission for the passage of clock pulses to the clock input of the Walsh function generation unit 8. After transferring amounts to registers

2 memory accumulators 1 accumulating type is reset to zero. The reset chains in FIG. 1 not shown. The ordinances of the next process being studied begin to arrive at the device input. The outputs of the Walsh functions of the block 8 control the operation of the converters 3 of the direct binary code, to the reverse: if the value of the Walsh function is + G, then the corresponding value from the register 2 is transmitted through the converter 3 in the forward code; if the value of the Walsh function is -1, then the contents of register 2 are transmitted in the reverse code. As a result, N products of the vector components of the sums stored in the registers 2 are sent to the discrete Walsh function. The sum of the 4 Walsh functions. is formed by the sum of the numbers arriving at its inputs in the form of a two-row code. The result of converting a two-code code to a single-digit one with the help of the first adder 5 with an accelerated spread of carries is proportional to the coefficient value for that function, whose value is currently present at the output of the block 8 Tempo of decompression coefficients of the input processes under study devices. In this case, the speed of the device in this mode is determined by the response time of the chain: converters 3 — summing unit 4 — first adder 5. In the inverse transformation mode — recovering signals by expansion coefficient by integral Walsh functions, the device operates as follows. The values of the decomposition coefficient of the recoverable process arrive at the input of devices in the binary code in time with the sync pulses. To the control input. 13 of the shift register 7 is applied O, and its initial value is 10 ... 0. for each clock pulse at the clock input of the shift register 7, its contents are shifted by one bit to the right., and the B-releasing bit is entered O from control input 13 of the register. After arrival at the clock input of the shift register 7 of the shift N, the sync pulse outputs of adders 1 appear the values of the decomposition coefficients, respectively. corresponding to the product of the vector of coefficients C. on the matrix E is the identical transformation, at which time the shift register 7 generates an overflow pulse, according to which the values of the coefficients from the adders 1 are rewritten into registers 2, and the trigger 12 is set to 1 ), which, when processing the first process, gives permission for the passage of clock pulses to the clock input of the Walsh function generation unit 8. After transferring the coefficients j-ro of the restored process to registers 2, the memory of adders 1 of accumulating type is reset to zero, and the coefficients () of the restored process begin to arrive at the input of the device. The outputs of the Walsh functions of the block 8 control the operation of the direct binary code converters 3 in the same way as in the direct conversion mode. Therefore, at the output of the first adder 5 with the accelerated propagation of carries, successively appear. . components b and vector In intermediate results. Let at the moment BpeMejiH device blocks be in the following state: in registers 2 - decomposition coefficients j-ro of the restored process, adders 1 and shift register 7 in the initial state, trigger 12 in state 1, on the outputs of block 8 are the sign-bearing function, and the output of the sum-, torus 5 is the value of the components b, c. the buffer register 10 is the value of the component b1; the output of the switch 11 of the information signals contains the value X from the register 10 due to the fact that the trigger 12 is in the unit state. The superscript indicates the number of the process being processed. With the arrival at the input of the device, the value of C accompanied by a clock pulse, the value of C is entered into the first (upper in Fig. 1) of adders 1, trigger 1.2 is zeroed, the contents of register 7 shift a is shifted one bit to the right, and to its left the bit is set to zero from the control input. According to the clock pulse at the second output of the switch, 6 clock pulses in the buffer register 10 is entered the value b | , and at the output of block 8, the value of the following Walsh function appears. After the transients are completed, the output of adder 5 is the value of b, which is subtracted with the help of adder 9 with the accelerated spread of hyphenation from the value of b stored in buffer register 10, the difference b | - L X. through the switch .11 information signals under the control of the zero signal from the output of three hera 12 will go to the second output of the device. The described sequence is repeated on the arrival of coefficients (1, 2, ..., N-1). With the arrival, accompanied by a sync pulse at the input of the device, the coefficient С fj value С jj is entered into the last of the adders 1, the value of X from the second output of the device. transmitted to the consumer. In the buffer register 10, the value of LX is entered at the outputs of block 8, the value of the sign-based Walsh function appears,

Ф14г.1 and the pulse of overflow from the output of register 7 Shift trigger 12 goes into one state, and the values of the decomposition coefficients (j4-l) -ro of the census process are recorded in registers 2, i.e. the device returns to the state in which it was at the beginning of its operation in this mode. Thus, the proposed device has enhanced functionality as compared to N10 with a known device, since with its help it is possible to carry out both direct and inverse transformation along Walsh integral functions.

Claims (1)

A device for orthogonal WALSH conversion, containing adders, a switch for information signals, a shift register, a Walsh function generation unit and a clock switch, the first input of which is a clock input of the device, the clock output of a clock switch connected to a clock input of a shift register, whose overflow output connected to the control input of the clock switch, the second output of which is connected to the clock input of the Walsh function generation unit, information input the adders are combined and are the information input of the device, the control inputs of the adders are connected to the outputs of the corresponding bits of the shift register, characterized in that, in order to expand the functionality of the device by performing the recovery of the signals represented by the expansion coefficients of the Walsh integral functions, it contains registers direct binary to reverse converters, summing block, first and second adders with accelerated hyphenation propagation, buffer register and a trigger, the outputs of the adders are connected to the information inputs of the registers, the reception control inputs of which are combined and connected to the overflow output of the shift register, the outputs of the registers are connected to the information inputs of the direct binary to the reverse converters, the control inputs of which are connected to the corresponding outputs of the Walsh function generation unit, the outputs of the direct binary to reverse converters are connected to the inputs of the summing block, the output of which is connected to the input of the first adder with radical propagation of transfers, the output of which is the first output of the device and connected to the information input of the buffer register and to the first input of the second adder with accelerated propagation of transfers, the second input of which is connected to the output of the buffer register and to the second information input of the information signal switch, the first information input of which is connected with the output of the second adder with accelerated propagation of transfers, the control input of the buffer register is connected to the second output of the switch clock, a clock and control inputs of which are respectively connected to first and second inputs of the flip-flop, whose output is connected to the control, the input switch information SU .... 1104527 signals, the output of which is the input input of the shift register is the second output of the device, controlling and controlling the input of the device. .