JPS6148038A - Zero detection of adder - Google Patents

Abstract

PURPOSE:To make possible a high-speed processing by detecting with separate means (complement on 1 or complement on 2) that an addition output is zero by the presence or absence of an initial carry. CONSTITUTION:When there is an initial carry, an output of a zero detection circuit (A)4 detecting that outputs of input control sections 1-a, 1-b are complements of 1 each other is ANDed at an AND gate 7. Then, through an OR gate 9, the result of the output of zero or not of an adder 2 is fed onto a zero detection line 13. When there is no initial carry, an output of a zero detection circuit (B)5 detecting that outputs of input control sections 1-a, 1-b are complements of 2 each other is ANDed at the AND gate 8. Then, through an OR gate, 9, the result of the output of zero or not of the adder 2 is fed onto the zero detection line 13.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides a high-speed zero detection method in a two-input adder. There is a method of creating a zero detection signal from the intermediate result of an adder (for example, Japanese Patent Laid-Open No. 55-87243). This means that the addition result is zero because both the addend and the summand are zero. The result of subtraction is zero by detecting that the subtrahend and minuend are equal in all of the bits, and the final output of the result of addition and subtraction is determined. This means that zero detection can be performed almost simultaneously.

However, the above conventional method has the following drawbacks. For example, when (+1)+(-1)=O is performed using a 4-bit adder, as shown in FIG.

A carry is output from the first bit of the adder, and the adder output becomes zero. In such a case, in the conventional method described above, if the operation is regarded as addition, zero cannot be detected because both the addend and the augend are not zero. Therefore, in order to detect zero, it is necessary to consider the addend (-1) to be the subtrahend (+1) and to set (+1)-(+1)=O.

Changing the addend (-1) to the subtrahend (+1) is to change the addend (-1
)~ is required, and a signal for detecting zero cannot be created until after this operation.

Generally, the operation of taking two's complement is achieved by inverting the data and adding 1 to the least significant bit.

A carry from the least significant bit may propagate to the most significant bit, and the propagation delay of the carry lookahead circuit in this case is , the number of gate stages is about the same or 1 to 2 stages less, so the delay time until this complement is obtained is at most 1 to 2 gate stages earlier than the output of the 2-input adder. This is the extent to which results can be obtained.

In this way, in the conventional method described above, zero detection during subtraction is slow;
It can only be obtained almost simultaneously with the adder output.

Incidentally, increasing the speed of zero detection in adders is becoming increasingly important in realizing high-speed processing.

For example, execute a certain instruction, create a condition code with the resulting zero detection result, and
In the case of a general sequence of instructions, where the next branch instruction determines whether to branch or not based on the code, it is desirable to be able to determine this condition code as early as possible.

This results in faster branch determination for the next branch instruction. Therefore, zero detection in the adder is required to be as fast as possible. In this way, the above-mentioned conventional method cannot be applied to high-speed processing where zero detection of the adder is required before the adder output is determined.

[Purpose of the invention]

An object of the present invention is to provide a zero detection method for a binary adder that can detect the zero of the adder at an earlier point in time than the time when the output of the adder is determined.6 [Summary of the Invention] Features of the Invention This means that in a two-input binary adder, the first detection means detects that two input data are in a one's complement relationship with each other, and the first detection means detects that two input data are in a two's complement relationship with each other. or both are zero, so that when there is an initial carry, the first detection means detects the initial carry without being conscious of whether the adder is performing an addition operation or a subtraction operation.・When there is no carry, the second detection means detects
It is designed to detect whether the adder output becomes zero or not.

[Embodiments of the invention]

FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, a two-input binary adder 2 has input control units 1-a and 1-b at each input, and an initial carry is given to the least significant bit of one input. ing. This initial carry is controlled by the initial carry control fi14 and the two-input binary adder 2.
The OR gate 6 performs an OR operation on the output of the register 3 (CAR) which holds the carry from the most significant bit of the signal. The OR output of this OR gate 6 is the zero detection circuit (A) 4
The inverted output of the OR gate 6 is ANDed with the output of the zero detection circuit (B) 5 and the AND gate 8.
And gated. The zero detection circuit (A) 4 is a circuit that detects that the outputs of the input control units 1-a and 1-b are in a one's complement relationship with each other. Zero detection circuit (B)
5 is a circuit that detects that the outputs of the input control units 1-a and 1-b are in a two's complement relationship with each other. The outputs of AND gates 7 and 8 are ORed by OR gate 9 to obtain zero detection.

The operation shown in FIG. 1 will be explained below. In addition operation,
Input control unit 1-a right and 1-b are connected to input data line 10.1
1 input data A and B are supplied as they are to a two-input binary adder (hereinafter simply referred to as an adder) 2, and in the subtraction operation, the input control unit 1-a supplies input data A as is to the adder 2, The input control unit 1-b counterclaims the input data B (
In addition, an initial carry is given to the least significant bit of adder 2. Adder 2 is input control section 1
The outputs of -a and 1-b and the OR output of OR gate 6 are added, the addition result is output to output data line 12, and the carry from the most significant bit is given to CAR3.

In this way, the adder 2 always performs only addition, and the addition/subtraction operations are controlled by the input control sections 1-a, 1-b and the initial carry. However, even if it is an addition operation of input data.

When the input data width is larger than the data ttJ of adder 2, for example, when adding 16 bytes of input data with an 8-byte [1] adder, the maximum width of adder 2 that occurs when adding the lower 8 nobates is Carry from upper bit (C
Since the AR output) is given as the initial carry when adding the upper 8 bytes, the initial carry is
Sometimes a carry is required.

Similarly, in subtraction, when the lower 8 bytes are subtracted, if there is no carry (CAR output) from the most significant bit of adder 2, the subsequent subtraction of the upper 8 bytes will use the inverted data of 1 input data B as the input data. Since it is added to A without an initial carry, there may be no initial carry even in a subtraction operation.

Therefore, in order to detect whether or not the output of adder 2 is A, the detection method should not be differentiated depending on the type of operation such as addition/subtraction of input data, but rather whether there is an initial carry or A. Therefore, it becomes necessary to use different detection methods.

If there is an initial carry, input control section 1-a
, l"b are in a one's complement relationship with each other. The outputs of the zero detection circuit (A) 4 are ANDed by the AND gate 7, and are passed through the OR gate 9 to the zero detection line 13 to the adder 2. It is detected whether the output of
In the case of the example in figure (a), the output (10
101010) and the output of lb (01010101) are in a one's complement relationship with each other.
When a carry is added, the output of adder 2 becomes zero.

Therefore, when there is an initial carry, it is possible to detect that the output of the adder 2 becomes zero by detecting that the outputs of the input control units 1-a and 1-b are in a one's complement relationship.

If there is no initial carry, the input control unit 1-a,
The output of the zero detection circuit (B) 5, which detects that the outputs of 1-b are two's complement numbers relative to each other, is ANDed by the AND gate 8, passed through the OR gate 9, and sent to the zero detection line 13 by the adder 2. It is detected whether the output of becomes zero. For example, the third
In the case of figure (b), the output of the input control unit 1-a (10101
010) and the output of 1-su (01010110) are the same ν
) have a two's complement relationship, and when the initial carry value O is added to these, the output of adder 2 becomes zero.

Therefore, when there is no initial carry, it is possible to detect that the output of the adder 2 is zero by detecting that the outputs of the input control units 1-a and 1-b are in a two's complement relationship with each other.

A zero detection circuit (A) 4 detects that the outputs of the input control units 1-a and 1-b are one's complement numbers.

The data is 1118 bytes (bit IIJ 64 bits).

The output of the input control unit 1-a is a...al・"' a R
j・The output of the input control unit 1-b is bLllbl+...b
When it is closed at 8 degrees, AouL= (a + l '■b1+)'' (a+■b+
)(a,,■b7)...(a8.■b,,-4) However, al■b1 is the exclusive OR of al and b5, (a+
■b) - (aa■bJ) is (at■b,) and (a''■b
, ) can be realized with a circuit that satisfies the logical product logic formula. Similarly.

A zero detection circuit (B) 5 detects that the input control units 1-a and 1-b are two's complement numbers.

BouL=(ar+ + bt+)” (a++
b+)・(at+L)”...(aMM+
b,,*) +(a,, +br+)・(at+b+)・
(ax + b7)...=' (ag z + bn
3) + (a n■b,,)・(a, +b, )(a,
+b,,)・-・(a,,* tensu, 3) +(a,,■b1,)(a,■b,)・<at, +b
,, ＞・Caq +bl )・”” (aFl* +
ba s ) +(an■b,,)・(a,■bI)・(a7■b2)
...'(all,■b,,2)・(a8.・b81
) However, (allbt) is the negative disjunction of a and b (a
4.a, +) can be realized with a circuit that satisfies the logical product of aJ and bJ.

When the 2-input binary adder 2 is an 8-byte TIJ adder, the number of gate stages is The number of stages is 4 to 5, which is the same number of stages as the carry created by the carry lookahead circuit, and the delay time thereof is also approximately the same. Therefore, the zero detection of the adder 2 is detected at the same time as the carry.

Since the final output of the adder 2 is obtained one or two stages after this carry, it is possible to detect whether or not it is zero at an earlier point in time than the final output of the adder.

〔Effect of the invention〕

According to the present invention, it is possible to detect whether the output of the adder becomes zero earlier than the time when the output of the adder is determined, so that the operation of the next step can be started before the operation of the adder ends. It becomes possible to start up the computer, perform faster processing, and improve the processing performance of the computer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing an example in which a carry is output from the first bit of an adder and the adder output becomes a blade, and FIGS. 3(a) and (b) ) is a diagram showing an example of zero detection according to FIG. 1. 1-a, lb...input control section, 2...2 input 2
Decimal adder, 3... Carry holding register. 4.5...Zero detection circuit. Figure 1 2nd shift 10-year-old man's fault Figure 2 o o o + (+) 10 seaney earth - Woni + (-) 1 (★Yarii) Figure 3 (α) 10+O+ (zo ,,, public 010+ olol, , cr), force +
ini′>1ruk
k? 1) 1(b) 10101010 1-α. Yin force 01010110 1-b=n*+
0 Inishano V Imamisaki Noi I 0 Tarii)

Claims (1)

[Claims] (1) In a method for detecting whether the calculation result of a two-input adder is zero, a first detection means for detecting that two input data of the adder are in a one's complement relationship with each other; , a second detection means for detecting that two input data are in a two's complement relationship with each other, and when there is an initial carry in the operation of the adder, the first detection means detects the initial carry. A zero detection method for an adder, characterized in that when there is no carry, the second detection means detects whether or not each operation result is zero.