JPH02304621A - Detecting circuit for equivalence of logical value - Google Patents

Abstract

PURPOSE:To reduce the number of input pieces of the detecting circuit and to efficiently execute the pattern design by providing an all '0' detecting circuit for inputting the output of an encoder for detecting the normalization quantity and the most significant bit of a mantissa. CONSTITUTION:This circuit is constituted by providing an all '0' (or all '1') detecting circuit 11 consisting of an AND circuit 12 and an inverter 13 inserted through a code bit line. In this constitution, the output D of a shift quantity encoder 1 detects how long the same value is continued from a code bit (MSB). In this state, in the case the output D is all '1', that is, the result of operation (mantissa of a floating point) A is all '0' (code bit C is also '0'), the flag of '1' is set to the output B of the circuit 11. When such a '0' detection is executed, no normalization is executed. In such a manner, the output of the result of operation (mantissa) is (n) bits, (log 2N) + 1 including one piece of the code bit becomes the number of input pieces to the circuit 11, the number of input pieces decreases and a pattern design can be executed efficiently. The larger the number of (n) is, the more useful it becomes.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) The present invention provides a normalization amount detection method for normalizing the addition and subtraction results of the mantissa part of a floating point arithmetic circuit. @0
The present invention relates to a circuit for performing 1 detection and @11 detection.

(Conventional technology) A conventional 1110m detection circuit of this type is shown in FIG.

This circuit is a floating point arithmetic unit or the like, and a NOR circuit 2 detects that the operation result (mantissa part) A to the shift amount encoder 1 becomes "O".

(Problem to be solved by the invention) In general, @01 detection is performed when the calculation result A is N
This was done by taking the OR. That is, when all the pits of the operation result (mantissa part) A become "Om", all the inputs of the NOR circuit 2 become "0#" fi, and the output B of the NOR circuit 2 becomes @l
``@0'' detection can be performed.

However, in this case, as the number of pits in the operation result (mantissa part) A increases, the number of inputs to the NOR circuit 2 increases,
・Medium turn area increases.

The purpose of the present invention is to provide the output of the shift amount encoder and the sign pit (the most significant bit of the mantissa part) which are essential for floating point operations.
is used to perform @0'' detection or Fi@t' detection of the mantissa part, thereby solving the above-mentioned drawbacks of the conventional method.

[Structure of the Invention (Means and Effects for Solving the Problems) The present invention provides an equivalence detection circuit for the logic value of an encoder input for normalization amount detection for normalizing the addition and subtraction results of the mantissa part of a floating point arithmetic circuit. Input the output of the encoder and the most significant pit of the mantissa as input, and write 9all'''Om.
Alternatively, the present invention is a logical value equivalency detection circuit characterized by comprising an all "1" detection circuit.

That is, in the present invention, when the output (mantissa part) of the arithmetic unit is n pits, togz n plus one sign pit (most significant bit of the mantissa part), that is, f'' (Log2 n) + lJ, all @0. The number of inputs to the # or all 11" detection circuit is reduced, and the area efficiency is improved due to the thin turn design.

(Example) The present invention will be described in detail below with reference to the drawings. #C1 is a block diagram of the same embodiment, and parts corresponding to those in FIG. 3 are given the same reference numerals. Figure 1 (a) is a block configuration diagram, and Figure 1 (b) is the all @0 diagram in Figure 1 (a).
1 is a detailed diagram of the detection circuit 1.

In the figure, C is the code (MsB), and D is the encoder output. The all "1" detection circuit 11 in pJ1 figure (b) consists of an AND circuit 12 and an inverter 1 inserted in the sign bit line.
It has 3.

The encoder 1 (shift) is essential for floating point operations. This shift amount encoder is necessary for data normalization, etc., so that the data after normalization is l? ), 1xxxXXJ.

rl, oxxxxxxJ (here, "X"Fi"l" or @O# may be used) to indicate the shift amount of data. And the output of the shift amount encoder is
It is detected whether the same value continues h times starting from the MSB.

For example, if ro, o 01 xxxxxxJ (this M
SB corresponds to "0m" to the left of the decimal point), and the output of encoder/1 is "2", that is, roloJ (it is necessary to shift two more digits).

In Figure 1, the output of encoder 1 is all
# That is, the operation result (floating point mantissa part) A is all 10
1 (code pit C4, “O”), all “1”
A flag is set for the output nVc@t'' of the detection circuit 11.If such @0'' is detected, for example, even if normalization is performed, it will only waste time.
No normalization is included.

FIG. 2 shows another embodiment of the present invention (al is a block diagram, and FIG. 2(b) is a detailed diagram of the all-1 bit detection circuit 21 in FIG. 2(a). Even if the outputs of the encoder l are all @1'', that is, when the calculation result A is all ``1'' (the code pit C is also ``l''), the output BK of the all 111 detection circuit 2 is The flag “@l” is set.

[Effects of the Invention] As explained above, according to the present invention, the output of the shift amount encoder is input to the @o't or 11m detection circuit, so the output of the operation result (mantissa part) is n bits. In the case of r (tog2 n ) including i number of code pits,
+IJ@O#i#f-1' The number of inputs to the detection circuit is reduced, and pattern design can be performed efficiently. This is useful when the number of rice fields is large.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a block diagram of another embodiment of the present invention, and FIG. 3 is a block diagram of a conventional device. 1...Shift amount encoder, 11...All @o"
Detection circuit, 21... All "1" detection circuit. Applicant's agent Patent attorney Takehiko Suzue Calculation result A B °"0"" detection output Figure 3

Claims (2)

[Claims] (1) In a logic value equivalency detection circuit of the encoder input for normalization amount detection for normalizing the addition/subtraction result of the mantissa part of the floating point arithmetic circuit, the output of the encoder and the most significant bit of the mantissa part are input. What is claimed is: 1. A logic value equivalence detection circuit characterized by comprising an all "0" detection circuit. (2) In a logic value equivalency detection circuit of the encoder input for normalization amount detection for normalizing the addition/subtraction result of the mantissa part of the floating point arithmetic circuit, the output of the encoder and the most significant bit of the mantissa part are input. What is claimed is: 1. A logic value equivalence detection circuit characterized by comprising an all "1" detection circuit.