JPH03164930A - Detection system for exception to overflow - Google Patents

Abstract

PURPOSE:To detect an exception of overflow at high speed by providing a substituting means which substitutes each digit of an insignificant digit part of an operand for '1001' and each digit of a significant digit part for '0000', respectively. CONSTITUTION:A replacement circuit 9 replaces an insignificant digit part and a significant digit part of an operand with '1001' and '0000' respectively. When the insignificant digit of a 2nd operand is masked by a mask circuit 4 and supplied to a register 17, the value of the register 17 is added to the output of the circuit 9 selected by a selector 13 via a decimal computing element 14. The result of this addition is stored in the register 17. In this case, no carry is produced and therefore 0 is stored in a register 16. At the same time, the insignificant digit of a 1st operand is masked by the circuit 4 and stored into a register 12. Then the output of the register 12 selected by the selector 13 is added to the output of the register 17. If a carry is produced, an exception detecting circuit 15 detects an exception. Thus an exception of overflow can be detected at high speed.

Description

TECHNICAL FIELD The present invention relates to an overflow exception detection method, and more particularly to an overflow exception detection method when calculating variable length decimal data.

Prior Art A conventional example of this type of overflow exception detection is shown in FIG. 3, and FIG. 4 is an operation time chart thereof. The operand supplied here is data in decimal packed format consisting of a sign part and an absolute value part, as shown in FIG.

One digit of the absolute value part is 4 bits, from 0000 (2) to 10
Expressed as a number up to 01 (2). Starting from the right digit, the numbers are digitized into the 100's, 10', . . . , 10'', and 1()'', and the absolute value of the decimal number is expressed using a maximum of 15 digits.

It is not possible to change the data width of a register or arithmetic unit in accordance with the data length of variable-length decimal data. In other words, although variable length decimal data is variable length, hardware that handles variable length decimal data is not variable length. Therefore, the variable length decimal data supplied to the hardware is always fixed length, and the actual variable length decimal data part is regarded as valid digits, and the part supplied for hardware reasons is regarded as invalid digits. I'm handling it.

The data length g is used to determine the valid and invalid digits of variable length decimal data, and the data length g is expressed with one decimal digit as the middle digit, and if the valid digits are up to the 103rd digit, then N
If the -4th and 10th digits are significant digits, g=12.

In the figure, 21 is an invalid digit indicating circuit that calculates the invalid digit part from the supplied data length g and instructs the part of the operand to be masked, and 24 is a mask that masks the invalid digit of the operand to "oooo". 26 is a comparator that compares the absolute values of the operands; 27 is an arithmetic control circuit that controls the decimal arithmetic unit 33 and determines the sign of the arithmetic result; 33 is the decimal arithmetic unit; and 36 calculates the significant digits of the arithmetic result. 37 is a comparison circuit that checks whether the significant digits of the calculation result overflow, and 38 is an exception detection circuit that detects an overflow exception.

Note that 22.23, 25.28 to 35.39 are registers.

On the apparatus shown in FIG.
Consider the case where a base addition instruction is executed. Here, an overflow exception occurs when the effective digits of the operation result are greater than gl.

- As an example, the first operand is -3524 (In) and the data length is 111 = 4. The second operand is +15241 (
In) The data length is g2-5. The second operand is supplied to the register 23 in the form shown in FIG. 6(A).

It doesn't matter what kind of data you put in the invalid digits marked with an X.

The invalid digit indicating circuit 21 determines the data length of the second operand ρ2=
5, “11111111110000” is stored in register 22.
0'' is output. Each bit corresponds to one digit of the decimal operand supplied to the register 23, and 1 is set in the digit to which the zero mask is applied.

At timing to shown in the time chart of FIG. 4, the second operand is set in the register 23, and the invalid digit indication information of the second operand is set in the register 22, respectively. The absolute value part of the second operand of the register 23 is sent to the mask circuit 24.
According to the instructions of the register 22, the invalid digits are zero-masked and set in the register 25 in the form shown in FIG. 6(B).

Also, the first operand is in register 2 in the form shown in Figure 6(C).
3.

Invalid digit indicating circuit 2] determines the data length g1- of the first operand.
4, to register 22" +11111111110
ooo” is output.

At the timing tl shown in the time chart of FIG. 4, the second operand with invalid digits zero-masked is set in the register 25, the first operand is set in the register 23, and the invalid digit instruction information of the first operand is set in the register 22. Ru.

The absolute value part of the first operand of the register 23 is zero-masked at the invalid digit part by the mask circuit 24 according to the instruction of the register 22, and is outputted in the form shown in FIG. 6(D).

The output of the mask circuit 24 and the absolute value part of the register 25 are compared by a comparator 26, and it is reported to the arithmetic control circuit 27 that the absolute value part of the register 25 is larger.

The arithmetic control circuit 27 outputs the sign of the sign part of the register 25, ie, +, as the sign of the arithmetic result, since the sign part of the register 923.25 has a different sign and the absolute value of the register 25 is larger. It also instructs the decimal arithmetic unit 33 to subtract the output of the register 31 from the output of the register 32.

At timing t2 shown in the time chart of FIG. 4, the output of the register 22, that is, the invalid digit information of the first operand, is sent to the register 28, the control information of the decimal operator 33 is sent to the register 29, and the control information of the decimal arithmetic unit 33 is sent to the register 3. The sign of each operation result is set. Further, the output of the mask circuit 24 is set in the register 31, and the output of the register 25 is set in the register 32, respectively.

According to the instruction from the register 29, the absolute value part is calculated by the 1o-adic calculation unit 3-3. The calculation result shown in FIG. 6(E) is stored in the register 32. At this time, since no carry occurs, O is set in the register 35.

At timing t3 shown in FIG. 4, the absolute value part of the operation result is set in the register 32, and the carry is set in the register 35. Registers 28.30 are held.

The significant digit calculation circuit 36 calculates the significant digits from the value of the register 32. ]If the first digit of O-adic is 0, outputs 0, and if it is other than O, outputs 1. In other words, “ooo.

00000011111” is output.

The comparison circuit 37 inverts the output of the significant digit calculation circuit and the output of the register 28, that is, "000 yen 0000001".
111", and it is reported that the significant digit of the absolute value of the operation result of the register 32 is larger.

The exception detection circuit 38 detects an exception based on the detection result of the comparison circuit 37 and the carry of the register 35.

In this case, an exception is reported because it is reported that the significant digits of the absolute value of the operation result are greater than the significant digits of the first operand. When referring to the carry in the register 35, for example, the first operand is in the form shown in FIG. 6(F), the data length g1=15, and the second operand is in the form shown in FIG. 6(G). The absolute value part of the operation result when the data length is Q 2 =15 is shown in FIG. 6 (H), and the comparator circuit 37 does not detect an overflow exception. However, since a carry is actually generated by the absolute value operation, an overflow exception occurs. In order to detect such a case, the exception detection circuit 38 uses the register 35.
It also refers to the carry of

At timing t4 not shown in the time chart of FIG. 4, the absolute value of the calculation result of the register 32 and the sign of the register 30 are set in the register 34.

An overflow exception is set in register 39.

In the conventional overflow exception detection method for variable-length decimal data described above, a dedicated significant digit calculation circuit 36 and a comparison circuit 37 are required, and an overflow exception cannot be detected until after the calculation is completed. There is a drawback.

A second object of the present invention is to provide an overflow exception detection method that can further speed up the detection of overflow exceptions while reducing the amount of hardware.

According to the present invention, there is provided an overflow exception detection method for a data processing device having arithmetic means for performing addition and subtraction processing on first and second operands which are arcuate length decimal data, the method comprising: Set each digit in the digit part to “1001”,
Further, a substitution means is provided for replacing each digit of the significant digit part with "oooo", and the significant digit of the second operand and the output of the substitution means are added together by the arithmetic means. The significant digits and the significant digits of the second operand are subjected to addition/subtraction processing by the arithmetic means based on the signs of both operands, and the first and second operands are added/subtracted based on the signs of both operands, and the first and second operands are added/subtracted according to the results of the addition process and the carry and boro outputs of the results of the addition/subtraction process. An overflow exception detection method characterized by detecting an overflow exception of the second operand is obtained.

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 shows a time chart I for explaining the operation of FIG. 1.

In FIG. 1, 1 is an invalid digit indicating circuit that calculates the invalid digit part from the supplied data length Ω and instructs the part of the operand to be masked, and 4 is the invalid digit part of the operand that
7 is a comparator that compares the absolute values of operands, 8 is an arithmetic control circuit that controls the decimal arithmetic unit 14 and determines the sign of the operation result, and 9 masks the invalid digits of the operands to "1001". 13 is a selector that selects the value of the conversion circuit 9 or register]2, 14 is a decimal arithmetic unit, and 15 is an exception detection circuit that detects an overflow exception. It is.

Note that 2, 3, 5, 6, 1.0 to 1.2, 16 to 19 indicate registers.

0 As described in the prior art, it is assumed that a decimal addition instruction is executed in which the sum of the second operand and the first operand is placed in the first operand's place. We will classify and consider the following three cases.

(1) When the first and second operands have the same sign, (2) When the first and second operands are different and the absolute value of the second operand is larger, (3) When the first operand
If the operand and second operand have different numbers and the absolute value of the first operand is greater, or the absolute value of the first and second operand is equal, an overflow exception can occur in cases (1) and (2). However, in case (3), the absolute value of the operation result cannot be greater than the absolute value of the first operand, so an overflow exception cannot occur.

First, case (1) will be explained. The first operand is +5473 (10) and the data length β1=4. Assume that the second operand is +7828 (10) and the data length is g2-4. At the timing to shown in FIG. 2, the second operand is supplied to the register 3 in the form shown in FIG. 7(A). Register 2 contains invalid digit instruction information “000000000 entry 011
11” is stored.

At the timing tl shown in FIG. 2, the first operand is supplied to the register 3 in the form shown in FIG. 7(B). register 2
Invalid digit instruction information “011000000000111
1" is stored. The sign of the second operand is stored in the register 5. The sign of the second operand is stored in the registers 6 and 17, and the invalid digits are masked by the mask circuit 4.
) is supplied in the form of

At timing t2 shown in FIG. 2, the value of the register 17 and the output of the switching circuit 9 selected by the selector 13 and shown in FIG. The result of the calculation, shown in FIG. 7(E), is stored in the register 17. At this time, since no carry occurs, 0 is stored in the register 16. register 1
2, the first operand stored in the register 3 is masked with invalid digits by the mask circuit 4, and is stored in the form shown in FIG. 7(F)2.

A comparator 7 compares the output of the mask circuit 4 and the output of the register 6, and reports the result to the arithmetic control circuit 8. Since the first and second operands have the same sign, the arithmetic control circuit 8 instructs the decimal arithmetic unit 14 to add the absolute values and also instructs the sign of the arithmetic result. 1 in register 10
The control information of the 0-base arithmetic unit 14 and the sign of the operation result are stored in the register 11, respectively.

At timing t3 shown in FIG. 2, the output of the register 12 selected by the selector 13 and the output of the register 17 are added according to an instruction from the register 10. As a result, the signal shown in FIG. 7(G) is output and a carry occurs. Exception detection circuit 1
5, an exception is detected based on the instruction of the register 10 based on the output of the register 16 and the carry of the decimal arithmetic unit 14.

Since the register 10 instructs to detect an exception, the exception is detected and the detection result is stored in the register 18.

In this case, an overflow exception is detected. register 1
9, the output of register 1] and decimal operation] 3 +31 in FIG. 7 (H), which is the operation result from the output of register 14.
01 (10) is stored.

Next, case (2) will be explained. The first operand is +284 (1,0), the data length g1-3, the second operand is -1204 (1 unit), and the data length β2=4. At the timing to shown in FIG. 2, the second operand is supplied to the register 3 in the form shown in FIG. 8(A). Register 2 contains invalid digit instruction information “000 flooooooll
l'' is stored.

At the timing tl shown in FIG. 2, the first operand is supplied to the register 3 in the form of fJX8 (B). Register 2 contains invalid digit instruction information' [10(+(In(1(+
00 (100111'' is stored. Register 5 stores the sign of the second operand. Registers 6 and 1
7, the second operand of the register 3 is supplied with invalid digits masked by the mask circuit 4 in the form shown in FIG. 8(C).

At timing t2 shown in FIG. 2, the value of the register 17 and the output of the switching circuit 9 (D) in FIG. The calculation result shown in FIG. 8(E) is stored in the register 17.

The generated carry is stored in register 16.

The first operand stored in the register 3 is stored in the register 12 by a mask circuit 4, with invalid digits being masked, and as shown in FIG.
) is stored in the form.

A comparator 7 compares the output of the mask circuit 4 with the output of the register 6, and reports the result to the arithmetic circuit 8.

The arithmetic control circuit 8 uses the decimal arithmetic unit 1 because the two operands have different signs and the absolute value of the register 6 is larger.
4, an instruction is issued to subtract the output of the selector 13 from the output of the register 17. Control information for this decimal arithmetic unit 14 is stored in register 1o. Further, the sign of the calculation result is determined to be - by the calculation control circuit 8, and is stored in the register 11.

At timing t3 shown in FIG. 2, the output of the register 12 selected by the selector 13 is subtracted from the output of the register 17 according to the instruction of the register 10. As a result, the 8th
Figure (G) is output and a borrow occurs.

5. The exception detection circuit 15 detects exceptions according to instructions from the register 10. The carry stored in register 6 and 10
The borrow output from the decimal operator 14 is canceled out, and no overflow exception is detected. The detection result is stored in the register 18. The register 19 receives the operation result -920 (1
0) is stored. FIG. 8(H) shows the calculation result.

Finally, case (3) will be explained. The first operand is ÷8428 (10) and the data length g1=4. The second operand is -7834 (10) and the data length is 112-4. At the timing of to shown in FIG. 2, the second
Operands are provided in the form of FIG. 9(A). Register 2 contains invalid digit instruction information “oooooooo.”

00001111" is stored.

At the timing tl shown in FIG. 2, the first operand is supplied to the register 3 in the form shown in FIG. 9(B). register 2
Invalid digit instruction information “oooooooooo.”

01111'' is stored in the register 5.The sign of the second operand is stored in the register 5.The sign of the second operand is stored in the registers 6 and 1]67 as shown in FIG. ) is supplied in the form of

At timing t2 shown in FIG. 2, the value of the register 17 and the output of the switching circuit 9 (D) in accordance with the instruction of the register 2, selected by the selector 13, are added by the arithmetic unit 14. , FIG. 9(E) are stored in the register 17.

In this case, since no carry occurs, O is stored in the register 16. The first operand stored in the register 3 is stored in the register 12 in the form shown in FIG. 9(F) with invalid digits masked by the mask circuit 4.

A comparator 7 compares the output of the mask circuit 4 and the output of the register 6 and reports the result to the arithmetic control circuit 8. Since the two operands have different signs and the absolute value of the register 6 is smaller, the arithmetic control circuit 8 uses the decimal arithmetic unit 14.
An instruction to subtract the output of the register 17 from the output of the selector 13 is issued.

Control information for this decimal arithmetic unit 14 is stored in the register 10. Further, the arithmetic control circuit 8 determines that the sign of the arithmetic result is 10, and stores it in the register 1].

At timing t3 shown in FIG. 2, the output of register]7 is subtracted from the output of register 12 selected by selector 13 according to the instruction of register 10. The result of the subtraction is shown in FIG. 9 (G), and a borrow occurs.

The exception detection circuit 15 detects an exception according to instructions from the register 10. If the first and second operands have different signs and the absolute value of the first operand is greater, or if the absolute values of the two operands are equal, no overflow exception occurs.

That is, register 10 is instructed to output that no overflow exception has been detected. Exception detection circuit 15
The output of is stored in register 18.

The operation result +0592 (10) is stored in the register 19 from the output of the register 11 and the output of the 1o-adic arithmetic unit 14. FIG. 9(H) shows the calculation result.

Effects of the Invention As described above, according to the present invention, prior to the actual operation, each of the invalid digits of the first operand is replaced with "100bi8", and each of the significant digits is replaced with 'oooo'. Mask data for the overflow detection vehicle is generated in advance, and the result of addition of this overflow detection mask data and the significant digit of the second operand is carried, and the first . Addition/subtraction of significant digits of the second operand; Song carry (or borrow)
This has the effect that an overflow exception of the addition/subtraction result can be detected at high speed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a time chart showing the operation of the blocks in Fig. 1, Fig. 3 is a block diagram showing the prior art, and Fig. 4 is a block diagram of the blocks in Fig. 3. 5 is a chart showing the decimal variable length data format. FIG. 6 is a chart showing the contents of each register for each operation timing of the block in FIG. 3. FIGS. The contents of each register for each operation timing of the block in Figure 1 are as follows:
FIG. 6 is a diagram showing each relationship between the first and second operands. Explanation of symbols of main parts 1...1 invalid digit indicating circuit] 4...Mask circuit 7...Comparator 8...Arithmetic control circuit 9... Conversion circuit 4... Decimal calculation circuit 5... Exception detection circuit

Claims (1)

[Claims] (1) An overflow exception detection method for a data processing device having arithmetic means for performing addition/subtraction processing on first and second operands that are variable length decimal data, wherein each digit of an invalid digit portion of the first operand is 1001" and each digit of the significant digit part to "0000", the significant digits of the second operand and the output of the replacing means are added together by the arithmetic means, and then the The significant digits of the first operand and the significant digits of the second operand,
Addition and subtraction processing is performed by the arithmetic means based on the signs of these two operands, and overflow exception detection of the first and second operands is performed in accordance with carry and borrow outputs of the addition processing results and the addition and subtraction processing results. Overflow exception detection method.